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JPH021371B2 - - Google Patents
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JPH021371B2 - - Google Patents

Info

Publication number
JPH021371B2
JPH021371B2 JP57133928A JP13392882A JPH021371B2 JP H021371 B2 JPH021371 B2 JP H021371B2 JP 57133928 A JP57133928 A JP 57133928A JP 13392882 A JP13392882 A JP 13392882A JP H021371 B2 JPH021371 B2 JP H021371B2
Authority
JP
Japan
Prior art keywords
lsi
film carrier
film
positioning
carrier lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57133928A
Other languages
Japanese (ja)
Other versions
JPS5923555A (en
Inventor
Masayuki Higuchi
Masahiro Higami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP57133928A priority Critical patent/JPS5923555A/en
Publication of JPS5923555A publication Critical patent/JPS5923555A/en
Publication of JPH021371B2 publication Critical patent/JPH021371B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65Shapes or dispositions of interconnections
    • H10W70/657Shapes or dispositions of interconnections on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688Flexible insulating substrates

Landscapes

  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は、フイルム上に、機器(電子式卓上計
算機等)の演算部等を構成するLSIチツプ、外部
接続端子(電源端子、キー信号入出力端子、表示
信号出力端子等)及び上記LSIチツプと外部接続
端子間を電気的に接続する配線を設けたフイル
ム・キヤリヤLSIの実装方法に関するものであ
る。
Detailed Description of the Invention (Technical Field) The present invention provides an LSI chip, external connection terminals (power supply terminal, key signal input/output terminal, The present invention relates to a method for mounting a film carrier LSI in which a display signal output terminal, etc.) and wiring for electrically connecting the LSI chip and external connection terminals are provided.

(発明の目的) 本発明は、上記フイルム・キヤリヤLSI取り付
け時の位置決めを簡単化することを目的としてな
されたものである。
(Object of the Invention) The present invention has been made for the purpose of simplifying the positioning when installing the above-mentioned film carrier LSI.

(発明の概要) 上記目的を達成した本発明の実装方法の概要は
以下のとおりである。すなわち、本発明のフイル
ム・キヤリヤLSIの実装方法は、フイルム上に、
LSIチツプ、外部接続端子及び上記LSIチツプと
外部接続端子間を電気的に接続する配線を設けた
フイルム・キヤリヤLSIの実装方法に於て、上記
フイルムの所定位置に、フイルム送り用のスプロ
ケツトホールとは別にいずれの組も少なくとも2
個の穴からなる2組の位置決め用穴を形成し、実
装する機器キヤビネツトの構造にあわせて上記い
ずれかの組の位置決め用穴を択一的に残して上記
フイルムからフイルム・キヤリヤLSIをカツテイ
ングし、上記位置決め用穴と機器キヤビネツトに
設けられる位置決め用ピンとの係合により、上記
フイルム・キヤリヤLSI取り付け時の位置決めを
行う構成としたことを特徴とするものである。
(Summary of the Invention) An outline of the implementation method of the present invention that achieves the above object is as follows. In other words, the method for mounting the film carrier LSI of the present invention includes:
In a method of mounting a film carrier LSI that includes an LSI chip, external connection terminals, and wiring for electrically connecting the LSI chip and the external connection terminals, a sprocket hole for film feeding is installed at a predetermined position on the film. Apart from that, each group has at least 2
Two sets of positioning holes are formed, and the film carrier LSI is cut from the film, leaving one of the sets of positioning holes selectively left in accordance with the structure of the equipment cabinet to be mounted. The present invention is characterized in that the positioning of the film carrier LSI is performed by engagement of the positioning hole with a positioning pin provided in the equipment cabinet.

(実施例) 以下、実施例を説明する。(Example) Examples will be described below.

第1図は、フイルム・キヤリヤLSIの供給状態
を示す斜視図である。図に於て、1はフイルム・
キヤリヤLSI、2はフイルム・キヤリヤLSI1が
巻き付けられているリールである。
FIG. 1 is a perspective view showing the state of supply of the film carrier LSI. In the figure, 1 is a film.
Carrier LSI 2 is a reel around which film carrier LSI 1 is wound.

第2図はフイルム・キヤリヤLSI1の詳細な構
成を示す平面図である。
FIG. 2 is a plan view showing the detailed structure of the film carrier LSI 1.

図に於て、3はフイルム、4はLSIチツプ、
5,6は電源端子(電池と接続される)7は発音
体接続端子、8はキー信号入出力端子及び表示信
号出力端子、9は上記LSIチツプ4と各端子間を
電気的に接続する配線、10はフイルム3の位置
決め及び送り用に使用されるスプロケツトホール
である。そして、11,12が本発明に係る、フ
イルム・キヤリヤLSI実装時の位置決め用穴であ
る。
In the figure, 3 is a film, 4 is an LSI chip,
5 and 6 are power supply terminals (connected to batteries) 7 is a sounding body connection terminal, 8 is a key signal input/output terminal and a display signal output terminal, and 9 is a wiring that electrically connects the LSI chip 4 and each terminal. , 10 are sprocket holes used for positioning and feeding the film 3. Reference numerals 11 and 12 are positioning holes when mounting the film carrier LSI according to the present invention.

リール2より順次供給されるフイルム・キヤリ
ヤLSI1を、組み込むべき機器の構造に応じて、
第3図に点線で示す形状Aまたは第4図に点線で
示す形状Bに打ち抜き、例えば第5図(断面図)
に示す構成で機器キヤビネツトに実装する。な
お、第5図は電子式卓上計算機(以下「電卓」と
いう)の場合の例を示すものである。すなわち、
フイルム3に2組の位置決め用穴を予め設けてお
き、組み込むべき機器の構造により、いずれか一
方を選択使用するようにしている。これにより、
同一構成のフイルム・キヤリヤLSI1を、カツテ
イング・パターンを変えるだけで異なる構造の機
種にも適用可能となる。
The film carrier LSI 1 sequentially supplied from the reel 2 is installed according to the structure of the equipment to be installed.
Punching into shape A shown by the dotted line in Fig. 3 or shape B shown by the dotted line in Fig. 4, for example Fig. 5 (cross-sectional view)
Install it in the equipment cabinet with the configuration shown below. Note that FIG. 5 shows an example of an electronic desktop calculator (hereinafter referred to as "calculator"). That is,
Two sets of positioning holes are previously provided in the film 3, and one of them is selected and used depending on the structure of the equipment to be incorporated. This results in
Film carrier LSI 1 with the same configuration can be applied to models with different structures by simply changing the cutting pattern.

第5図に於て、13はキヤビネツト、14はキ
ートツプ、15は導電ゴムスプリング、16はキ
ー配線シート、17はフイルム・キヤリヤLSI、
18は表示素子(TN−FEM LCD)である。キ
ー配線シート16の端部いは、フイルム・キヤリ
ヤLSI17の表示信号出力端子と表示素子18の
端子間を電気的に接続するための配線も形成され
ており、該端部を円柱状の弾性体19に巻き付け
て、表示素子18とフイルム・キヤリヤLSI17
との間に挾み込む構成とすることにより、キー配
線とLSI17間の接続と同時に、表示素子18と
LSI17間の接続も達成される。20は押え板、
21は固定用のビス、22は底パネルである。ま
た、23は電源となる電池、24は電池端子であ
る。
In FIG. 5, 13 is a cabinet, 14 is a key top, 15 is a conductive rubber spring, 16 is a key wiring sheet, 17 is a film carrier LSI,
18 is a display element (TN-FEM LCD). Wiring for electrically connecting between the display signal output terminal of the film carrier LSI 17 and the terminal of the display element 18 is also formed at the end of the key wiring sheet 16, and the end is connected to a cylindrical elastic body. 19, display element 18 and film carrier LSI 17
By making the configuration sandwiched between the key wiring and the LSI 17, the display element 18 and the
Connection between LSIs 17 is also achieved. 20 is a presser plate,
21 is a fixing screw, and 22 is a bottom panel. Further, 23 is a battery serving as a power source, and 24 is a battery terminal.

本発明に係る部分の構成は以下のとおりであ
る。
The structure of the part related to the present invention is as follows.

キー配線シート16及び押え板20には、フイ
ルム・キヤリヤLSI17に設けられている上記位
置決め用穴11(または12)と同一のパターン
の穴が、それぞれ設けられている。一方、キヤビ
ネツト13には、上記各穴と同一のパターンの位
置決め用ピン25が設けられている。該ピン25
が、キー配線シート16、フイルム・キヤリヤ
LSI17及び押え板20それぞれの各穴に挿入さ
れる形で組み立てを行えば、フイルム・キヤリヤ
LSI17及びキー配線シート16は正しい位置に
位置決めされて固定される。
The key wiring sheet 16 and the holding plate 20 are provided with holes having the same pattern as the positioning holes 11 (or 12) provided in the film carrier LSI 17, respectively. On the other hand, the cabinet 13 is provided with positioning pins 25 having the same pattern as each of the holes. The pin 25
However, key wiring sheet 16, film carrier
If assembled by inserting it into each hole of LSI 17 and holding plate 20, the film carrier
The LSI 17 and key wiring sheet 16 are positioned and fixed at correct positions.

第5図に示す電卓の組み立て順序は以下のとお
りである。
The order of assembling the calculator shown in FIG. 5 is as follows.

キヤビネツト13に、キートツプ14、導電ゴ
ムスプリング15、表示素子18、キー配線シー
ト16、円柱状弾性体19、電池端子24及び電
池23を実装する。キー配線シート16の端部は
円柱状弾性体19の周囲に巻き付けておく。
A key top 14, a conductive rubber spring 15, a display element 18, a key wiring sheet 16, a cylindrical elastic body 19, a battery terminal 24, and a battery 23 are mounted on the cabinet 13. The end of the key wiring sheet 16 is wrapped around the cylindrical elastic body 19.

その後、金型により打ち抜いた第3図形状Aま
たは第4図形状Bのフイルム・キヤリヤLSI17
を、その位置決め用穴11または12に上記位置
決め用ピン25が挿入される形で実装する。これ
により、LSI17は正しい位置に位置決めされ
る。押え板20を当て、ビス21により固定し、
底パネル22を実装して、組立完了となる。
Thereafter, a film carrier LSI 17 having shape A in Figure 3 or shape B in Figure 4 is punched out using a die.
is mounted such that the positioning pin 25 is inserted into the positioning hole 11 or 12. Thereby, the LSI 17 is positioned at the correct position. Apply the presser plate 20 and fix it with the screws 21,
The bottom panel 22 is mounted and the assembly is completed.

(効果) 以下詳細に説明したように、本発明の実装方法
によれば、フイルム・キヤリヤLSIの位置決めを
きわめて簡単に行うことができ、また同一構成の
フイルム・キヤリヤLSIを、組み込むべき機器の
構造に応じてカツテイング・パターンを変えるだ
けで異なる構造の機種にも適用可能となるという
効果を奏するものである。
(Effects) As explained in detail below, according to the mounting method of the present invention, the film carrier LSI can be positioned extremely easily, and the film carrier LSI of the same configuration can be installed in the structure of the equipment to be installed. This has the effect that it can be applied to models with different structures simply by changing the cutting pattern accordingly.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は斜視図、第2図乃至第4図は平面図、
第5図は断面図である。 符号の説明、1:フイルム・キヤリヤLSI、
2:リール、3:フイルム、4:LSIチツプ、
5,6:電源端子、7:発音体接続端子、8:キ
ー信号入出力端子及び表示信号出力端子、9:接
続配線、10:スプロケツト・ホール、11,1
2:位置決め用穴、13:キヤビネツト、14:
キートツプ、15:導電ゴムスプリング、16:
キー配線シート、17:フイルム・キヤリヤ
LSI、18:表示素子、19:円柱状弾性体、2
0:押え板、21:ビス、22:底パネル、2
3:電池、24:電池端子、25:位置決め用ピ
ン。
Figure 1 is a perspective view, Figures 2 to 4 are plan views,
FIG. 5 is a sectional view. Explanation of codes, 1: Film carrier LSI,
2: Reel, 3: Film, 4: LSI chip,
5, 6: Power supply terminal, 7: Sound element connection terminal, 8: Key signal input/output terminal and display signal output terminal, 9: Connection wiring, 10: Sprocket hole, 11, 1
2: Positioning hole, 13: Cabinet, 14:
Key top, 15: Conductive rubber spring, 16:
Key wiring sheet, 17: Film carrier
LSI, 18: display element, 19: cylindrical elastic body, 2
0: Holding plate, 21: Screw, 22: Bottom panel, 2
3: Battery, 24: Battery terminal, 25: Positioning pin.

Claims (1)

【特許請求の範囲】 1 送り用のスプロケツトホールを形成したフイ
ルム上に、LSIチツプ、外部接続端子及び上記
LSIチツプと外部接続端子間を電気的に接続する
配線を設けたフイルム・キヤリヤLSIの実装方法
に於て、 上記フイルムの所定位置には上記スプロケツト
ホールとは別にいずれの組も少なくとも2個の穴
からなる2組の位置決め用穴が形成され、 上記フイルム・キヤリヤLSIは実装する機器キ
ヤビネツトの構造にあわせ、上記いずれかの組の
位置決め用穴を択一的に残してフイルムからカツ
テイングされ、 機器キヤビネツトに設けられる位置決め用ピン
との係合により、上記フイルム・キヤリヤLSI取
り付け時の位置決めを行う構成としたことを特徴
とするフイルム・キヤリヤLSIの実装方法。
[Claims] 1. An LSI chip, an external connection terminal, and the above-mentioned
In the method of mounting a film carrier LSI in which wiring is provided to electrically connect the LSI chip and external connection terminals, each set has at least two sprocket holes at predetermined positions on the film. Two sets of positioning holes are formed, and the film carrier LSI is cut from the film leaving one of the above sets of positioning holes selectively left in accordance with the structure of the device cabinet to be mounted, and the device is cut. A method for mounting a film carrier LSI, characterized in that the film carrier LSI is positioned by engagement with a positioning pin provided on a cabinet to determine the position when the film carrier LSI is installed.
JP57133928A 1982-07-30 1982-07-30 Mounting method for film carrier lsi Granted JPS5923555A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57133928A JPS5923555A (en) 1982-07-30 1982-07-30 Mounting method for film carrier lsi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57133928A JPS5923555A (en) 1982-07-30 1982-07-30 Mounting method for film carrier lsi

Publications (2)

Publication Number Publication Date
JPS5923555A JPS5923555A (en) 1984-02-07
JPH021371B2 true JPH021371B2 (en) 1990-01-11

Family

ID=15116351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57133928A Granted JPS5923555A (en) 1982-07-30 1982-07-30 Mounting method for film carrier lsi

Country Status (1)

Country Link
JP (1) JPS5923555A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0750724B2 (en) * 1986-12-17 1995-05-31 株式会社日立製作所 Liquid crystal display
JP2812627B2 (en) * 1992-10-30 1998-10-22 三菱電機株式会社 Tape carrier, semiconductor device test method and apparatus
JP2509804B2 (en) * 1994-07-22 1996-06-26 シャープ株式会社 Display device
JP2002093861A (en) * 2000-09-12 2002-03-29 Mitsui Mining & Smelting Co Ltd 2-metal TAB, double-sided CSP, BGA tape, and manufacturing method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7215649A (en) * 1972-11-18 1974-05-21
JPS544375A (en) * 1977-06-13 1979-01-13 Suwa Seikosha Kk Circuit substrate

Also Published As

Publication number Publication date
JPS5923555A (en) 1984-02-07

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