JPH021377B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a well of a complementary insulated gate field effect semiconductor device that enables high speed and high integration.

A complementary MOS semiconductor device constituted by N-channel and P-channel insulated gate field effect (hereinafter referred to as MOS) transistors has conventionally had the structure shown in FIG. In other words, a P channel MOS transistor 2 is placed in an N type silicon substrate 1.
is formed, and the N-channel MOS transistor 3
was formed in the P well 4 formed in the N type silicon substrate 1. As the degree of integration increases, if necessary, parasitic MOS transistors will be installed near the silicon substrate interface of the field oxide film surrounding each transistor.
In order to prevent this effect, in the case of an N-channel MOS transistor, the highly doped P-type regions 5 and 6 and the P-channel
In the case of a MOS transistor, highly doped N-type regions 7 and 8 would be formed. But even denser complementary types
In order to realize a MOS semiconductor device, complementary type
It is necessary to prevent latch-up, which is a phenomenon peculiar to MOS semiconductor devices. It has been known that reducing the resistance of the diffusion layer by increasing the impurity concentration of the silicon substrate and the well is highly effective in preventing latch-up. This is contrary to attempts to lower the substrate impurity concentration and the well impurity concentration. On the other hand, the method of forming a highly doped buried region in advance and forming an epitaxial layer thereon complicates manufacturing and also limits the formation of other elements.
The integrated circuit device lacks versatility.

The object of the present invention is to provide an effective manufacturing method that eliminates the above-mentioned drawbacks.

The present invention is characterized by a step of ion-implanting an impurity of an opposite conductivity type from one principal surface of a predetermined portion of a semiconductor substrate of one conductivity type to form a high impurity concentration region of the opposite conductivity type; and ion-implanting impurities of one conductivity type into the interior to form a low impurity concentration region of the opposite conductivity type, the sides and bottom of the low impurity concentration region of the opposite conductivity type are injected with high impurity concentration of the opposite conductivity type. A method for manufacturing a complementary insulated gate field effect semiconductor device in which a well region of opposite conductivity type surrounded by a region is formed, and a channel type transistor of one conductivity type is formed in a low impurity concentration region of opposite conductivity type in the well region. be. In this way, the method of the present invention
By ion-implanting impurities of opposite conductivity type and one conductivity type to compensate, a low concentration region of opposite conductivity type is formed surrounded by a high concentration region. According to this method, the concentration of each part of the well can be easily formed to a desired value, and since there is no need to use an epitaxial layer covering the entire semiconductor substrate, other elements can be formed freely, and it is versatile. It becomes a highly integrated circuit device.

2 and 3 are devices obtained by the method of the invention.

In FIG. 2, in the N-type silicon substrate 21,
P-well regions 22 and 23 are formed, and since the P-well 22 has a lower P-type impurity concentration than the P-well 23, the characteristics of the N-channel MOS transistor 24 are not deteriorated, and the surrounding area of the P-channel MOS transistor 25 is This acts as a channel stopper to prevent parasitic MOS effects, and also reduces the resistance of the P-well diffusion layer, making latch-up less likely to occur. On the other hand, P channel MOS
A channel stopper may be inserted into the transistor 25 if necessary to prevent parasitic MSO effects, but this is not necessary if the impurity concentration of the N-type silicon substrate 21 is high. In the first embodiment, the P-wells 22 and 23 are formed in an N-type silicon substrate 21, but the same applies to the case where an N-well is formed in a P-type silicon substrate.

In FIG. 3, an N-type silicon substrate 31 with a very low impurity concentration is used, and a P-channel MOS transistor 32 is formed using N-wells 33, 3.
In this case, the N-channel MOS transistor 35 is formed in the P wells 36 and 37. The MOS transistors of each channel are formed in wells 33 and 36 with low impurity concentration, and the P channel MOS transistors 3
By increasing the impurity concentration in the side and bottom portions 34 and 37 of each well, a channel stopper is automatically formed and the minimum distance between the diffusion layers between N-channel MOS transistor 35 and N-channel MOS transistor 35 is made very small. There is. Also, a high concentration at the bottom of the well is highly effective against latch up.

Next, an example of the manufacturing method of the present invention is shown in FIGS.
The manufacturing process is shown in order.

Figure 4a: First, an N-type low concentration silicon substrate 101
is thermally oxidized to form a thick silicon oxide film 102, a desired region 103 on the silicon substrate 101 is etched away using a photoetching technique, and B ⁺ ions are implanted at a high concentration through the opened hole 103. 104.

FIG. 4b: The silicon substrate 101 is further thermally oxidized. The new silicon oxide film 105 is etched again using the photoetching technique in the area included in the area 103 etched away by the photoetching technique. B ⁺ ions have already been implanted into the holed portion 106 and P
By ion-implanting phosphorus atoms 108 into the P-well 107, which has replaced the mold, a region 109 with a low P-type impurity concentration is formed. It is within this region 109 with a low concentration of P-type impurities that the N-channel MOS transistor 130 is formed.

FIG. 4c: After removing the silicon oxide film on the silicon substrate 101, the substrate 101 is manufactured in a conventional manner, and silicon nitride films 110 and 111 are patterned on the thin silicon oxide film 112 to form a P-channel MOS transistor. Channel stoppers 113 and 114 are introduced for this purpose.

FIG. 4d: Field oxide film 115, selectively oxidized using silicon nitride films 110 and 111 as a mask,
116 is formed. After that, a thin gate oxide film 11
7 and 118 are formed, and polycrystalline silicon 119 and 120 serving as gate electrodes are deposited thereon and patterned. Next, using the photoresist as a mask, N-type impurities such as phosphorus and arsenic are added at a high concentration to form the source and drain 121 and 122 of the N-channel MOS transistor 130. Next, using a photoresist as a mask, a P-type impurity such as boron is doped at a high concentration, and the sources and drains 123 and 12 of the P-channel MOS transistor 131 are
form 4.

Figure 4e: Oxide films 128, 12 by conventional technology
9 is provided, and further aluminum wiring 125,
126 and 127 are formed to constitute a complementary MOS semiconductor device.

In the above description, a P-well type complementary MOS semiconductor device has been shown, but it goes without saying that the manufacturing method of the present invention can also be applied to an N-well type. Also, in Figure 3, N
Although the P-channel MOS transistor is formed in the N-well and the N-channel MOS transistor is formed in the P-well using the type substrate 31, the substrate may be of either the N type or the P type. It is clear that the method of forming each well may be carried out by applying the method of the present invention to one well at a time using appropriate impurities.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional complementary MOS semiconductor device, and FIGS. 2 and 3 are sectional views of complementary MOS semiconductor devices obtained by the method of the present invention. 4A to 4E are cross-sectional views showing step by step a method of manufacturing a complementary MOS semiconductor device according to an embodiment of the present invention. In the figure, 1...N-type silicon substrate, 2
...P channel MOS transistor, 3...N
Channel MOS transistor, 4...P well,
5, 6... Channel stopper on the N channel side in the P type high concentration region, 7, 8... Channel stopper on the P channel side in the N type high concentration region, 9
...Interlayer insulating silicon oxide film, 10...Aluminum wiring, 21...N-type silicon substrate, 22...
Low concentration P well, 23...High concentration P well, 24
...N-channel MOS transistor, 25...
P channel MOS transistor, 31...N type silicon substrate, 32...P channel MOS transistor, 33...Low concentration N well, 34...High concentration N well, 35...N channel MOS transistor, 36...Low concentration P well, 37... High concentration P well, 38... Interlayer silicon insulation oxide film, 39, 40... Aluminum wiring, 101...
. . . N-type silicon substrate, 102 . oxide film removal region opened inside, 10
8... Phosphorus atom ion implantation, 109... Low concentration P well region, 110, 111... Silicon nitride film, 112... Thin silicon oxide film, 113, 1
14... Channel stopper of P channel MOS transistor, 115, 116... Field oxide film, 117, 118... Gate oxide film, 1
19,120...gate electrode, 121,122...
...Source and drain regions of N-channel MOS transistor, 123, 124...P-channel
Source and drain regions of MOS transistor, 1
25,126,127...aluminum wiring, 1
28, 129...Interlayer insulating silicon oxide film, 13
0...N channel MOS transistor, 131
...It is a P-channel MOS transistor.

Claims (1)

[Claims] 1. A step of ion-implanting an impurity of the opposite conductivity type from one principal surface of a predetermined portion of a semiconductor substrate of one conductivity type to form a high impurity concentration region of the opposite conductivity type, and forming a high impurity concentration region of the one conductivity type inside the high impurity concentration region forming a low impurity concentration region of the opposite conductivity type by ion-implanting an impurity of A method for manufacturing a complementary insulated gate field effect semiconductor device, comprising forming a well region of a conductivity type, and forming a channel type transistor of one conductivity type in a low impurity concentration region of the opposite conductivity type in the well region.