JPH0213826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in an insulated gate field effect semiconductor device using silicon as a semiconductor.

Conventionally, MIS (metal-insulator-semiconductor structure) and FET (field effect transistor) as shown in FIG. 1, for example, have been known.

In the figure, 1 is, for example, a P-type silicon semiconductor substrate, 2 is a field insulating film, 3 is a gate insulating film, 4 is an n ⁺ type source region, 5 is an n ⁺ type drain region, 6 is a source electrode, and 7 is a 8 indicates a drain electrode, and 8 indicates a gate electrode.

In a MIS/FET having such a structure, the channel current flowing between the source and drain is controlled depending on the voltage level applied to the gate.

In addition, a short gate type FET as shown in FIG. 2 is also known.

In the figure, 11 is a semi-insulating substrate, 12 is, for example, an epitaxially grown n-type semiconductor layer, and 13 is a semi-insulating substrate.
n ⁺ type source region, 14 is n ⁺ type drain region, 1
5 is the source electrode of the ohmic contact, 16
is the drain electrode of the ohmic contact, 17
is the gate electrode of the shot contact.

This FET also controls the channel current depending on the level of the voltage applied to the gate electrode 17.

Now, generally speaking, in order to operate a FET at high speed, the gate length must be kept as short as possible.
However, the MIS and
In a FET, a depletion layer is generated at the drain junction, so if the gate length is too short, the depletion layer reaches the source region, which tends to cause a so-called punch-through condition. Therefore, the gate length cannot be made extremely short.

On the other hand, since the shot gate type FET explained with reference to FIG. The gate length can be shortened. Also, since the carrier flows in the pulp, the MIS in Fig. 1 where the carrier flows in the channel on the surface of the semiconductor layer.
Carrier mobility is large compared to FET.
However, shot gate type FETs are not full of good features; for example, depletion type FETs have input and output with opposite polarity, making it difficult to connect to the next stage, and enhancement type FETs have gate input is in the forward direction, so
It is not possible to apply a very large voltage, and therefore a large logic amplitude cannot be obtained.

The present invention was made in order to overcome the drawback of the shot-gate type FET, in which a very large voltage cannot be applied in the forward direction. Insulated gate type FET
This design maintains the advantages of shot gate type FETs, such as no fear of punch-through even when the gate length is shortened, and higher carrier mobility than general MIS FETs. ,
Since voltage can also be applied in the forward direction, a large logic amplitude can be obtained, and this will be explained in detail below.

FIG. 3 is a side sectional view of a main part of an embodiment of the present invention.

In the figure, 21 is a semi-insulating silicon single crystal substrate, and 22 is a semi-insulating silicon single crystal substrate formed by vapor phase epitaxial growth, for example, with an impurity concentration of 1×10 ¹⁷ [atoms/cm ³ ] and a thickness of about 0.2 [μm]. ] n-type silicon semiconductor layer, 2
3 and 24 are n ⁺ type source regions and n ⁺ type drain regions having a surface impurity concentration of, for example, 1×10 ¹⁹ [atoms/cm ³ ], which are selectively formed by, for example, a normal vapor phase diffusion method; 25 is, for example, A gate insulating film with a thickness of, for example, 0.15 [μm] formed by thermal oxidation, 26 a source electrode of an ohmic contact, 27 a drain electrode of an ohmic contact, and 28 a gate electrode formed at the same time as these electrodes. It is. still,
After forming the gate electrode 28, the temperature was 500 [℃] for 20 hours.
It is recommended that the heat treatment be performed for about [minutes].

The MIS-FET of the present invention obtained in this way operates on substantially the same principle as the shot-gate type FET, and the length of the depletion layer changes depending on the voltage applied to the gate electrode 28. The channel current flowing through is controlled.

The MIS/FET according to the present invention can obtain the following effects.

(1) Since the source region and the drain region have the same conductivity type as the epitaxially grown semiconductor layer, no depletion layer is generated even when a voltage is applied, and punch-through is less likely to occur. Therefore, the gate length can be made as short as possible, which is effective for higher speed and higher integration.

(2) Since the carrier moves in bulk, conventional
Carrier mobility is large compared to MIS/FET.

(3) Since it has a gate insulating film, unlike conventional shot gate type FETs, gate voltage can be applied in the forward direction even when used in enhancement mode, and large logic amplitude can be obtained. .

(4) Since silicon is used as the wafer (substrate + semiconductor layer), a high-quality oxide insulating film can be formed and used.

[Brief explanation of drawings]

1 and 2 are side sectional views of main parts of a conventional example, and FIG. 3 is a side sectional view of main parts of an embodiment of the present invention. In the figure, 21 is a substrate, 22 is a semiconductor layer, 2
3 and 24 are a source region and a drain region, 25 is a gate insulating film, 26 and 27 are a source electrode and a drain electrode, and 28 is a gate electrode.

Claims (1)

[Claims] 1. A semiconductor wafer having a silicon semiconductor layer of one conductivity type epitaxially grown on a semi-insulating single crystal substrate, a source region and a drain region having the same conductivity type as the silicon semiconductor layer and having a higher concentration than the silicon semiconductor layer;
An insulated gate field effect semiconductor device comprising a gate insulating film formed between the regions, a gate electrode thereon, a source electrode in contact with the source region, and a drain electrode in contact with the drain region. .