JPH0213866B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a pulse integration circuit, and particularly to a pulse input circuit that is suitable for taking advantage of improved processing power of a CPU, etc. by lengthening the pulse input reading cycle. .

(b) Prior art and problems The prior art will be explained with reference to the drawings.

FIG. 1A shows a conventional pulse input circuit, in which a pulse signal P to be measured having an unspecified pulse width and an unspecified period is sent from an input terminal 1 to a low-frequency wave generator 2 that absorbs a chattering waveform, etc. Buffer circuit 3
The read strobe signal STB for access supplied from the CPU 5 is connected to the other input terminal of the AND gate 4, and the AND gate 4 is connected in series to one input terminal of the AND gate 4. The output E is connected to a counter circuit 5a in the CPU 5, and is configured to integrate the number of input pulses of the pulse signal P to be measured.

Figure 1B is a time chart of each part of A and the CPU
5 is shown. That is, the cycle of the read strobe signal STB is certified to be shorter than the minimum pulse width included in the pulse signal P to be measured, and is supplied from the CPU 5. t is time, and _t1 to _t12 indicate the cycle time of the read strobe signal. As shown in the time chart, the input of the pulse signal P to be measured and the lead strobe signal
Output E of AND gate 4 corresponding to input of STB
In order to recognize the cumulative value of the counter 5a of the CPU 5, the output E at time _t2 is first memorized as "1", and compared with the output E of the next read strobe signal, when it changes to "0". Judgment integration is performed with the nth pulse input. Therefore, since the output E at time _t3 is "1", no integration is performed and the next time _t4 is waited for. Output E at time t ₄ is “0”
Therefore, starting from here, the n-th pulse input is integrated. Similarly, at time t ₅ to t ₆ , the n+1
The n+2th value is integrated at time t ₁₁ to _{t 12} .

When integrating using the above method, change from “1” to “0”.
Therefore, in order to prevent the pulse number from being omitted from integration, it is necessary to set the period of the strobe signal STB smaller than the minimum pulse width of the pulse signal under test. If the pulse width of signal P becomes shorter than the minimum pulse width, or if the number of measurement systems increases, CPU5
The cycle of the read strobe signal STB must be made even faster, which has the disadvantage of reducing the processing capacity of the CPU 5.

(c) Purpose of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention utilizes a flip-flop to read the pulse input without limiting the reading period to within the minimum pulse width of the pulse signal under test. The purpose of the present invention is to provide a pulse input circuit that can be lengthened to less than the minimum period.

(d) Structure of the Invention According to the present invention, the device has a data terminal, a clock terminal, a Q output terminal, and a reset terminal, and when both the data terminal and the clock terminal have a logic value “1”, the Q A D-type flip-flop whose output is set, an AND gate to which the Q output terminal is connected to one input terminal and a read strobe signal is constantly input to the other input terminal, and an AND gate which delays the input read strobe signal by a predetermined time. and a delay circuit for inputting to the reset terminal, a logic value "1" is always input to the data terminal, and a pulse signal under test is input to the clock terminal. This is accomplished by providing a circuit.

(e) Examples of the invention Examples of the invention will be described in detail below with reference to the drawings. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and redundant explanation thereof will be omitted.

FIG. 2 shows a pulse input circuit according to the present invention, and FIG. 3 shows a time chart of the same circuit.

In the figure, the FF includes a clock terminal C, a data terminal D, a reset terminal R, and an output terminal Q (also called a Q output terminal). A D-type flip-flop whose output is set and whose Q output is unconditionally reset by applying a reset pulse to the reset terminal R; DL is a delay circuit;
t ₁₃ to t ₂₂ indicate time.

As shown in FIG. 2, a conventional buffer circuit 3
The output of
, and "1" is always applied to data terminal D. The output terminal Q is connected to one input terminal of the AND gate 4, and the strobe signal STB is branched, one branch is input to the other input terminal of the AND gate 4, and the other branch is connected to the flip-flop FF via the delay circuit DL. The circuit configuration is such that the input is input to the reset terminal R of the .

Here, the period of the read strobe signal STB is set to be less than the minimum period of the pulse signal P to be measured.
As shown in the time chart in Fig. 3, when the pulse signal under test P is input, the output terminal Q of the flip-flop FF is output in response to the rising edge of the pulse signal under test P at time _t13 . "1" is output, and one input terminal of the AND gate 4 receives a sustained input of "1" (that is, a set state). Next, at time _t14 , when the rising signal of the read strobe signal STB is input to the other input terminal of the AND gate 4, one pulse is output to the output E of the AND gate 4. This output is determined to be a detection signal of one pulse of the pulse signal to be measured. Furthermore, since the read strobe signal STB is branched and input to the delay circuit DL, the output rising signal of the delay circuit DL rises at time _t15 , slightly later than time _t14 , and is input to the reset terminal R of the flip-flop FF. Therefore, the sustained output "1" at the output terminal Q of the flip-flop FF is reset to a sustained state of output "0" at time _t15 . To recognize the integration of the counter 5a, it is sufficient to integrate only the output E of the AND gate.

Next, at time _t15 , the flip-flop FF has no effect even though the pulse signal P under test falls, and at time _t17 , the read strobe signal
Even if STB is input, the output of output terminal Q is “0”
Therefore, AND gate 4 does not output.

Similarly, the rising edge of the pulse signal P under test at time _t18 is output as "1" to the output terminal Q of the flip-flop FF until the next read strobe signal STB is input to the AND gate 4 at time _t19 . To last, definitely and gate 4
The output E of can be integrated. Furthermore, immediately after the integration, the output of the output terminal Q of the flip-flop FF is reset by the action of the delay circuit DL to wait for the next pulse signal P to be measured, so that there is no error in the integration. In this way, one input terminal of the AND gate 4 is held in the set state in response to the input of the pulse signal P under test itself, and then the AND gate 4 is ANDed with the read strobe signal input to the other input terminal of the AND gate 4. Obtaining a pulse signal for counting by the output, and immediately after that, canceling the set state using a delayed signal of the read strobe signal,
Waits for input of the next pulse signal P to be measured. By using a delay signal to release the set state immediately after pulse counting, the period of the read strobe signal can be extended to less than the minimum period of the pulse signal under test.

In this embodiment, the integration operation is performed by the CPU, but it can also be easily performed by a micro CPU, micro processor, etc.

(f) Effects of the Invention As explained in detail above, according to the pulse input circuit of the present invention, the period of the read strobe signal can be lengthened to less than the minimum period of the pulse signal under test, so that the CPU processing It has the effect of improving abilities.

[Brief explanation of drawings]

FIG. 1 shows a conventional pulse input circuit, where A is a block diagram and B is a time chart of the circuit.
FIG. 2 shows a block diagram of a pulse input circuit according to the present invention, and FIG. 3 shows a time chart of FIG. In the figure, 4 is an AND gate, P is the pulse signal to be measured, E is the output of the AND gate, STB is a read strobe signal, t and t ₁₃ to t ₂₂ are times, and t ₁
~ _t12 is the cycle time of the read strobe signal,
n is the integrated number, FF is a flip-flop, R is a reset terminal, Q is an output terminal, and DL is a delay circuit.

Claims (1)

[Claims] 1. A D-type flip-flop having a data terminal, a clock terminal, a Q output terminal, and a reset terminal, and in which the Q output is set when both the data terminal and the clock terminal have a logical value of "1". , an AND gate that connects the Q output terminal to one input terminal and constantly inputs a read strobe signal to the other input terminal; and a delay circuit that delays the input read strobe signal by a predetermined time and inputs it to the reset terminal. A logical value "1" is always input to the data terminal, and when a pulse signal under test is input to the clock terminal, one input terminal of the AND gate is set via the Q output terminal. Immediately thereafter, an AND output when a read strobe signal is input to the other input terminal is determined as a detection signal of the pulse signal under test, and the Q output is reset by a delayed signal of the read strobe signal. A pulse input circuit characterized in that: