JPH021392B2 - - Google Patents
Info
- Publication number
- JPH021392B2 JPH021392B2 JP6800384A JP6800384A JPH021392B2 JP H021392 B2 JPH021392 B2 JP H021392B2 JP 6800384 A JP6800384 A JP 6800384A JP 6800384 A JP6800384 A JP 6800384A JP H021392 B2 JPH021392 B2 JP H021392B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- layer
- etching resist
- inner layer
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005530 etching Methods 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 12
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000011888 foil Substances 0.000 description 13
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 9
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 8
- 238000000576 coating method Methods 0.000 description 7
- 239000002904 solvent Substances 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229960003280 cupric chloride Drugs 0.000 description 4
- 238000003475 lamination Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Description
(技術分野)
本発明は多層印刷配線板の製造方法に関し、特
に多層印刷配線板の内層の製造方法に関する。
(従来技術)
近年、印刷配線板に搭載するIC、LSI等の電子
部品の高速度化、高密度化に伴ない、これらの電
子部品の消費する電力の供給が問題となつてきて
いる。このため多層印刷配線板の内層導体層に用
いる銅箔の厚さを次第に厚くし、電力供給を良好
にする傾向となつてきている。
すなわち一般には、内層導体層としての電源層
及び接地層に厚さ35〜70μmの薄い銅箔を使用し
ていたが、厚さ150〜300μmまたはそれ以上の厚
い銅箔を用いて電力供給を改善するようになつて
来た。
第1図A〜Mにより従来工法による厚い内層導
体層を使用した多層印刷配線板の製造方法を説明
する。
先ず、第1図Aは絶縁基板1に厚い金属箔2
a,2bを接着した両面金属箔張絶縁板の断面図
である。こゝで金属箔2a,2bには例えば
150μm以上の厚さの銅箔を用いる。
次に、第1図Bに示すように、金属箔2a,2
b上にホトレジスト層3a,3bを被着形成し、
ホトマスク4a,4bを介して感光させる。
次に、第1図Cに示すように、未露光部分をク
ロロセン等の溶剤を用いて溶解・除去させエツチ
ングレジスト被膜3a,3bを形成する。
次に、第1図Dに示すように、金属箔2a,2
bのエツチングレジスト被膜3a,3bに覆われ
ていない部分を塩化第2銅等を用いてエツチング
除去し、さらに第1図Eに示すように、エツチン
グレジスト被膜3a,3bを塩化メチレン等の溶
剤を用いて溶解除去すると内層板6の回路パター
ンが得られる。
次に、第1図Fに示すように、内層板6の上下
両面にプリプレグ7a,7b,7c,7dを介し
て外層導体層8a,8bを積層し、次いで第1図
Gに示すように、ホツトプレスなどで熱圧着し、
多層化基板9を形成する。
次に、第1図Hに示すように、多層化基板9に
スルーホール10をあける。次いで第1図Iに示
すように、外層導体層8a,8b及び金属箔に回
路パターンを形成した内層導体層2a,2bの間
を電気的に接続するためのスルーホールめつき1
2を施す。
次に、第1図Jに示すように、外層導体層8
a,8b上に感光性樹脂層3c,3dを被着形成
し、ホトマスク4c,4dを介して露光する。次
いで、第1図Kに示すように、未露光部分をクロ
ロセン等の溶剤を用いて溶解除去し、エツチング
レジスト被膜3c,3dを形成する。
次に、第1図Lに示すように、エツチングレジ
スト被膜3c,3dをマスクとして、塩化第2銅
液等で外層導体層のエツチングレジスト被膜3
c,3dに覆われていない部分をエツチング除去
し、次いで第1図Mに示すように、エツチングレ
ジスト被膜3c,3dを塩化メチレン等の溶剤で
溶解除去すると、従来の多層印刷配線板13が得
られる。
しかし、上記した従来の製造方法では、厚い金
属箔を内層導体層に使用した場合以下に示す大き
な欠点があつた。
(1) エツチングによるアンダーカツトが大きくな
り、回路形成精度が悪化し、エツチング残り
や、オーバーエツチングを発生し易くなり、絶
縁劣化又は電源供給不良を起す。
(2) 内層板の絶縁基材と内層導体層との間の段差
が大きいため、積層時に段差の部分が樹脂で埋
まらず積層ボイドを発生する。
(3) 内層板の段差が大きいため、外層導体層の平
坦性が悪化し、エツチングレジスト被膜の被着
不良や露光ボケを発生する。
(発明の目的)
本発明の目的は、従来の欠点を除去し、電力供
給が容易で、かつ回路形成精度が高く、積層ボイ
ドの発生もなく、外層導体層の平坦性も良好な多
層印刷配線板の製造方法を提供することにある。
(発明の構成)
本発明の多層印刷配線板の製造方法は、導体層
の所望の位置にエツチングレジスト被膜を被着形
成する工程と、前記エツチングレジスト被膜をマ
スクとして前記導体層の所望部分を表裏両面より
エツチングする工程と、前記エツチングをした導
体層をプリプレグを介して上下に配置し熱圧着さ
せて内層板を形成する工程と、前記内層板の表面
に絶縁樹脂を塗布し絶縁層を形成する工程と、前
記絶縁層を形成した内層板を一層以上内層に配置
し外層導体層をプリプレグを介して熱圧着し多層
化基板を形成する工程と、前記多層化基板にスル
ーホールを形成する工程と、前記スルーホールを
形成した多層化基板にスルーホールめつきを施す
工程と、前記スルーホールめつきを施した多層化
基板の外層の所望の位置にエツチングレジスト被
膜を被着形成しエツチングレジスト被膜に覆われ
ていない箇所をエツチング除去し外層回路を形成
する工程とを含んで構成される。
(実施例)
以下、本発明の実施例について、図面を参照し
て説明する。
第2図A〜Uは本発明の一実施例を説明するた
めに工程順に示した断面図である。
先ず、第2図A,Bに示すように、金属箔2
2,22′を準備する。金属箔22,22′の厚さ
は150μm以上の銅箔を使用する。
次に、第2図C,Dに示すように、金属箔2
2,22′の両面上にホトレジスト23a,23
b,23a′,23b′を被着形成しホトマスク24
a,24bおよび24a′,24b′を介して露光す
る。
次に、第2図E,Fに示すように、未露光部分
をクロロセン等の溶剤を用いて溶解・除去しエツ
チングレジスト被膜23a,23bおよび23
a′,23b′を形成する。
次に、第2図G,Hに示すように、金属箔2
2,22′の上下両面から、エツチングレジスト
被膜23a,23bおよび23a′,23b′に覆わ
れていない部分を塩化第2銅液等を用いてエツチ
ングする。次いで第2図I,Jに示すように、エ
ツチングレジスト被膜23a,23bおよび23
a′,23b′を塩化メチレン等の溶剤を用いて除去
する。
次に、第2図Kに示すように、エツチングを施
した金属22,22′をプリプレグ27aを介し
て上下に配置し、第2図Lに示すように、ホツト
プレス熱圧着させると内層板26が形成できる。
次に、第2図Mに示すように、内層板26の表
裏にスクリーン印刷又は、ロールコート等の方法
によつて絶縁樹脂層34a,34bを被着形成し
絶縁樹脂コート内層板35を形成する。
次に第2図Nに示すように、絶縁樹脂コート内
層板35および外層導体層28a,28bおよび
プリプレグ27b,27cを介して配置し、第2
図Oに示すように、ホツトプレスにより熱圧着さ
せる多層化基板29を形成する。
次に、第2図Pに示すように、通常の方法で多
層基板29にスルーホール30を形成する。次い
で第2図Qに示すように、外層導体層28a,2
8bおよび絶縁樹脂コート内層板35の導体部分
を電気的に接続させるスルーホールめつき32を
施す。
次に、第2図Rに示すように、外層導体層28
a,28b上に形成したスルーホールめつきの表
面にホツトレジスト23c,23dを被着形成さ
せた後、ホトマスク24c,24dを介して露光
させ、第2図Sに示すように、未露光部分をクロ
ロセン等の溶剤で溶解・除去しエツチングレジス
ト被膜23c,23dを形成する。
次に、第2図Tに示すように、スルーホールめ
つき32上に形成したエツチングレジスト被膜2
3c,23dに覆われていない部分を塩化第2銅
液等でエツチング除去する。次いでエツチングレ
ジスト被膜23c,23dを塩化メチレン等の溶
剤で溶解・除去すれば第2図Uに示すような多層
印刷配線板33が完成する。
なお本発明の効果をより明確にするため、従来
方法並びに本発明方法により製作した多層印刷配
線板の精度測定結果を第1表並びに第2表に示
す。
第1表は従来方法によるものであり、第2表は
本発明方法によるものである。
(Technical Field) The present invention relates to a method for manufacturing a multilayer printed wiring board, and particularly to a method for manufacturing an inner layer of a multilayer printed wiring board. (Prior Art) In recent years, as electronic components such as ICs and LSIs mounted on printed wiring boards have become faster and more dense, the supply of power consumed by these electronic components has become a problem. For this reason, there is a trend to gradually increase the thickness of copper foil used for the inner conductor layer of multilayer printed wiring boards to improve power supply. In other words, in general, thin copper foil with a thickness of 35 to 70 μm was used for the power supply layer and ground layer as inner conductor layers, but power supply was improved by using thicker copper foil with a thickness of 150 to 300 μm or more. I've come to do it. A method of manufacturing a multilayer printed wiring board using a thick inner conductor layer using a conventional method will be explained with reference to FIGS. 1A to 1M. First, in FIG. 1A, a thick metal foil 2 is placed on an insulating substrate 1.
FIG. 2 is a cross-sectional view of a double-sided metal foil-clad insulating board with parts a and 2b bonded together. Here, the metal foils 2a and 2b include, for example,
Use copper foil with a thickness of 150 μm or more. Next, as shown in FIG. 1B, the metal foils 2a, 2
Forming photoresist layers 3a and 3b on b,
It is exposed to light through photomasks 4a and 4b. Next, as shown in FIG. 1C, the unexposed portions are dissolved and removed using a solvent such as chlorocene to form etching resist films 3a and 3b. Next, as shown in FIG. 1D, the metal foils 2a, 2
The portions not covered by the etching resist films 3a and 3b in b are etched away using cupric chloride, etc., and as shown in FIG. The circuit pattern of the inner layer board 6 can be obtained by dissolving and removing the material. Next, as shown in FIG. 1F, outer conductor layers 8a and 8b are laminated on both upper and lower surfaces of the inner layer plate 6 via prepregs 7a, 7b, 7c, and 7d, and then, as shown in FIG. 1G, Bonded with heat using a hot press etc.
A multilayer substrate 9 is formed. Next, as shown in FIG. 1H, through holes 10 are made in the multilayer substrate 9. Next, as shown in FIG. 1I, through-hole plating 1 is formed for electrically connecting between the outer conductor layers 8a and 8b and the inner conductor layers 2a and 2b, each of which has a circuit pattern formed on metal foil.
Apply 2. Next, as shown in FIG. 1J, the outer conductor layer 8
Photosensitive resin layers 3c and 3d are formed on a and 8b and exposed to light through photomasks 4c and 4d. Next, as shown in FIG. 1K, the unexposed portions are dissolved and removed using a solvent such as chlorocene to form etching resist films 3c and 3d. Next, as shown in FIG. 1L, using the etching resist coatings 3c and 3d as masks, the etching resist coating 3 of the outer conductor layer is etched using a cupric chloride solution or the like.
A conventional multilayer printed wiring board 13 is obtained by etching away the portions not covered by layers c and 3d, and then dissolving and removing the etching resist films 3c and 3d with a solvent such as methylene chloride, as shown in FIG. 1M. It will be done. However, the conventional manufacturing method described above has the following major drawbacks when thick metal foil is used for the inner conductor layer. (1) Undercuts due to etching become larger, circuit formation accuracy deteriorates, and etching residue and over-etching are more likely to occur, resulting in insulation deterioration or power supply failure. (2) Because the level difference between the insulating base material of the inner layer plate and the inner conductor layer is large, the level difference portion is not filled with resin during lamination, resulting in lamination voids. (3) Since the inner layer plate has a large step difference, the flatness of the outer conductor layer deteriorates, resulting in poor adhesion of the etching resist film and exposure blur. (Objective of the Invention) The object of the present invention is to eliminate the drawbacks of the conventional multilayer printed wiring, which facilitates power supply, has high circuit formation accuracy, does not generate laminated voids, and has good flatness of the outer conductor layer. The object of the present invention is to provide a method for manufacturing a board. (Structure of the Invention) The method for manufacturing a multilayer printed wiring board of the present invention includes a step of depositing an etching resist film on a desired position of a conductor layer, and using the etching resist film as a mask, desired portions of the conductor layer are formed on the front and back sides. a step of etching from both sides; a step of arranging the etched conductor layers one above the other via a prepreg and bonding them under heat to form an inner layer plate; and applying an insulating resin to the surface of the inner layer plate to form an insulating layer. a step of arranging one or more inner layers on which the insulating layer is formed and an outer conductor layer bonded by thermocompression via a prepreg to form a multilayer board; and a step of forming a through hole in the multilayer board. , a step of applying through-hole plating to the multilayer substrate on which the through-holes have been formed, and forming an etching resist film on a desired position of the outer layer of the multilayer substrate on which the through-hole plating has been applied; The method includes a step of etching away uncovered portions to form an outer layer circuit. (Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 2A to 2U are cross-sectional views shown in order of steps to explain an embodiment of the present invention. First, as shown in FIG. 2A and B, the metal foil 2
Prepare 2, 22'. The metal foils 22, 22' are copper foils with a thickness of 150 μm or more. Next, as shown in FIG. 2C and D, the metal foil 2
Photoresist 23a, 23 on both sides of 2, 22'
b, 23a', 23b' are deposited and photomask 24 is applied.
a, 24b and 24a', 24b'. Next, as shown in FIG. 2E and F, the unexposed portions are dissolved and removed using a solvent such as chlorocene to form the etching resist coatings 23a, 23b and 23.
form a' and 23b'. Next, as shown in FIG. 2G and H, the metal foil 2
The portions not covered by the etching resist coatings 23a, 23b and 23a', 23b' are etched from both upper and lower surfaces of 2, 22' using cupric chloride solution or the like. Next, as shown in FIGS. 2I and 2J, etching resist coatings 23a, 23b and 23 are formed.
a' and 23b' are removed using a solvent such as methylene chloride. Next, as shown in FIG. 2K, the etched metals 22 and 22' are placed one above the other through the prepreg 27a, and as shown in FIG. Can be formed. Next, as shown in FIG. 2M, insulating resin layers 34a and 34b are formed on the front and back surfaces of the inner layer plate 26 by screen printing, roll coating, etc. to form an insulating resin coated inner layer plate 35. . Next, as shown in FIG. 2N, a second
As shown in Figure O, a multilayer substrate 29 is formed by thermocompression bonding using a hot press. Next, as shown in FIG. 2P, through holes 30 are formed in the multilayer substrate 29 using a conventional method. Next, as shown in FIG. 2Q, the outer conductor layers 28a, 2
Through-hole plating 32 is provided to electrically connect the conductor portions of the inner layer plate 8b and the insulating resin coated inner layer plate 35. Next, as shown in FIG. 2R, the outer conductor layer 28
After forming hot resists 23c and 23d on the surfaces of the through-hole plating formed on a and 28b, they are exposed to light through photomasks 24c and 24d, and as shown in FIG. The etching resist coatings 23c and 23d are formed by dissolving and removing the resists using a solvent such as the like. Next, as shown in FIG. 2T, an etching resist film 2 is formed on the through-hole plating 32.
The portions not covered by 3c and 23d are removed by etching with cupric chloride solution or the like. Next, the etching resist films 23c and 23d are dissolved and removed using a solvent such as methylene chloride to complete a multilayer printed wiring board 33 as shown in FIG. 2U. In order to clarify the effects of the present invention, Tables 1 and 2 show the accuracy measurement results of multilayer printed wiring boards manufactured by the conventional method and the method of the present invention. Table 1 is based on the conventional method, and Table 2 is based on the method of the present invention.
【表】【table】
【表】
上記第1表、第2表から明らかならうに、仕上
り平均値、最大値、最小値、標準偏差の各数値共
に本発明方法により大幅に改善されることを示し
ている。
すなわち、本発明方法では厚い金属箔の上下両
面から一度にエツチングするため、エツチングで
形成された貫通孔を通してエツチング液が流れ、
貫通孔内壁もエツチングされ、アンダーカツト・
エツチング残りおよびオーバーエツチングのない
平坦な面になるので、回路形成精度が向上する。
また、厚い金属箔のエツチングされた部分が、
絶縁樹脂で充てんされているので、内層板の段差
がなく、積層ボイドの発生を防止できる。その
上、多層導体層の平坦性も良好で高精度の外層回
路形成が可能となつた。
なお、本実施例では、絶縁樹脂コート内層板を
1枚用いた4層の多層印刷配線板で説明したが、
絶縁樹脂コート内層板を2枚以上、あるいは通常
の工法により形成された内層板をこれと共に用い
ても何等支障のないことは勿論である。
(発明の効果)
以上説明したとおり、本発明によれば、良好な
電力供給が可能で、回路形成精度が高く、積層ボ
イドの発生もなく、外層導体層の平坦性も良好
で、パターンを高精度で形成できる多層印刷配線
板が得られる。[Table] As is clear from Tables 1 and 2 above, the average finish value, maximum value, minimum value, and standard deviation values are all significantly improved by the method of the present invention. That is, since the method of the present invention etches both the upper and lower surfaces of a thick metal foil at once, the etching solution flows through the through holes formed by etching.
The inner wall of the through hole is also etched, creating an undercut.
Since the surface is flat with no etching residue or over-etching, the accuracy of circuit formation is improved. In addition, the etched part of the thick metal foil
Since it is filled with insulating resin, there is no level difference between the inner layer plates, and the occurrence of lamination voids can be prevented. Furthermore, the flatness of the multilayer conductor layer is also good, making it possible to form outer layer circuits with high precision. In this example, a four-layer multilayer printed wiring board using one insulating resin coated inner layer board was explained.
Of course, there is no problem in using two or more insulating resin-coated inner plates, or an inner plate formed by a conventional method. (Effects of the Invention) As explained above, according to the present invention, good power supply is possible, circuit formation accuracy is high, stacking voids do not occur, the flatness of the outer conductor layer is good, and patterns can be improved. A multilayer printed wiring board that can be formed with precision is obtained.
第1図A〜Mは従来の多層印刷配線板の製造方
法を説明するために工程順に示した断面図、第2
図A〜Uは本発明の一実施例を説明するために工
程順に示した断面図である。
1……絶縁基板、2a,2b,22,22′…
…金属箔、3a,3b,3c,3d,23a,2
3b,23a′,23b′,23c,23d……ホト
レジスト、4a,4b,4c,4d,24a,2
4b,24a′,24b′,24c,24d……ホト
マスク、6,26……内層板、7a,7b,7
c,7d,27a,27b,27c……プリプレ
グ、8a,8b,28a,28b……外層導体
層、9,29……多層化基板、10,30……ス
ルーホール、12,32……スルーホールめつ
き、13,33……多層印刷配線板、34a,3
4b……絶縁樹脂層、35……絶縁樹脂コート内
層板。
1A to 1M are cross-sectional views shown in the order of steps to explain a conventional method for manufacturing a multilayer printed wiring board;
Figures A to U are cross-sectional views shown in order of steps to explain an embodiment of the present invention. 1...Insulating substrate, 2a, 2b, 22, 22'...
...Metal foil, 3a, 3b, 3c, 3d, 23a, 2
3b, 23a', 23b', 23c, 23d...Photoresist, 4a, 4b, 4c, 4d, 24a, 2
4b, 24a', 24b', 24c, 24d...Photomask, 6, 26...Inner layer plate, 7a, 7b, 7
c, 7d, 27a, 27b, 27c... prepreg, 8a, 8b, 28a, 28b... outer conductor layer, 9, 29... multilayer board, 10, 30... through hole, 12, 32... through hole Plating, 13, 33...Multilayer printed wiring board, 34a, 3
4b... Insulating resin layer, 35... Insulating resin coat inner layer plate.
Claims (1)
膜を被着形成する工程と、前記エツチングレジス
ト被膜をマスクとして前記導体層の所望部分を表
裏両面よりエツチングする工程と、前記エツチン
グをした導体層をプリプレグを介して上下に配置
し熱圧着させて内層板を形成する工程と、前記内
層板の表面に絶縁樹脂を塗布し絶縁層を形成する
工程と、前記絶縁層を形成した内層板を一層以上
内層に配置し多層導体層をプリプレグを介して熱
圧着し多層化基板を形成する工程と、前記多層化
基板にスルーホールを形成する工程と、前記スル
ーホールを形成した多層化基板にスルーホールめ
つきを施す工程と、前記スルーホールめつきを施
した多層化基板の外層の所望の位置にエツチング
レジスト被膜を被着形成しエツチングレジスト被
膜に覆われていない箇所をエツチング除去し外層
回路を形成する工程とを含むことを特徴とする多
層印刷配線板の製造方法。1 A step of depositing an etching resist film on a desired position of the conductor layer, a step of etching a desired portion of the conductor layer from both the front and back sides using the etching resist film as a mask, and a step of forming a prepreg on the etched conductor layer. a step of forming an inner layer plate by arranging the inner layer plate one above the other and thermally pressing the inner layer plate, a step of applying an insulating resin to the surface of the inner layer plate to form an insulating layer, and a step of forming the inner layer plate with the insulating layer formed thereon on one or more inner layers. a process of arranging and thermocompression-bonding the multilayer conductor layer via prepreg to form a multilayer board; a process of forming through holes in the multilayer board; and a process of through hole plating in the multilayer board with the through holes formed. a step of depositing an etching resist film at a desired position on the outer layer of the multilayered substrate to which the through-hole plating has been applied, and etching away the portions not covered with the etching resist film to form an outer layer circuit. A method for producing a multilayer printed wiring board, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6800384A JPS60211896A (en) | 1984-04-05 | 1984-04-05 | Method of producing multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6800384A JPS60211896A (en) | 1984-04-05 | 1984-04-05 | Method of producing multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60211896A JPS60211896A (en) | 1985-10-24 |
| JPH021392B2 true JPH021392B2 (en) | 1990-01-11 |
Family
ID=13361259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6800384A Granted JPS60211896A (en) | 1984-04-05 | 1984-04-05 | Method of producing multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60211896A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100209259B1 (en) * | 1996-04-25 | 1999-07-15 | 이해규 | Ic card and method for manufacture of the same |
-
1984
- 1984-04-05 JP JP6800384A patent/JPS60211896A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60211896A (en) | 1985-10-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |