JPH02139937A - Ldd structure mosfet - Google Patents

Abstract

PURPOSE:To eliminate performance deterioration of a transistor caused by parasitic resistance of a lightly doped layer by forming the lightly doped layer on a substrate surface below a conductor film formed on the side of the gate electrode and electrically connected to the same in a self-alignment manner with respect to a gate electrode. CONSTITUTION:A gate 3 comprising polycrystalline silicon is selectively formed into a predetermined pattern on a gate oxide film 2 formed on a p type silicon substrate 1. On the side of the gate electrode 3 a polycrystalline silicon conductor film 15 is formed. On the other hand, on the surface of the substrate 1 N<-> layers 6, 7 are formed just under the conductor film 15, and N<+> layers 8, 9 are formed adjoined to the N<-> layers 6, 7 to construct a source-drain area. The N<-> layers 6, 7 and the side conductor film 15 of the gate electrode 3 exhibit an LDD structure by being overlapped in a self-alignment manner. Hereby, parasitic resistance of the N<-> layers 6, 7 as a lightly doped layer is sharply reduced to restrict the deterioration of transistor characteristics.

Description

[Detailed Description of the Invention] Industrial Application Field] The present invention provides an LD in which fluctuations in transistor characteristics are suppressed.
MOSFET (insulated gate field effect transistor) with D (Lightly Doped Drain) structure
Regarding.

[Prior Art] In MOSFETs, an LDD structure is used in order to avoid fluctuations in transistor characteristics that tend to occur as the MOSFET becomes smaller and to ensure high reliability over a long period of time.

Figure 4 shows an N-channel MOSF with a conventional LDD structure.
It is a sectional view showing ET.

Gate oxide film 22 formed on P-type silicon substrate 21
A gate electrode 23 made of a polycrystalline silicon film is formed thereon. The side and top surfaces of this gate electrode 23 are covered with silicon oxide WA 24, and a sidewall oxide film 25 is further formed on the side surfaces.

On the other hand, N- layers 26 and 27 are formed on the surface of the substrate 21 in a self-aligned manner with respect to the gate electrode 23, and
N1 layers 28 and 29 are formed in self-alignment with the gate electrode 23 and sidewall oxide film 25. In this way, the N- layer 26.27 is arranged between the end of the channel region and the N'' layer 28.29, forming the source/drain region of the LDD structure.

This LDDil MOSFET is constructed as described above, and the depletion layer at the drain junction is composed of N in the low concentration region.
- extends also into layers 26,27, thus relaxing the electric field at the train junction. Thereby, it is possible to suppress deterioration of transistor characteristics due to hot electrons due to impact ionization, etc., which becomes more noticeable due to miniaturization of MO8FET elements.

However, the MOSFET with the LDD structure described above has a source
Since a low concentration N- layer 26.27 exists between the N+J' 128, 29 of the drain region and the channel region, this N- layer 26.27 becomes a parasitic resistance. For this reason, the driving ability of the conventional MOSFET having the LDD structure is lower than that of a normal MOSFET in which the source and drain are formed of only a single heavily doped diffusion layer. Further, sidewall oxide JI! formed on the side surface of the gate electrode 23! 2
Since 5 is an insulating film, hot electrons generated by impact ionization or the like may be injected into this sidewall oxide film 25 and trapped there. Then, this trapped charge depletes the substrate surface region of the N- layer 26, 27 that exists directly under the sidewall oxide film 25, so that the - layer parasitic resistance increases and the MO of this LDD structure
SFET transistor characteristics deteriorate significantly.

In order to solve these problems, an LDD structure has been proposed in which a gate electrode and an N-layer are formed in an overlapping manner.

Figure 5 shows the MOSFET with the LDD structure described above [1
986 IEDM Technical Digest
, P 742745, Tiao-yuan Hua
ng et al.].

A gate electrode 33 having a convex portion at the center is formed of polycrystalline silicon on a gate oxide film 32 on a P-type silicon substrate 31. An oxide film 35 is formed on the gate electrode 33 so as to cover the convex portion. On the other hand, N- layers 36 and 37 are formed on the surface of the substrate 31 at positions other than the area immediately below the convex portion of the gate electrode 33, and furthermore, there are portions of the gate electrode 33 protruding laterally from the convex portion. N+ layers 38 and 39 are formed at positions other than the area immediately below. These N+ layers 38, 39 and N- layers 36, 37 constitute source/drain regions.

In the LDD structure MOSFET described above, since the N- layer 36 and 37 exist directly under the protruding end portion of the gate electrode 33, the N- layer 36 and 37 are
．． An electric field directed toward 37 is generated. For this reason, the N-layer 36.
The surface layer of the transistor 37 is changed to N+ to reduce the parasitic resistance, thereby avoiding a decrease in the driving ability of the MOSFET having the LDD structure. Also,
The existence of the N-'' layers 36 and 37 relaxes the drain electric field, making it difficult to generate hot electrons, and improving the reliability of the MOSFET with the LDD structure.

Next, a method for manufacturing the above-mentioned MOS FET will be explained step by step with reference to FIGS. 6(a) to 6(d).

First, as shown in FIG. 6(a), a P-type silicon substrate 3 is
After forming a gate oxide 132 on the entire surface, a polycrystalline silicon film 33a is grown to a thickness of 3,000 to 4,000 wafers on the entire surface, and then an oxide film 30 is grown on the entire surface by a vapor phase growth method. After depositing the oxide film 30 to a thickness of about 100 mL, a resist 34 is formed into a desired gate electrode pattern on the oxide film 30 using photolithography or the like.

Next, as shown in FIG. 6(b), the polycrystalline silicon film 33a is selectively anisotropically etched using the resist 34 as a mask. In this case, polycrystalline silicon film 33a
The etching is not completely removed by etching, but only a thickness of 500 to 1000 layers remains before etching is completed.

Phosphorus is ion-implanted into the substrate 31 with an acceleration energy that can pass through the remaining polycrystalline silicon film 33a having a thickness of 500 to 1000 nm to form N- layers 36 and 37.Next, the resist 34 is removed.

Next, as shown in FIG. 6C, an oxide film 35 is deposited over the entire surface to a thickness of about 2,000 to 5,000 wafers using a vapor phase growth method or the like.

Thereafter, as shown in FIG. 6(d), the oxide film 35 is subjected to anisotropic selective etching so that the oxide film 35 remains only on the gate electrode 33 and its side surfaces, and the oxide film 35 in other areas is etched. Remove. Then, using the remaining oxide film 35 as a mask, the polycrystalline silicon film 33a is selectively etched and removed.

Next, as shown in FIG. 5, by ion-implanting arsenic, for example, N+ is formed in the oxide film 35 in a self-aligned manner.
Layers 38 and 39 are formed.

[Problem to be solved by the invention] However, the above-mentioned LDD structure MOSFET has the following problems:
In the manufacturing process, the polycrystalline silicon film 33a is etched to a desired thickness as shown in FIG.
It is extremely difficult to control the impurity concentration of the N- layer 36, 37 to a desired concentration because it is necessary to ion-implant the impurity for forming the N- layer 36, 37 so as to pass through a. That is, the rate at which impurities for forming the N- layers 36 and 37 pass through the polycrystalline silicon film 33a and reach the silicon substrate 31 is greater than the polycrystalline silicon tl! Although it depends on the remaining film thickness of 33a, it is extremely difficult to precisely control the etching conditions so that the remaining film thickness becomes the same within the same wafer and among many wafers. Therefore, there is a drawback that it is difficult to obtain N-NJ36.37 with a desired impurity concentration.

Furthermore, after forming an oxide film 35 on the entire surface, the gate electrode 33
Even in the process of controlling the anisotropic selective etching to stop so that the oxide film 35 remains only on the top and side surfaces of the formation area, there is a problem in the reproducibility of the etching amount, and it is difficult to leave the oxide film 35 in the desired shape. It is difficult to do so.

As described above, the conventional LDD structure MOSFET has the problem of being extremely difficult to manufacture and lacking in practical use.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a MOSFET with an LDD structure that can avoid deterioration in transistor performance due to parasitic resistance of a low concentration impurity layer and can be manufactured easily and with high reproducibility.

[Means for Solving the Problems] A MOSFET manufactured by LDDl'i according to the present invention includes a gate electrode formed on the surface of a first conductivity type semiconductor substrate with a gate insulating film interposed therebetween, and a gate electrode formed on the side surface of the gate electrode. a conductive film formed to be electrically connected to the gate electrode; and a second conductivity type high concentration impurity in source and drain regions formed on the surface of the semiconductor substrate in a self-aligned manner with respect to the gate electrode and the conductive film. and a second conductivity type low concentration impurity layer formed on the surface of the semiconductor substrate below the conductive film on at least the train region side in a self-aligned manner with respect to the gate electrode.

[Function] In the present invention, a conductive film electrically connected to the gate electrode is formed on the side surface of the gate electrode, and a conductive film is formed on the substrate surface below the conductive film on at least the drain region side to connect to the gate electrode. A low concentration impurity layer is formed in a self-aligned manner. Further, since the gate electrode and the conductive film are electrically connected, the conductive film acts as a part of the gate electrode. Therefore, since the low concentration impurity layer is placed below the conductive film that forms part of the gate electrode, an electric field is generated from the gate electrode toward the low concentration impurity layer, reducing parasitic resistance and deteriorating transistor performance. can be avoided.

With this structure, the gate electrode and the conductive film can be formed in separate steps, so for example, after forming the gate electrode, a low concentration impurity layer is formed in a self-aligned manner with respect to the gate electrode, Next, after forming a conductive film, a high concentration impurity layer can be formed in a self-aligned manner with respect to the conductive film and the gate electrode. This makes it possible to avoid the conventional difficult process of controlling the anisotropic selective etching to stop at the desired residual film thickness.
It becomes easier to manufacture an IL-based MOSFET and improves reproducibility.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention, P
Gate oxide film 2 formed on a silicon substrate 1
A gate electrode 3 made of polycrystalline silicon is selectively formed thereon in a predetermined pattern. A conductive film 15 of polycrystalline silicon is formed on the side surface of this gate electrode 3. On the other hand, an N- layer 6.7 is formed on the surface of the substrate 1 directly below the conductive film 15, and N+ layers 8 and 9 are formed adjacent to this N- layer 6.7.

In this embodiment, the source/drain regions are N+ layers 8
.

Then, the N- layers 6 and 7 and the sidewall conductive film 15 of the gate electrode 3
They overlap in a self-aligned manner and have a DD tank structure.

Next, the manufacturing method of this example will be explained.

Figures 2 (a) to (d) show the MOS of this LDDtll construction.
FIG. 3 is a cross-sectional view showing a method for manufacturing an FET in order of steps.

First, as shown in FIG. 2(a), a P-type silicon substrate 1 is
A gate oxide film 2 is formed thereon, and then a polycrystalline silicon film 3a is deposited to a thickness of 3000 to 6000 nm.

Next, the oxide film 12 is grown to a thickness of 500 to 3000 nm using a vapor phase growth method or the like. Then, a resist 16 is selectively formed in the region where the gate electrode 3 is to be formed by photolithography or other lithography techniques.

Thereafter, as shown in FIG. 2(b), this resist 16
Using this as a mask, anisotropic selective etching is sequentially performed on the oxide film 12 and the polycrystalline silicon film 3a to form the gate electrode 3.

Next, in a self-aligned manner with respect to the remaining oxide film 12 and gate electrode 3, for example, phosphorus is
Ion implantation is performed under conditions of 0 KeV and a concentration of about 1013 to IQ cm- to form an N- layer 6.7.

Next, as shown in FIG. 2C, for example, a polycrystalline silicon film 15a is applied as a conductive film over the entire surface with a thickness of 1000 to 300.
Deposited to a thickness of 0 people.

Next, as shown in FIG. 2(d), this polycrystalline silicon film 15a is selectively anisotropically etched so that it remains only on the side surfaces of the gate electrode 3, and the other parts are removed to form a polycrystalline silicon film 15a. A sidewall conductive film 15 made of silicon is formed. Thereafter, using the oxide film 12 and the conductive film 15 as a mask, ions of, for example, arsenic are implanted into the surface of the substrate 1 under conditions of an acceleration energy of 40 to 7 O-KeV and a concentration of 1015 to 10" cm -2, thereby forming a self-aligned structure. N+ layers 8 and 9 are formed thereon.

Since the LDD structure MOSFET of this example has the above-described structure, it is necessary to use a technique with poor reproducibility, such as controlling the stop of anisotropic selective etching with high precision to obtain a desired residual film thickness. do not have.

Therefore, it is easy to manufacture and has excellent reproducibility. Further, an N- layer 6 which is a low concentration impurity layer is provided on the substrate surface below the conductive film 15 electrically connected to the gate electrode 3.
, 7 are provided, the parasitic resistance of this lightly doped impurity layer is significantly reduced, and deterioration of transistor characteristics can be suppressed.

FIG. 3 is a cross-sectional view showing a second embodiment of the present invention. This embodiment differs from the first embodiment in that the gate electrode 3 is made of two layers of a polycrystalline silicon film 3b and a silicide film 13. The rest of the structure is basically the same as that of the first embodiment, so in FIG. 3, the same parts as in FIG. Detailed explanation will be omitted.

In this embodiment, as described above, the gate electrode 3 has a so-called polycide structure composed of two layers of the polycrystalline silicon film 3b and the silicide film 13.

As a result, the same effects as in the first embodiment can be obtained, and the resistance of the gate wiring is reduced, so that the characteristics of the MOSFET in high-speed operation are improved.

Further, since the upper part of the gate electrode 3 is the silicide film 13, the conductivity type of the conductive film 15 on the side surface of the gate electrode 3 can be arbitrarily selected. This allows the conductive film 1 to optimize the barrier potential between the conductive film 15 on the side surface and the substrate 1.
Since conductivity type 5 can be selected, N-7 below the conductive film 15 can be selected.
The surfaces of layers 16 and 7 can be made to have resistance to waste paper.

[Effects of the Invention] In the LDD structure MOSFET according to the present invention, a conductive film electrically connected to the gate electrode is formed on the side surface of the gate electrode, and a gate is formed on the substrate surface below the conductive film. A low concentration impurity layer is formed in a self-aligned manner with respect to the electrode. Thereby, performance deterioration of the transistor due to parasitic resistance of the lightly doped impurity layer can be avoided. Furthermore,
Since the gate electrode and conductive film can be formed in separate processes,
It is easy to manufacture, has excellent reproducibility, and has the effect of significantly improving reliability.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a first embodiment of the present invention, and FIG.
a) to (d) are cross-sectional views showing the manufacturing method in the order of steps, FIG. 3 is a cross-sectional view showing the second embodiment of the present invention, and FIG. 4 is a cross-sectional view showing a conventional LDD structure MOS FET. Figure 5 shows a conventional improved LDD structure MOSFE.
A sectional view showing T, and FIGS. 6(a) to 6(d) are sectional views showing the manufacturing method in the order of steps. 1.21, 31; p-type silicon substrate, 2.22°32;
Gate oxide film, 3, 23, 33; Gate electrode, 3a, 3
b; Polycrystalline silicon film, 6, 7, 26. 27, 36, 3
7; N-layer, 8,9,28°29.38,39. N+ layer, 12, 35: oxide film, 13; silicide film, 15; conductive film, 16, 34; resist, 25; sidewall oxide film

Claims (1)

[Claims] (1) a gate electrode formed on the surface of a first conductivity type semiconductor substrate via a gate insulating film; a conductive film formed on the side surface of the gate electrode in electrical connection with the gate electrode;
a second conductivity type high concentration impurity layer in the source and drain regions formed on the surface of the semiconductor substrate in a self-aligned manner with respect to the gate electrode and the conductive film; and the semiconductor below the conductive film on at least the drain region side. M of an LDD structure, characterized in that it has a second conductivity type low concentration impurity layer formed on the substrate surface in a self-aligned manner with respect to the gate electrode.
OSFET.