JPH021423B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image transmission method, and particularly to an image transmission method that reduces transmission information when image information is divided into predetermined blocks and transmitted sequentially.

In order to reduce the time required to transmit image information in a facsimile, etc., a series of pixel signals is divided into blocks, and each block is checked to see if it contains a black signal or not. In place of the pixel signal, a control signal shorter than the pixel length of one block is sent out, and for a block containing a black signal, the pixel signal of that block is sent out as is without adding a control signal. Bandwidth compression methods are known. According to this method, the position and length of each block are fixed, so that for a white pixel signal string at any consecutive position of one block length, that signal string becomes all the pixel signals of the block. What we get is a probabilistic problem, and furthermore, in a certain block,
Although one block length is not satisfied, there is a drawback that the transmission time of the signal string cannot be shortened even if there is a continuous white pixel signal string of a length to be considered.

An object of the present invention is to provide an image transmission method that can shorten the time required for image transmission when image information is divided into predetermined blocks and transmitted sequentially, in view of the drawbacks of the conventional example described above. be.

In particular, the present invention stores information regarding the data content and data length of the transmitted block, and based on this stored information, determines whether or not the data to be transmitted thereafter is the same as the data of the transmitted block, and determines whether the data is the same as the data of the transmitted block. An object of the present invention is to provide an image transmission method in which, when the data is determined, a copy signal indicating that the data is the same as the transmitted block data is transmitted, thereby omitting the actual transmission of the data. This example will be described in detail below.

In this embodiment, a skip signal is transmitted for all-white basic block strings that are consecutive for a predetermined number N, and for all-white (or black) basic block strings that are consecutive for an arbitrary number M less than or equal to N/2. is followed by the same number of consecutive all-white (or black) basic blocks as the number M of consecutive all-white (or black) basic blocks, all pixel signals belonging to the subsequent all-white (or black) basic block string are A configuration is used that reliably shortens the transmission time of a somewhat continuous all-white (or black) signal string existing at an arbitrary position by transmitting a copy signal instead of the transmission.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the embodiment of the present invention, one basic block is composed of 8 bits. When a white image signal exists for 8 consecutive bytes, a control signal (hereinafter referred to as a skip signal) that is 1 byte long and has an amplitude three times the amplitude of the transmitted image signal is sent, and all white (or black) basic blocks are transmitted. When two all-white (or black) basic blocks continue immediately after two consecutive blocks, and when eight all-white basic blocks continue immediately after the skip signal is sent, the amplitude is twice the amplitude of the transmitted image signal. A 1-byte long control signal (hereinafter referred to as a copy signal) with a length of 1 byte is sent, and in the case of a string of all white (or black) basic blocks that are not consecutive for 4 or more blocks and a block in which black and white are mixed in one basic block, that block is All pixel signals contained within are sent out.

This sending rule is illustrated in FIG. 1a.
In this figure, immediately after processing state (1), state (2)
When the condition (2) continues, the signal in the matrix is sent out instead of sending the pixel signal in (2). For example, if 6 bytes of white pixels continue after sending 1 black byte, the first 2 bytes of white pixels will be sent as is, and 2 bytes of copy signal will be sent to the next 4 bytes of white pixels. Send. Further, if 4 bytes of black pixels continue after 1 byte of white pixels are sent, 2 bytes of black pixels and a copy signal are sent. In this case, the skip signal, copy signal, and image signal (white) sent in FIG. 1a are each 1 byte long as shown in FIG. 2b, and the skip signal and copy signal are each an image signal It has an amplitude three times and twice that of the previous one.

A more specific example is shown in FIG. 2, where the image signal sequence shown in FIG. 2a has the levels shown in FIG. 2b. First, there are 8 consecutive blocks (8 bytes) of white, so the second
A skip signal _C1 is sent as shown in Figure c, and
Next, after 2 bytes of white image signal _C2 are sent,
Since there are two consecutive blocks of white, the skip signal _C3 is sent out instead, and then, since there are two consecutive blocks of black, the black picture signal _C4 is sent out as is.
Thereafter, since there are four consecutive black blocks, two bytes of skip signals C ₅ and C ₆ are sent out, and then the image signal C ₇ of the white block is sent out as is.

FIG. 3 shows a block diagram of the transmitter circuit used in the method of the invention. Reference numeral 1 denotes a known document reading device that decomposes information on a document (not shown) into pixels and reads them in units of scanning lines, and the read image signals are sequentially stored in a line memory 2. The line memory 2 is composed of a shift register having a capacity of, for example, 2048 bits, and is capable of storing pixel signals read out from an original document corresponding to one scanning line. The pixel signal from this line memory 2 is input to an 8-byte shift register 3 via a signal line 1a. Transfer to line memory 2 and shift register 3 is via signal line 1 from transfer bit counter circuit 5.
It is controlled by the clock appearing at _h .

Reference numeral 8 denotes a clock generator that generates a clock with a constant frequency _f on the signal line _1e . Generate bite clock.
This byte clock is inputted to a monostable multivibrator (M/M) 0, a judgment circuit 6, and a transmission data control circuit 12, respectively, and these circuits are operated in units of bytes according to this clock. Further, the frequency of the clock having the frequency f is divided by 8/n by the 8/n frequency divider 9', and a sampling clock whose frequency is divided by 8/n is generated on the signal line _1y , and this sampling clock is sent to the shift register 11. The signal from the signal line _1b that is input to the shift register 11 is sampled and output to the signal line _1c .
Furthermore, the signal line _1e is also input to a transfer bit counter circuit 5, which is operated by a clock having a frequency f.

The 8-byte parallel data from the shift register 3 is latched into the latch circuit 4 by a signal appearing on the signal line _1q of the transfer bit counter circuit 5. The content of this latched data is determined by the determining circuit 6 in synchronization with the byte clock on the signal line _1f , and the signal pattern to be transmitted next is determined. If it is determined to send a skip signal, it outputs a skip signal ready to the signal line _1t and an 8-byte transfer ready signal to the signal line _1n , thereby preparing the next data transfer to the shift register 3. When it is determined that a copy signal is to be sent, a copy signal ready signal is output to the signal line 1 _u , and a 2 or 8 byte transfer ready signal is output to the signal line 1 _o or 1 _n . If it is determined that an image signal is to be sent, a 1-byte transfer ready signal is generated on the signal line _1p .
All of these judgments are made when the data in the shift register 3 is latched, that is, when the output _1q of the transfer bit counter circuit 5 becomes "1" as will be described later. A more detailed explanation of this decision circuit 6 will be given later in connection with FIG.

7 is a transmission pattern storage circuit. Judgment circuit 6
The determination result is held until the next byte clock arrives, and the transmission pattern information one byte clock past is fed back to the determination circuit 6. The output of signal line _1j becomes ``1'' when 8 blocks of all-white basic blocks were transmitted in the previous byte clock, and the output of signal line <sub>1k</sub> becomes ``1'' when 8 blocks of all-white basic blocks were transmitted as a 2-block copy signal or an image signal in the previous byte clock. 1", and the output of _1l becomes "1" when two all-black basic blocks were previously transmitted as a copy signal or an image signal. If the outputs of 1 _j , 1 _k and 1 _l are all "0", it means that one basic block of pixel signals was transmitted in the previous byte clock. This circuit is explained in detail in FIG.

5 is a transfer bit counter. When the data in the shift register 3 is latched, the transfer information, that is, the 8, 2, and 1 byte transfer ready signals appearing on the signal lines 1 _n , 1 _o , and 1 _p from the judgment circuit are set, and the next data is transferred to the shift register 3. The number of transfer clocks _1h to be transferred to is notified. A monostable circuit (M/M) 10 generates a pulse 1 _g at the falling edge of the byte clock 1 _f . _1g is the start pulse of the transfer bit counter 5. The transfer bit counter counts the clock _1e by the number of transfer bits, and when the count is finished, it outputs a pulse _1q to operate the latch circuit 4 to latch the data in the shift register 3, and also to connect the signal lines _1n and _1o to the above. , 1 Set the information of _p . The transfer bit counter 5 will be explained in detail in FIG.

11 is a shift register for one basic block. The first byte of the latched shift register 3 is taken in by pulse _1z , and sequentially outputted bit by bit to _1c using data sample clock _1y . The pulse _1z is generated by the monostable circuit 10 at the time when four inversions of the sampling clock _1y are counted from the falling edge of _1f . (Figure 12a
- c).

12 is a transmission data control circuit. Judgment circuit 6
The transmission pattern judgment data from, that is, the outputs of signal lines 1 _t and 1 _u are set immediately before the rising edge of 1 _f , which is the transmission start timing. This 1 _t , 1 _u
Synchronize the output information with clock _1f and connect it to signal line 1.
Output to _v , 1 _w , 1 _x . The output of _1v is the image signal transmission control output, and when the output of _1v is "1", the output of the skip signal control line _1w and the output of the copy signal control line _1x is "0", the output of the OR gate 14 is The output of the OR gate 15 becomes the serial image signal data which is the output of the shift register 11. Similarly, when either the output of 1 _w or 1 _x is "1", the output of the OR gate 14 becomes high level and the output of the OR gate 15 also becomes high level. 13 is an amplitude control circuit, which controls the output amplitude of the OR gate 15 using control lines 1 _v , 1 _w , 1 _x
It is adjusted according to the state of and output to signal line _1d . That is, when sending a skip signal, the amplitude is set to three times the image signal (white), and when sending a copy signal, the amplitude is set to twice the image signal (white).

FIG. 4 shows detailed circuits of the latch circuit 4 and the judgment circuit 6. Latch circuit 4 is A ₀ ~ _{A 7}
, and outputs 8-bit parallel output data from the shift register 3 to outputs _Q0 to _Q7 , respectively. The monostable multivibrator circuit 26 is activated by the byte clock appearing on the signal line _1f , and generates a pulse on the signal line _1p with a certain delay from the rising edge of the byte clock (see FIG. 12g). The outputs 1 _j , 1 _k , and 1 _l of the transmission pattern storage circuit 7 are set by this pulse on the signal line 1 _p . That is, since the transmission pattern information of the previous basic block appears at the outputs 1 _j , 1 _k , 1 _l of the transmission pattern storage circuit 7, this information is set by the byte clock. For example, if the previous 8 blocks were all white information and were sent as a skip or copy signal, a signal of "1" was sent to signal line _1j , and the 2 blocks before 2 byte clocks were all white information and either a copy signal or an image signal. When sending 2 _blocks as
When the two blocks before the byte clock are all black information and two blocks are transmitted as a copy signal or an image signal, a signal of ``1'' appears on the signal line _1l . Also, when the image signal of one basic block was transmitted last time, "0" signals appear on the signal lines _1j , _1k , and _1l .

The output of the signal line 1 _j is input to an AND gate 20 and is also inverted and input to an AND gate 19 . Further, the pulse on the signal line 1 _k is input to an AND gate 21 , and the pulse on the signal line 1 _l is input to an AND gate 22 .

The 8-bit outputs of each of the latch circuits Q ₂ to _{Q 7} are input to the AND gate 16 via the corresponding AND gates, and the ANDed signal of the 8-bit output of Q ₁ is input to the AND gate 17.
Also, a signal obtained by ANDing the inverted outputs is input to the AND gate 17'. Furthermore, the 8-bit output of Q ₀ is logically ANDed, and the logically ANDed signal of the inverted output is output to AND gates 17 and 1, respectively.
7' is applied to the other input. and gate 1
The output of 6 directly appears on the signal line 1 _n and is applied to AND gates 19 and 20, and the inverted output of AND gate 16 is input to AND gate 21. The output of AND gate 17 is input to AND gates 16 and 21, and the output of AND gate 17' is input to AND gate 22. Furthermore, the outputs of the AND gates 21 and 22 are input to an OR gate 24.

The determination circuit 6 further includes signal lines 1 _t , 1 _u , 1 _o ,
1 _p , 1 _n , 3 _d , 1 _r , 3 _z , the signal line 1 _t receives the output of the AND gate 19, and the signal line 1 _u receives the logical sum of the output of the AND gate 20 and the OR gate 24 (OR gate 23) appears. Also, the output of the OR gate 24 is on the signal line 1 _o , and the gates 24 and 16 of the NOR gate 25 are on the signal line 1 _p .
An inverted signal of the logical sum appears, and the output of the AND gate 16 appears on the signal line _1n . Signal line _3d ,
The AND output of the latch output Q ₀ and its inverted AND output appear on 3 _e , and the outputs 3 d and 3 _d appear on the signal line 1 _r .
3 The AND of the inverted signals of _e appears.

Therefore, the logical formula for these circuit configurations is 1 _n = (3 _a ) · (1 _j ) + (3 _a ) · (1 _j ) = 3 _a 1 _o = (3 _a ) · (3 _b ) · (1 _k ) + (3 _c )・(1 _l ) 1 _p = (1 _o ) + (1 _n ) 1 _t = (3 _a )・(1) 1 _u = (3 _a )・(1 _j ) + (1 _o ) becomes.

The signal line 1 _t of the judgment circuit 6 configured in this way
The skip signal ready is generated and the skip is performed when the AND gate 19 is turned on, that is, when the previous 8 blocks contain at least one piece of black information and the signal line _1j is a "0" signal. This is when the current (subsequent) 8 blocks are all white information and the AND gate 16 is turned on. Also, the copy signal ready appears on the signal line 1 _u and the copy signal is sent when any one of the AND gates 20, 21, and 22 is turned on. For example, all 8 blocks from the previous and current times are When the AND gate 20 is turned on with all white information, or when the 2 blocks before 2 byte clocks and the first 2 blocks of this time are white information and the AND gate 21 is turned on, or when the 2 blocks before 2 byte clocks and the first 2 blocks of this time are turned on. This is when the first two blocks are all black information and the AND gate 22 is turned on.

Also, when all eight blocks are white information, a high level signal appears on the signal line _1n , and the 8-byte transfer ready signal turns on.Therefore, a transfer signal appears on the output _1h of the transfer bit counter circuit 5.
The line memory 2 and shift register 3 are now in a state where 8 bytes, that is, 8 blocks can be transferred. Also, when the first two blocks of the current two blocks two byte clocks ago are all white information or all black information, a 2-byte transfer ready signal appears on signal line _1o , and line memory 2 and shift register 3
Byte transfer becomes possible. Further, when sending out a uniform image signal in which black and white are mixed on the current and previous clocks, a 1-byte transfer ready signal appears on the signal line _1p , and the line memory 2 and shift register 3 become ready for 1-byte transfer.

Also, when the first block is all white information, the output of signal line _3d becomes "1", the output of signal _{line 3e} becomes "0",
Also, when all the information is black, the output of signal line _3d is "0"
Therefore, the output of _3e becomes "1". On the other hand, if black and white information is mixed in the first block, signal line 3
The outputs of both _d and _3e become "0", and the output of signal line _1r becomes "1".

5 and 6 show organized logical tables of the number of bytes to be transferred to the shift register 3 described above in the judgment circuit of FIG. 4. FIG. 5 shows the shift register 3, which consists of 8 cells each consisting of 8 bits, and the outputs of each cell are logically ANDed to form a ₀ to a ₇ , b ₀ , b _{1 ,} respectively. Output. Each of these outputs is connected to latch circuit 4 in FIG.
corresponds to each AND output of outputs Q ₀ to Q ₇ .

In Figure 6, "H" indicates high level, "L" indicates low level, and "X" indicates "H" or "L".
Show that either is fine.

FIG. 7 shows the transmission pattern storage circuit 7, in which the byte clocks from the signal line _1p are connected to the clock inputs of D flip-flops 33 to 35, respectively, and the D inputs when the byte clocks are input,
That is, the outputs of the signal line 1 _n , the output signal line 4 _j of the OR gate 31, and the output signal line 4 _k of the OR gate 32 are generated as respective Q outputs. Each Q output of flip-flops 33 to 35 becomes signal lines 1 _j , 1 _k and 1 _l . As described above, the signal line _3d of the judgment circuit 6 becomes "1" when the first block is completely white, and this signal is input to the AND gates 27 and 36. Further, a 2-byte transfer ready signal appears on the signal line 1 _o and is input to the AND gates 27 and 29. A 1-byte transfer ready signal appears on the signal line _1p and is input to AND gates 28, 30, 36, and 37. Also, the signal line _3e , which becomes "1" only when the first block is completely black, is connected to the AND gates 29 and 37.
is input.

Also, the byte clock connects the signal line to D via 1 _f .
The clock inputs of flip-flops 38 to 41 are connected to signal lines 1 _r
It is reset by the OR gates 42 and 43 via the OR gates 42 and 43 when black and white information is mixed in the block.

AND gates 36, 37, flip-flop 3
8 to 41, and the circuit consisting of OR gates 42 to 43 outputs the Q output 4 _e of the flip-flop 39 (when it is black, the Q output of the flip-flop 41 This is a circuit that sets the Q output 4 _f ) of 1 to 1.

For example, when two all-white blocks are sent as a full-picture signal (16 bits) as a white signal, the transmission pattern storage circuit stores the transmission pattern as follows. In other words, each of the latch outputs Q ₀ and Q ₁ is completely white, and the judgment circuit 6 outputs "1" to the signal line 3 _d .
"0" is output to _3e , and since a 1-byte transfer ready signal is output, signal line _1p outputs "1". Therefore, the output _4a becomes "1" through the AND gate 36, and the flip-flop 38 is turned on at the rising edge of the byte clock appearing on the next signal line _1f .
Q output _4c becomes "1". Output _4c resets flip-flops 40 and 41 via OR gate 43 and at the same time becomes the D input of flip-flop 39, so at the next byte clock, output _4e of flip-flop 39 is turned on and two consecutive all-white blocks are transmitted. Show that. This is because, for example, if an all-white basic block is followed by an all-black basic block, the output of the signal line _3e will be "1" and the signal line _3d will be "0", so the output _4d of the flip-flop 40 will be the rising edge of the byte clock. "1"
Therefore, flip-flops 38, 39
is reset and the output _4e becomes "1". Also, when a basic block with mixed black and white follows one all-white basic block, the output of the signal line 1r becomes "1 _" at that point. 1" and resets the flip-flops 38 to 41, so the output _4e becomes "0".
becomes. Furthermore, when the output _4e becomes "1" and the flip-flop 34 operates with the byte clock of the signal line _1p , and its Q output _1k turns on, the flip-flops 38 and 39 are reset and the output _4e becomes "0". Become.

When two all-black basic blocks continue and their full-picture signals are sent out, the Q output _4f of the flip-flop 41 becomes "1" in the same manner as described above. Therefore, when two consecutive all-white or all-black blocks are sent out as they are, the byte clock appearing on the signal line _1p causes the Q outputs _1k or 1l of the flip-flops 34 and ₃₅ to become "1", respectively. ”, and it is stored that 2 bytes of the same image signal were transmitted for all 8 bits (Since the image signal is sent, the output of signal line 1 _p is “1”.) Also, the output of signal line 1 _n is “1”. Assuming that the 8-byte transfer is ready, the Q output of the flip-flop 33 becomes "1" by the next byte clock _1p , and the output "1" is output on the signal line _1l .
It remembers that the skip block signal was sent by means of the copy signal. In addition, a 2-byte transfer ready signal is output and "1" is generated on signal line _1o , the first block is completely white, and the output on signal line _3d is "1".
Then, the output _4j of the OR gate 31 is turned on, and the output _1k of the flip-flop becomes ``1'' by the pulse on the signal line _1p , and it is stored that the copy signal has been sent. As described above, even when a 2-byte white image signal is sent with 2 bytes of all white, it becomes "1", so it is stored that the image signal is a copy signal and 2 all-white blocks were sent.

Similarly, when an output of ``1'' appears on the signal line _1l , it is remembered that two all-black blocks have been transmitted by either the image signal or the copy signal.

Figure 8 a to d are signal lines 1 _f , 1 _p , 1 _q , 4 _l , 4 _f
In the timing chart of the signals appearing in 1 _f , 1 _p
The output waveforms each have a frequency of f/64 and are byte clocks. The outputs of the signal lines 1 _n , 1 _o , 1 _p , 1 _r , 3 _e and 3 _d are set by the pulses shown in FIG. 8 c, and the outputs 4 _e and 4 _f are set by the pulses shown in FIG. 8 d. The output of is set.

A specific circuit diagram of the transfer bit counter circuit 5 is shown in FIG. The start pulse of signal line _1g is input to the APE terminal of counter 47,
Also, the inverted signal is sent to the flip-flop 49.
is input to the set terminal of Signal line 1 _n , 1 _o , 1
The 8, 2, and 1 byte transfer ready signals of _p are input to the J ₆ J ₄ J ₃ terminals of the counter 47, and when each output becomes "1", the counter 47 is set to 64, 16.8, respectively.
Set to the value of Also, clock 5 of signal line 1 _e
is input to the AND gate 46. The other terminal of the AND gate 46 is connected to the Q of the flip-flop 49.
Output 6 _a is input. The output 1 _h of the AND gate 46 serves as a clock input to the counter 46 and also serves as a transfer clock for the shift register 3 and line memory 2. Carry terminal CY of counter 47
and signal line _4e are connected to a NOR gate 48 whose output _6b is applied to the clock input. The output of the flip-flop 49 is connected to the signal line _1q , and as described above, the signal lines _1n , _1o , _1p , _1r , _3e , 3
At the same time, the output of _d is set, and the 8-byte information input to the latch circuit 4 is latched.

In the transfer bit counter circuit having such a configuration, a start pulse as shown in FIG. 10b appears on the signal line _1g in synchronization with the byte clock shown in FIG. 10a. As shown in Figure 10h
Assuming that an output "1" appears on the signal line 1 _n during the period t ₁ and an 8-byte transfer ready signal appears, the counter 47 is set to 64. Furthermore, the flip-flop 49 is set by the start pulse _G1 , and a high level signal is generated at its Q output as shown in FIG. 10c. As a result, a clock of frequency f appears at the output of the AND gate 46 as shown in FIG. 10d, and the counter 47 counts this clock. As the count progresses and 64 clocks are counted, the CY terminal outputs "1", which generates a pulse _B1 as shown in Figure 10e, which changes the output of signal line _1q to "1". do. At the same time, the output _6a becomes "0" and the AND gate 46 is turned off, so the counter 47 stops counting. When a signal "1" appears on the signal line _1q , the data in the shift register 3 is latched by the latch circuit, and the transfer information from the determination circuit is set.

Further, in the period _t2 , a 1-byte transfer ready signal appears on the signal line _1p , and the counter 47 is set to 8. The counter 47 counts 8 clocks f by the start pulse _G2 (Fig. 10d)
Then, as described above, an output of "1" is generated on the signal line _1q (FIG. 10f).

A shift register 11 is illustrated in FIG. The first byte (8 bits) of the shift register 3 is loaded by the pulse appearing on the signal line _1z , and sequentially output bit by bit to the signal line _1c by the data sample clock appearing on the signal line _1y .

Next, the operation of the transmitter configured in this way is explained in the first
This will be explained with reference to FIGS. 2 and 13.

First, the image information of the document read by the reading device 1 is sequentially transferred to the line memory 2 and shift register 3 in accordance with the clock of the signal line _1h .
Shift register 3 stores 8 blocks (64 bits) of information. Assume that each block is reading information in which black and white information is mixed. The determination circuit 6 is operated by the byte clock appearing on the signal line _1f shown in FIG. 12a, and the _Q0 to _Q7 outputs of the latch circuit 4 are determined. In such a case, the determination circuit 6 generates a 1-byte transfer ready signal on the signal line 1 _p and outputs "1" on the signal line 1 _r , as described above. No output is generated on other signal lines. In addition, the shift register 11
The first block of the shift register 3 latched by the pulse appearing on the signal line _1z is taken in as shown in _FIG . send out a signal. In this case, the outputs of the signal lines 1 _t and 1 _u are "0", so the output of the image signal control line 1 _v of the transmission data control circuit 12 is "1", and the image signal of the signal line 1 _c is transmitted to the amplitude control circuit 13 The signals are sequentially sent out from the signal line _1d without amplitude control.

Further, the transfer bit counter circuit 5 is operated by a start pulse appearing on the signal line _1g to operate the counter 47. Since the 1-byte transfer is now ready, the counter 47 is set to "8". Eight transfer clocks appear on the signal line _1h until the counter 47 is decremented to "0", and the line memory 2,
One block (8 bits) is transferred to each shift register 3, and at the same time, its contents are latched into a latch circuit 4 by a latch pulse.

Since it is assumed that each block contains a mixture of black and white information, each image signal is sent to the signal line _1d using the same operation as described above. The bold line in FIG. 3 shows this flow.

On the other hand, it is assumed that a portion of the document with considerable white information is entered and eight blocks of completely white information shown at _H1 in FIG. 13a are latched in the latch circuit 4. At this time, in Fig. 4, the output of signal line _1j is ``0'' (assuming that there is at least black information in the previous 8 blocks), so the output of signal line <sub>1t</sub> is ``1'', indicating the skip signal ready, and the signal line 1 An 8-byte transfer ready signal is generated at _n . At this time, the transmission data control circuit 12
is “0” on the control signal lines 1 _v , 1 _w , and 1 _x, respectively.
Generates outputs of "1" and "0", and also 64 in Figure 12 e.
8 blocks are skipped by the transfer bits A, and a 1-byte skip signal having an amplitude three times that of the image signal is generated on the signal line _1d (see Fig. 12h).
part of _H1 ). When this transfer is completed, the contents of the shift register ₃ are latched by the latch pulse F1 appearing on the signal line _1q , and the signal lines _1n , _1o , _1p , _1r , _3e , and _3d are set. be done.
Furthermore, information on the signal lines 1 _j , 1 _k , 1 _l is set by the pulse P shown in FIG. 12g. The state at the end of this 8-byte transfer is shown in FIG. 13b. At this time, if the information latched in the latch circuit 4 is all white information as shown in _H2 of _FIG . 19 is turned off, AND gate 20 is turned on, and a copy signal ready appears on signal line _1u . At the same time, an 8-byte transfer ready signal is generated on signal line _1n .

At this time, it is the section shown in _H2 in Fig. 12, and the signal lines _1v , _1w , _1x are "0",
"0", "1", and as shown in Figure 12e, 64 transfer bits B appear on signal line _1h , 8 blocks are transferred, and 8-bit copies are transferred on signal line _1d . A signal appears (Fig. 12h)
part of _H2 ). The state at the time of 8 block transfer is the 13th state.
This is illustrated in Figure c, where the latch pulse
F ₂ (FIG. 12f) appears and the latching and setting operations are performed in the same manner as described above.

Next is the image signal portion _H3 of "10110000", and the image signals are sequentially sent to the signal line _1d as described above. At this time, the control line 1 of the transmission data control circuit 12
_v , _1w , and _1x are "1", "0", and "0", and the image signal is sent onto the signal line _1d without having its amplitude controlled. The contents of the shift register 3 are shifted one block by the eight transfer bits appearing on the signal line _1e shown in FIG. 12e, and then the new image information is latched by the latch pulse _F3 .
In the same operation as described above, the amount of information sent out is controlled according to the black and white information of each block.

Although not shown in FIG. 9, if the previous two blocks were white information and the current two blocks are white or black information, a copy signal ready appears on the signal line _1u , and a copy signal ready appears on the signal line _1o . A byte transfer ready signal is generated, a copy signal is generated on signal line 1 _u , and 2
It is understood that bytes are transferred. Furthermore, the first
It is easily understood that skip signals, copy signals, image signals, etc. are also sent to other signal trains as shown in the figure.

Although the synchronization signal indicating the beginning of one line has been omitted in the above explanation, a method is conceivable in which the synchronization signal has the same amplitude as the skip signal, but only the signal length is changed. 8 bytes of synchronization signal, signal line 1 _y ,
Transmission time of each chart No. 1 to No. 8 created by CCITT when transmitting using AM-PM-VSB modulation method with 1 _f frequency of 7740 Hz and 967.5 Hz and total number of pixels of 1 line 1226 bits The 14th
As shown in the figure. (The linear density in the sub-scanning direction is 3.85/mm.
).

Figure 14 uses the CCITT test chart,
This figure shows the transmission time obtained by the method of the present invention when transmitting at a recording density of 3.85 in/mm. That is, when examining the transmission time using eight types of test charts with different image densities and contents, for example, chart #1 requires 45.5 seconds and chart #5 requires 74 seconds. And chart #1~
The average value up to #8 is 79 seconds. On the other hand, CCITT
Using the G standard, 3 minutes (180 seconds) is required regardless of the content of the test chart, so it can be seen that the method of the present invention can achieve a significant compression effect.

As described above, the information forming apparatus according to this embodiment converts a basic block consisting of a plurality of pixels into one
As a unit, basic blocks with a mixture of black and white and 4
For a string of all-white (or all-black) basic blocks that are not continuous for more than 8 blocks, a full-picture signal in the block string is sent, and for a string of all-white basic blocks that are continuous for 8 blocks, a skip signal is sent. When a skip signal is sent, the following data is 8 consecutive blocks of all white, and when 2 blocks of continuous all white (black) is sent as an image signal or a copy signal, the subsequent data is 2 blocks of continuous all white (black). By sending a copy signal to the subsequent signal sequence, the time required to transmit four or more consecutive blocks of the same image signal can be reliably shortened.

In the embodiment described above, two basic blocks containing the same pixel signal are consecutive, and then two consecutive basic blocks are used. The present invention can also be applied to cases where basic blocks containing pixel signals are continuous, and then the same number of continuous basic blocks with the same pixel signals appear.

Furthermore, although the skip signal and the copy signal differ from the image signal in the above embodiment only in amplitude, the skip signal, the copy signal, and the image signal each differ from each other in amplitude, phase, signal length, or a combination thereof. Of course, it can be identified by reading it.

As described above, according to the present invention, information regarding the data content and data length of the transmitted block is stored, and based on this stored information, it is determined whether the data to be transmitted thereafter is the same as the data of the transmitted block, If it is determined that the data is the same, a copy signal is sent out indicating that the data is the same as the transmitted block data, and the actual sending of the data is omitted, making it possible to reduce the amount of data to be sent.
High-speed transmission is possible.

[Brief explanation of drawings]

FIG. 1a is a table diagram explaining the transmission form of a signal train according to an embodiment of the present invention, and FIG. 1b is a waveform diagram showing waveforms of a skip signal, a copy signal, and an image signal.
2a to 2c are waveform diagrams showing an example of transmission of one signal train in FIG. 1, FIG. 3 is a block diagram showing the overall configuration of a transmitter used in the method of the present invention, and FIG. FIG. 5 is a block diagram showing the configuration of the shift register in FIG. 4. FIG. 6 is a table showing the logical configuration of the determination circuit in FIG. 4. 7 is a more detailed circuit diagram of the transmission pattern storage circuit of FIG. 3, and FIG.
Figures a to d are signal waveform diagrams explaining the operation of the transmission pattern storage circuit, Figure 9 is a more detailed circuit diagram of the transfer bit counter circuit of Figure 3, and Figures 10 a to i.
11 is a signal waveform diagram explaining the operation of the transfer bit counter, FIG. 11 is a block diagram showing a more detailed configuration of the shift register in FIG. 3, and FIGS. 12 a to n explain the operation of the transmitter in FIG. 3. FIGS. 13a to 13c are explanatory diagrams showing the transmission of an image signal sequence in the transmitter of FIG. 3, and FIG. 14 is a table showing the transmission results according to the method of the present invention. 1...Reading device, 2...Line memory, 3
...Shift register, 4...Latch, 5...Transfer bit counter circuit, 6...Judgment circuit, 7...Transmission pattern storage circuit, 8...Clock generator,
9, 9'... Frequency divider, 10... Monostable multivibrator, 11... Shift register, 12... Transmission data control circuit, 13... Amplitude control circuit.

Claims (1)

[Scope of Claims] 1. In an image transmission method in which image information is divided into predetermined blocks and transmitted sequentially, information regarding the data content and data length of the transmitted blocks is stored, and data to be subsequently transmitted is determined based on this stored information. It is determined whether or not the data is the same as the data of the transmitted block, and if it is determined that they are the same, a copy signal indicating that the data is the same as the data of the transmitted block is sent, and the actual data is sent. An image transmission method characterized by omitting the.