JPH021435B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal processing circuit for a color television receiver, and in particular, in an ACC (Automatic Color Signal Control) amplification circuit for stabilizing a carrier color signal level, the ACC amplification function is impaired. The present invention relates to a color signal processing circuit that can perform a color killer operation by attenuating its gain without causing any damage.

The carrier color signal supplied to the color demodulation circuit of a color television receiver detects the burst signal included as a reference signal and keeps its amplitude constant.
The level is stabilized by ACC operation. In addition, when receiving black and white broadcasts or when the carrier color signal is absent or very weak, the level of the burst signal output from the ACC amplifier circuit is detected and the signal path is changed to prevent unnecessary signals and noise from being added to the color demodulation circuit. A color killer circuit is needed.
Conventionally, this color killer operation is performed by attenuating the signal level of the output signal of the ACC amplifier circuit in the path that transmits it to the color demodulation circuit. At that time, since there is no burst signal, the ACC amplifier circuit is controlled to the maximum gain, and the output of the ACC amplifier circuit is amplified with the maximum gain of the monochrome broadcast video signal or the noise carrier color signal frequency band component. It appears with a very large amplitude. This unnecessary excessive output signal during color killer operation makes the signal cut-off operation of the color killer circuit incomplete, causing a residual leak component at the input of the color demodulation circuit, and causing color noise on the TV screen. There were cases where this happened.

In order to eliminate such inconvenience, the present invention attenuates the gain of the ACC amplifier circuit so that the above-mentioned excessive output signal does not appear at the output of the ACC amplifier circuit when operating the color killer circuit, and also performs the ACC operation. The purpose of the present invention is to provide a color signal processing circuit that can selectively control the gain of the ACC amplifier circuit so that it has a normal amplification function only during the burst signal period required for the ACC amplifier circuit.

The present invention will be explained in detail below using the drawings.

FIG. 1 shows a conventional example of a color signal processing circuit. The carrier color signal that has passed through the band filter is input to input terminal 1.
The signal is supplied to the ACC amplifier circuit 2, where it is amplified and the level is kept constant. The output of the ACC amplifier circuit 2 is
The signal is supplied to the next stage amplifier circuit 3. The amplifier circuit 3 is
In periods other than the burst gate period, color control is performed according to the voltage at terminal 4, and during color killer operation, the AC gain of amplifier circuit 3 becomes zero and the carrier color signal at terminal 6 is erased. Further, the amplifier circuit 3 amplifies the input signal of the amplifier circuit 3 at a constant gain during the burst gate period using the burst gate pulse supplied from the terminal 5, and supplies the amplified signal to the output terminal 6. The signal output to the output terminal 6 is supplied to an ACC detection circuit 7, a color killer detection circuit 8, a color demodulation circuit 9, and an APC detection circuit 10. The ACC, color killer, and APC detection circuits 7, 8, and 10 are
Operate during the burst gate period, respectively, ACC
Generates control voltage, color killer signal, and APC control voltage.

However, the circuit system shown in FIG. 1 has the following drawbacks.

Now, if we consider the case when a black and white broadcast is received and a black and white signal is supplied to the input terminal 1, the ACC detection circuit 7 generates a control voltage depending on the amplitude of the burst signal.
It operates to maximize the gain of amplifier 2. Therefore, the signal components in the frequency band of the video signal and noise carrier color signal, which are added as a black and white signal via a band filter, are amplified at maximum gain, so an excessive input signal is supplied to the next stage amplifier circuit 3, and the amplifier circuit is overloaded. Due to saturation of the active elements, signal leakage in the bias circuit, etc., residual leakage of black and white signals appears at the output terminal 6, and this is applied to the color demodulation circuit 9, making the color erasing function incomplete.

FIG. 2 shows an embodiment of the present invention. Here 1
~10 correspond to each circuit in Fig. 1 and operate in the same way, except that the output of color killer detection circuit 8 is ACC.
It is added to the amplifier circuit 2', and in addition to the burst signal period, it also performs ACC during the chroma signal period during color killer operation.
A killer operation is performed by setting the gain of the amplifier circuit 2' to zero.

Therefore, the disadvantage that an excessive input is supplied to the next stage amplifier circuit 3 when a black and white signal occurs as shown in FIG. 1 is eliminated.

A more detailed explanation of the above operation is shown in Figures 3 and 4.
Do it with diagrams.

FIG. 3 shows a conventional example of a color signal amplification circuit.
This corresponds to parts 1 to 8 in FIG.

In FIG. 3, an input carrier color signal is applied to input terminal 1. This input terminal 1 is connected to a resistor 15 and the base of a transistor 11. The emitter of transistor 11 is grounded through resistor 13, and the collector is connected to the commonly connected emitters of transistors 17 and 18. The emitter of transistor 37 provides the same bias through resistor 15 to the base of transistor 11 and through resistor 16 to the base of transistor 12, and resistor 3
It is grounded through 8. The emitter of transistor 12 is resistor 1 having the same resistance value as resistor 13.
4 and the collector is connected to transistor 1.
It is connected to the commonly connected emitters 9 and 20.
The collectors of transistors 17 and 19 are connected to a power supply, and the collectors of transistors 18 and 20 are connected to a load resistor 21 whose one end is connected to the power supply and to the base of transistor 22. transistor 1
The bases of 7 and 20 are commonly connected and serve as an ACC control terminal. On the other hand, the bases of transistors 18 and 19 are also commonly connected to the power supply voltage V _cc and the voltage source 41.
A bias voltage created by resistors 39 and 40 is applied.

The connections described above result in transistors 18 and 1
A predetermined bias voltage is supplied to the common bases of transistors 17 and 20, and a control voltage is supplied from the ACC detection circuit 7 to the common bases of transistors 17 and 20.
The current distribution ratio of is controlled. Therefore, the AC current based on the input signal supplied to the input terminal 1 flows through the load resistor 21 according to the distribution ratio. On the other hand, regarding DC current and voltage, transistor 1
Since the collectors of transistors 8 and 20 are commonly connected and transistors 11 and 12 are biased with the same voltage, the voltage between transistors 17 and 18 and between transistors 19 and 20 depends on the control voltage from ACC detection circuit 7.
Even if the current distribution ratio between them changes, the DC current flowing through the load resistor 21 is kept constant and the output DC potential does not change. In other words, since the DC potential hardly changes, the AC gain for the input signal is
An output signal controlled by a control voltage from is obtained.

The voltage appearing at this resistor 21 is supplied to the base of an emitter follower transistor 22, and after being level-shifted from the emitter by a diode 23, it is supplied to a resistor 24 whose one end is grounded and to the base of a transistor 25.

25 to 36 correspond to the amplifier circuit 3 in FIG.
The emitter of transistor 25 is diode 2
7. It is grounded through a resistor 28 and connected to a resistor 29. The other end of the resistor 29 is grounded through a capacitor 31 and connected to the bases of transistors 26 and 37. The capacitor 31 feeds the DC voltage component generated across the resistor 21 back to the input transistor, and the transistor 25
The base DC potential of is kept almost constant.

The emitter of the transistor 26 is grounded through a resistor 30 having the same resistance value as the resistor 28. Here, the DC voltages applied to the resistors 28 and 30 are both lower than the potential across the capacitor 31 by the diode forward voltage, so the transistors 25 and 26
The DC collector currents of are almost equal. The collector of transistor 25 is connected to transistors 32 and 33.
The collector of transistor 26 is connected to the emitter of transistors 34 and 35, respectively, and the collectors of transistors 32 and 34 are connected to the power supply.
_Vcc , the collectors of the transistors 33, 35 are connected to a common load resistor 36, one end of which is connected to the power supply, and to the output terminal 6. The operation of these transistors 32 to 35 is as follows:
~20, approximately equal to the operation of transistors 32,
The gain of the input signal applied to the base of the transistor 25 is controlled according to the potential difference between a terminal 43 connected to the base of the transistor 35 and a terminal 44 connected to the transistors 33 and 34. However, the AC resistance connected to the emitter of the transistor 25 at this time is a resistance 28 and a resistance 29 connected in parallel.

Here, a bias voltage is applied to the terminal 43 from a bias source (not shown). On the other hand, different control voltages are applied to the terminal 44 during the burst gate period and during other periods. That is, during the burst gate period, a control voltage that is sufficiently higher than the bias voltage applied to the terminal 43 is applied to the terminal 44 in order to amplify the input burst signal with a constant gain. As a result, transistors 32 and 35 are turned off, transistors 33 and 34 are turned on, and an amplification operation is performed with a large constant gain.
Next, outside the burst gate period, a sufficiently low voltage is applied to terminal 43 so that the gain is zero during killer operation, and when the killer is not operating, the externally set color control (color saturation control) voltage is applied. A corresponding voltage is applied to perform color control operation.

A part of the output from terminal 6 is detected by the ACC detection circuit during the burst gate period to create an ACC control current, which is passed through resistor 42 and applied to the bases of transistors 17 and 20.
Gives ACC control voltage. In this case, when a large amount of current flows through the resistor 42, the gain decreases.

The disadvantages of the conventional example will be explained below with reference to FIG.

Consider a case where a black and white signal is input to input terminal 1.
At this time, since there is no burst signal, the ACC amplifier circuit has maximum gain during killer operation. If noise is supplied to the input terminal 1 in this state, or furthermore, if the black and white signal components include a signal with a frequency component close to the burst frequency, these signals are amplified at the maximum gain and sent to the transistor 25. join the base of For such an excessive signal, the smoothing circuit consisting of the resistor 29 and capacitor 31 cannot sufficiently attenuate and smooth the signal to the required level, so a level corresponding to the division ratio is applied to the connection point of the resistor 29 and capacitor 31. signal remains. This residual signal component is added as an alternating current signal to the base of the transistor 26, which should normally flow a direct current, and during killer operation, the collector current of the transistor 26 is supplied to the load resistor 36 through the transistor 35, and the amplified residual signal is sent to the output terminal. It appears as a component.

Furthermore, the excessive current that charges and discharges the capacitor 31 flows through the resistor 29 to the transistors 25 and 32, but if there is impedance at the bias terminal 43, a signal is generated at the terminal 43 due to the base current of the transistor 32, and the differential transistor 3
When a signal level exceeding the reverse bias of 2 and 33 and 35 and 34 is reached, a differentially amplified residual signal component appears in the load resistor 36.

As described above, there is a drawback that a residual signal component is generated at the output terminal 6 even though the color killer is in the operating state when a black and white signal is used.

FIG. 4 shows one embodiment of the present invention, and shows blocks 2 and 3 in FIG. 2 as a circuit diagram.

Here, 7, 11 to 43 are the same as in FIG. Terminal 44' carries a voltage similar to terminal 44 but not affected by killer operation. That is, a voltage that provides the maximum gain is applied during the burst gate period, and a voltage that corresponds to color control is applied during the other periods.

A signal detected by the killer is applied to the terminal 48, and the function is to put the current source 45 into an operating state when the killer is activated, and to stop the current from the current source 45 when the killer is not activated. Current source 45 is connected to the emitters of transistors 46 and 47, the collector of transistor 46 is grounded, and the collector of transistor 47 is connected to
It is connected to the ACC control current output, the common base of transistors 17 and 20, and the common connection point of resistor 42. Further, a constant potential is applied to the base of the transistor 47, that is, the terminal 50, and a voltage that is sufficiently lower than the terminal 50 potential during the burst gate period is applied to the base of the transistor 46, that is, the terminal 49. A high potential is applied to the In this way, the transistors 46 and 47 perform a switch operation, and the resistor 4
A current from the current source 45 is applied to the current source 45. For this reason, the gain control circuit composed of transistors 17 to 20, during killer operation and other than the burst gate period, narrows down the gain by the potential generated by the current of the current source 45 and the resistor 42, and selects this value. By doing so, the gain can be made zero.

Therefore, as explained in FIG. 3, when receiving a black and white signal, the transistor 2
The phenomenon that an excessive signal is added to the base of 5 does not occur, and the above-mentioned drawbacks are eliminated.

Furthermore, since no current flows through the transistor 47 during the killer non-operation period and during the burst gate period, the transistor 47
There is no effect due to the addition of 5 to 50 circuits.

FIG. 5 shows a block diagram of another embodiment of the invention.

The only difference from the embodiment shown in FIG. 2 is that the amplifier circuit 3 is caused to perform a killer operation in the same manner as in FIG. This is particularly effective when the gain of the amplifier circuit 3 is large and it is necessary to amplify noise components and prevent noise signals from appearing in the output during killer operation.
In the example shown in FIG. 5, the killer operation in the ACC amplifier circuit 1 does not have to be performed completely, but it is sufficient to reduce the gain to the extent that the signal amplitude can be suppressed to a level that does not affect other circuits when a black and white signal is used.

Also, in Figures 3 to 5, the gain of the ACC amplifier circuit 1 is reduced during the killer operation and outside the burst gate period, but it is also possible to reduce the gain during the killer operation and outside the blanking period. good.
This is because no image appears on the television screen during the blanking period, so even if a color signal component is added to the color demodulation circuit 9, it will not affect the operation.

Furthermore, although the above description has been made using the examples of FIGS. 2 and 4 as the color signal amplification circuit, it is clear that the circuit configuration is not limited to this.

As an example, the amplifier circuit 3 that performs color control shown in FIG. 2, and its control terminal 4 connected to the output terminal 6
Even if the circuit configuration is between the demodulation circuit 9 and the demodulation circuit 9, the effects of the present invention do not change at all.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional example, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a circuit diagram of a conventional example, FIG. 4 is a circuit diagram of an embodiment of the present invention, and FIG. The figure is a block diagram of another embodiment of the invention. 1... Color signal input terminal, 2, 2'... ACC amplification circuit, 3... Amplification circuit, 4... Color control terminal, 5... Bust gate pulse input terminal, 6
...Color signal output terminal, 7...ACC detection circuit, 8
...Color killer detection circuit, 9...Color demodulation circuit,
10...APC detection circuit.

Claims (1)

[Claims] 1. In a color signal processing circuit for a carrier color signal including a burst signal and a chroma signal, the burst signal is detected and a burst signal amplitude detection signal is generated.
an ACC detection circuit; a color killer detection circuit that detects the burst signal and generates a color killer signal; and a color killer detection circuit that receives the carrier color signal and controls a gain for the carrier color signal in response to the burst signal amplitude detection signal and outputs the signal. comprising an ACC amplifier circuit, an amplifier that amplifies the output of the ACC amplifier circuit and supplies it to a color demodulation circuit, and means for supplying the color killer signal to the ACC amplifier circuit only during the chroma signal period excluding a burst period, The color signal processing circuit is characterized in that the ACC amplifier circuit performs a color killer operation by reducing the signal gain during the chroma signal period excluding the burst signal period in response to the color killer signal.