JPH0214730B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to an information processing device that is expected to repeatedly process the same loop through a program.

FIG. 1 shows the configuration of a conventional general information processing device. In the figure, reference numeral 1 denotes a control circuit, and as is well known, the overall operation is controlled by control signals sent from this control circuit to each part. 2 is an instruction register that stores instructions to be executed from now on; 3 is a storage device that stores instructions and data to be executed; 4 is a program counter PC that stores the address of the next instruction to be executed; 5 is a stack that temporarily saves the address information of PC4. Further, 6 is an arithmetic circuit that performs arithmetic processing on data. 7 is a general-purpose register file for recording temporary data.

Next, the operation when performing repetitive processing using such an information processing apparatus will be explained using a flowchart of a general repetitive processing shown in FIG. Here, the processes X ₁ to X _o are tasks that must be executed repeatedly at least twice, and the loop control for the repeated processes uses general-purpose registers to set the initial setting A before entering the loop, and the loop within the loop. Control register update Y and loop end determination Z are performed.

Therefore, if the register Y8 in the general-purpose register file 7 is used as a loop control register, the information processing will be executed as follows. First, instructions are read from the storage device 3 to the instruction register 2 in the order indicated by the PC 4, and based on the instructions, the control circuit 1 sends control signals to each component. Initial setting A is performed by setting a certain value corresponding to the number of repetitions in register Y8. Next, when the processes X ₁ to X _o are executed once using the general-purpose register file 7, the arithmetic circuit 6, etc., the contents of the register Y8 are subsequently updated through the arithmetic circuit 6. Thereafter, whether or not to end the loop is determined by comparing in the arithmetic circuit 6 whether the register Y8 has reached a predetermined final value. If it does not end, transfer the data retrieved from the storage device 3 to the PC 4 and start the loop, that is, process X ₁
Return to If the process is finished, move on to the next process.

In this way, conventional information processing devices use the common control circuit 1 and arithmetic circuit 6 for both the processes X ₁ to _{X o} that are to be repeatedly executed, the register update Y for loop control, and the loop termination determination Z. It is not possible to run them in parallel at the same time. Therefore, the loop becomes longer because register update Y and loop end judgment Z are performed after processing X ₁ to _{X o} in the loop, and an extra amount of time is added by the number of repetitions x {register update Y + time for end judgment Z and branch}. The drawback was that it took a lot of time. Especially at the microprogram level, when performing multiplication/division, block transfer, search, etc. in software, repetitive processing is required.
The processing time for register update Y and end determination Z for X ₁ to _{X o} cannot be ignored, and has been an obstacle to improving the speed of the information processing apparatus.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an information processing device that can improve information processing speed, particularly the repeat processing speed of the same loop.

In order to achieve such an objective, the present invention
A repeat flag is provided to instruct repeat processing, a specific field is provided in the instruction register to be activated at the time of the last processing instruction of the repeat processing loop, and the contents of the loop control register are updated by activation of the specific field. A loop end determination control circuit is provided which compares the updated contents of the loop control register with the final value on condition that the update circuit and repetition flag are activated, and controls the stack and program counter according to the result. The present invention will be explained in detail below using Examples.

FIG. 3 is a block diagram showing one embodiment of the present invention. In the figure, 1a is a control circuit, 2a is an instruction register, 3a is a storage device, and others 4-
Reference numeral 8 indicates a portion equivalent to that indicated by the same symbol shown in FIG. Furthermore, as a feature of the present invention, 20 is an update circuit for the loop control register Y8 in the general-purpose register file 7, and 21 is a comparison circuit that has a predetermined standard for determining whether or not the general-purpose register Y8 has reached the target closing value. Compare with the value and judge. The functions of the update circuit 20 and the comparison circuit 21 are both realized without using the arithmetic circuit 6. 2
2 is a repeat flag, which indicates that the information processing device is currently performing repeat processing. Reference numeral 23 denotes a repetition control circuit, which outputs a control signal CN2 when the control signal CN1 from the control circuit and the outputs of the comparator circuit 21 and the repetition flag 22 meet the conditions for ending the loop.
is sent to transfer address data from stack 5 to PC 4.

FIG. 4a shows the instruction register 2 used in this embodiment.
The command field of a is shown. As is clear from a comparison with the instruction field of the instruction register 2 in the conventional example shown in FIG. 1 of FIG.・Register Y)
A field 40 named .

In the above configuration, when substantially the same process as shown in the flowchart of FIG. 2 is executed, the procedure is expressed as in the flowchart shown in FIG. In the figure, initial settings B include initial settings for components newly added in the present embodiment shown in FIG. Processing X ₁ to _{X o} is the same as that in FIG. 2, but processing X _o updates loop control register Y Y _a
and loop end determination Z _a is performed simultaneously. That is, the processing indicated by the broken line arrow in the figure is performed based on the UPY field 40 of the instruction register 2a. Note that the dashed dotted line in the figure indicates that the block is based on one instruction.

Next, the operation of this apparatus will be explained in detail according to this flowchart. First, in initial setting B, after initializing each component for normal processing X ₁ to X _o , the repetition flag 22 is activated, the updated value of the update circuit 20 and the final value (reference value) of the comparison circuit 21 are activated. and initialize the loop control register Y8. For example, the initial value of the loop control register Y8 is set to a constant value corresponding to the number of repetitions, the final value of the comparator circuit 21 is all 0, the update value of the update circuit 20 is set to -1, and the loop is executed once. The contents of the loop control register Y8 may be decremented by 1 each time it is executed, or the initial value of the reverse loop control register Y8 may be set to 0, for example, and the final value of the comparison circuit 21 may be set to a constant value corresponding to the number of repetitions. value and update circuit 2
The update value of 0 may be set to +1, and the contents of the loop control register Y8 may be incremented by 1 for each loop. Of course, one of the final values of loop control register Y8 and comparison circuit 21 does not have to be 0, and the updated value of update circuit 20 does not have to be ±1, but may be any other constant value. Finally, the initial address data of process _X1 is saved in the stack 5, the stack pointer in the control circuit 1a is updated, and the initial setting B is completed. Then iterate
Execute X ₁ ~ X _o . That is, the control circuit 1a is
Similar to the conventional device, each processing step is sequentially executed using the register file 7, arithmetic circuit 6, etc. according to instructions read from the storage device 3a to the instruction register 2a. The UPY field 40 of the instruction register 2a shown in FIG. 4a is inactive until processing X _o-1 before the final processing of this loop.
The above field is activated for the first time in the final process _Xo . Then, in parallel with the original processing using the register file 7, arithmetic circuit 6, _etc.
The control circuit 1a updates the update circuit 2 using the control signal CN1.
0, the comparison circuit 21 and the repetition control circuit 23 are activated, and register update Y _a and loop end determination Z _a are performed. That is, the repetition control circuit 23 sends out a control signal CN2 to indicate whether to return to the beginning or end the loop, based on the comparison result between the updated contents of the loop control register Y8 and a predetermined end value, that is, the output of the comparison circuit 21. If the final value has been reached, the control signal CN2 returns the stack pointer in the control circuit 1a, and the PC4 proceeds to the next step. If the closing price has not been reached, the control signal CN
In step 2, the address data at the beginning of process _X1 , which had been saved in the stack 5, is transferred to the PC 4, and the program execution returns to the beginning of the loop. Here, even if address data is read from the stack 5, the stack pointer of the control circuit 1a is not changed, so there is no need to set it again. Therefore, the arithmetic instructions, branch instructions, etc. that were conventionally performed in the register update Y and end determination Z of FIG. 2 are no longer necessary, and the instruction execution time and the number of program steps are shortened accordingly. Also, the length of the repeating loop is
Since the UPY field 40 is only activated after the initial setting B, its length is not particularly limited. However, in order to perform the loop end determination Z _a when the UPY field 40 is activated, it is necessary that the repetition flag 22 be activated. If initial setting B
If the repetition flag 22 is not activated in
Only the update circuit 20 operates, and no loop termination determination is performed. In other words, by providing the repeat flag 22, two types of operations can be assigned to the UPY field 40: simply updating the register Y8 in parallel with other instructions, and executing three operations: update, comparison, and branch. is possible.

In addition, although the above-mentioned embodiment describes the case where it is used at the microprogram level of an information processing device, it is possible to configure it so that it can also be used in a higher level program.
This is because the action is essentially the same as the DO-UNTIL statement in a high-level language.

Further, in the above-described embodiment, only the case where a single loop is used has been described, but if a dedicated stack or the like is provided for the repetition flag 22, it is possible to cope with the case where repeated processing of multiple loops is performed.

As described above, according to the present invention, a few components, namely, a repetition flag, an update circuit, and a loop end determination control circuit are added to a conventional information device, and an instruction register is activated by the last processing instruction of a repetition processing loop. By providing a specific field to be converted into data, it has become possible to speed up repetitive processing that is widely used in general information processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of an information processing device, FIG. 2 is a flowchart showing an example of a repetitive processing program, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIGS. 4 a and b 5 is a diagram showing an example of the configuration of an instruction field given to an instruction register in comparison with a conventional example, and FIG. 5 is a flowchart showing an example of a repeat processing program. 1a...Control circuit, 2a...Instruction register, 3
a...Storage device, 4...Program counter PC,
5...Stack, 7...General-purpose register file,
8... Loop control register Y, 20... Update circuit, 21... Comparison circuit forming a loop end determination control circuit, 22... Repetition flag, 23... Repetition control circuit forming a loop end determination control circuit, 40 ...Specific field of instruction register 2a.

Claims (1)

[Scope of Claims] 1. A program counter that specifies the address of an instruction to be executed, a stack that temporarily holds the contents of this program counter, a general-purpose register that stores data to be processed, and a storage device that stores the program. an instruction register for storing an instruction read from the storage device according to an address specified by the program counter; a loop control register for storing the number of repetitions; and updating the contents of the loop control register by a predetermined value. and a comparison circuit that compares the contents of the loop control register with a predetermined final value, a part of the instruction register is a dedicated field for loop control register update control, and the instruction register is It has a repetition flag that independently indicates a state of repetition processing, activates said repetition flag by an initialization instruction of repetition processing, transfers the address of the first instruction of repetition processing to said stack, and when said repetition flag is in an inactivated state. When an instruction for activating the dedicated field is fetched into the instruction register, the update circuit is used to update the memory of the loop control register using the dedicated field, and the activation state of the repeat flag is updated. In,
Along with updating the memory of the loop control register,
If the output of the comparison circuit indicates a mismatch state, the repetitive processing is continued by transferring the address of the first instruction of the repetitive processing that has been transferred to the stack to the program counter;
If the output of the comparison circuit indicates a match state, the repeat processing is terminated by erasing the address of the first instruction transferred to the stack and inactivating the repeat flag. Information processing equipment.