JPH0215956B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory that reduces instantaneous current when driving its output capacitance.

In general, data processing speed is one of the important factors in microcomputer systems, although it depends on the application. For this reason, there has recently been a demand for even faster operation of CPUs (Central Processing Units) or memories. By the way, in a microcomputer system, the output of a semiconductor memory is connected to a data bus. The capacity existing on this data bus is extremely large, and in semiconductor memory, the time from address input to data output is determined when a capacity of about 150 PF is connected to the output of the semiconductor memory. This time is determined to be smaller and smaller as semiconductor memories operate at higher speeds. At present, the mainstream of microcomputers is an 8-bit configuration, so here we will temporarily consider a semiconductor memory with an 8-bit output. Now, the 8-bit output of the memory is changing from “0” to “1” at the same time.
Suppose that it becomes Suppose that the output rises from 0V to 3V at a rate of 20 nanoseconds. In this case, since each bit has a capacitance of 150 pF, it is necessary to drive a capacitance of 150 pF x 8 = 1200 pF for 8 bits. The required current at this time is shown by the following equation.

=CV/t=8×150× ^10-12 ×3/20× ^10-9 =180m
A: In other words, at this time, a current of 180mA flows instantaneously. However, normally the operating current of semiconductor memory is
It is 100-150mA. For this reason, the above 180mA
If excessive current flows rapidly, noise will be introduced into the power supply and ground lines, impairing the stable operation of memory, and there is also the risk that the contents of RAM, etc., may be reversed due to noise. It is also necessary to consider the influence of this memory on peripheral integrated circuits, and when such a memory is used, extra consideration is required in the system design of the microcomputer.

Next, the above-mentioned required current will be explained with reference to a partial configuration diagram of the semiconductor memory shown in FIG. 1 ₁ to 1 _o are memory cell arrays whose two groups of row lines are connected to a common row decoder 3, and 4 ₁ to 4 _o are column selection circuits connected to five groups of column lines of the memory cell arrays 1 ₁ to 1 _o . , 6 are the column selection circuits 4 ₁ to 4 _o
Column decoders ₇₁ to _7o are connected in common to the column selection circuits 41 to 4o, sense amplifiers 81 to 8o are respectively connected to the column selection circuits ₄₁ to _4o , and ₈₁ to _8o are connected to the sense amplifiers ₇₁ to _7o , respectively. Output buffers are connected correspondingly, and the output terminals of the buffers 8 ₁ to 8 _o are respectively connected to corresponding external output terminals.

The memory cell arrays ₁₁ to _1o each have a memory cell at each intersection of a row line and a column line, and one row line is driven and selected by the row decoder 3 in accordance with a row address input, and a column address input. Column selection circuits 4 ₁ to 4 _o driven by column decoder 6 according to
Accordingly, memory cells present at each intersection with one column line selected for each memory cell array are selected. As a result, each memory cell array 1 ₁ to 1 _o
Data is read out one bit at a time, and 8-bit data is derived from the external output terminal.

Incidentally, in a semiconductor memory, in order to minimize the chip size, the row lines are wired with polysilicon, and the column lines and the output lines of the column decoder 6 are wired with aluminum. The above polysilicon is usually 30 to 50
Since it has a resistance of Ωμ ² , there is a time delay in the voltage on the row line located far from the row decoder 3 compared to the voltage on the row line located close to the row decoder 3. Therefore, when a memory cell in each memory cell array is newly selected due to a change in the row address, the memory cell closer to the row decoder is selected faster in time. A time difference occurs depending on the position to each selected memory cell. Therefore, the 8-bit output from the output buffer does not change at the same time, and the aforementioned 180 mA current is not required.

However, when only the column address changes, the output line of the column decoder 6 is wired with aluminum and has a resistance of approximately 0Ω due to the necessity of its pattern layout, so each column selection circuit is connected to each memory cell array. Each column line is selected almost simultaneously, and 8-bit data from each selected memory cell is simultaneously output from the output buffer. At this time, an extra current of 180 mA flows instantaneously, causing malfunction. That is, when the column address changes and data is output, noise is most likely to be applied to the power supply and ground lines.

The present invention has been made in order to eliminate the above-mentioned drawbacks, and even when the output of only the column decoder changes, the difference in the timing at which each output bit data of a plurality of memory cell arrays is derived to a plurality of corresponding output buffer circuits is made. By providing a timing difference means for differentiating the drive timing of the column selection circuit or sense amplifier to increase the power output, it is possible to prevent a large output current from flowing instantaneously, and to suppress the induction of noise into the power supply and ground lines. ,
The present invention provides a semiconductor memory that provides stable memory operation.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. The memory shown in FIG. 2 includes each column selection circuit 4 ₁ in the memory described above with reference to FIG.
A depletion type MOS transistor 11 is connected to the column decoder output lines between the 4 _o 's and the column select circuits as a means for differentiating the driving times of the column selection circuits, and the gate of this transistor 11 is connected to the power supply _Vc .

According to such a memory, a column decoder (first
Even when the output changes as shown in Figure 6), the voltage on the output line of the column decoder drives each column selection circuit at a sequentially delayed timing for each column selection circuit, so one column line of each memory cell array is selected at the same time. Never.

Therefore, the timings at which the output bit data of each memory cell array specified by the same address are led out to the corresponding output buffer circuits are different, so that the memory outputs do not change simultaneously, and the large instantaneous current mentioned above is also reduced. It can be suppressed.

Note that even if the drive time of each column selection circuit is made different as described above, this time difference accounts for a small proportion of the memory system's operating time, and the column decoder output line has a smaller load capacitance than the row line. Since the wiring is usually made of aluminum, the time it takes for the address input to change and the column decoder output line to change is shorter than the time for the address input to change and the row line to change, so when reading memory data, There are no problems that slow down the speed.

FIG. 3 shows a memory according to another embodiment of the invention.
This memory has a first column decoder 31, a second column decoder 32, and this first column decoder 31
The second column decoder 32 drives the column selection circuits 4 ₁ to 4 _o , and the second column decoder 32 drives the two sense amplifiers 33 ₁ , 34 ₁ , 3
3 ₂ , 34 ₂ , . . . and connect one output buffer 35 ₁ to 35 _o to each pair of sense amplifiers, and connect the column decoder output lines between each of the two sense amplifiers. The depletion type transistor 11 is connected as described above. Even in such a memory, the driving time of each group of sense amplifiers differs depending on the output of the second column decoder 32, so the outputs of the output buffers 35 ₁ to 35 _o change simultaneously when the column address changes. Never. Of course, at the same time, it is more desirable to differentiate the driving times of the column selection circuits as described above. Furthermore, when switching between two sense amplifiers, the second column decoder 32 may output address data as is, that is, address data A and its inverted data A. That is, the second column decoder 32 may be an address buffer circuit. Also, the third
In the figure, pulses may be generated in synchronization with changes in column addresses, and the second decoder 32 and sense amplifier may be used in dynamic operation.

FIGS. 4a to 4e show various examples of replacement of the transistor 11 in FIGS. 2 and 3 above. Figures a and b show that the gate of the transistor 11 is connected to the column decoder side of the column decoder output line or to the opposite side thereof. Figures c and d in the same figure are a combination of the above a and b, and figure e is one in which an inverter 41 is used.

As described above, according to the present invention, when the output line of the column decoder drives the column selection circuit or sense amplifier corresponding to each output buffer, the time difference between the outputs appearing to the output buffer circuit corresponding to each memory cell array is reduced. Since a timing difference means is provided, the above outputs will not change at the same time. Therefore, the instantaneous current when driving the capacitance of the output terminal is reduced, and it is possible to provide a semiconductor memory that enables stable operation of the system when applied to a microcomputer system.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an example of a conventional semiconductor memory, FIG. 2 is a configuration explanatory diagram showing main parts of an embodiment of a semiconductor memory according to the present invention, and FIG. 3 is a configuration explanatory diagram showing another embodiment of the present invention. A configuration explanatory diagram showing the
FIG. 4 is a circuit diagram showing an example of replacing the transistor 11 in FIGS. 1 ₁ - 1 _o ... memory cell array, 3 ... row decoder, 4 ₁ - 4 _o ... column selection circuit, 6 ... column decoder, 7 ₁ - 7 _o ... sense amplifier.

Claims (1)

[Scope of Claims] 1. A plurality of output buffer circuits provided corresponding to multiple bit outputs and outputting data specified by the same address to the outside; A plurality of memory cell arrays from which respective output bit data are derived from a plurality of output buffer circuits, a row decoder and a column decoder that select memory cells of each of the plurality of memory cell arrays, and each output bit data of the plurality of memory cell arrays. 2. A semiconductor memory comprising timing difference means for differentiating drive timings of column selection circuits or sense amplifiers in order to differentiate the timings at which the output buffer circuits output the sense amplifiers to the respective plurality of corresponding output buffer circuits. 2. The semiconductor memory according to claim 1, wherein the timing difference generating means comprises a delay circuit inserted between the column selection circuits or between the sense amplifiers.