JPH0217939B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to semiconductor devices, and particularly to self-extinguishing switching semiconductor devices such as transistors and gate turn-off thyristors.

In this type of semiconductor device, a turn-off operation is performed by extracting carriers in a semiconductor substrate from a gate electrode (base electrode in a transistor).
Therefore, gate turn-off thyristor (hereinafter referred to as
This is explained in detail using GTO (abbreviated as GTO) as an example. FIG. 1 is a partial cross-sectional view of a semiconductor substrate 1 constituting a GTO, and shows four adjacent semiconductor layers having sequentially different conductivity types: p _E layer 2, n _B layer 3, p _B layer 4, n _E The pn junction J formed by the _pB layer 4 and the _nE layer 5 has a planar junction structure exposed on the upper main surface of the semiconductor substrate 1. Usually the _nE layer 5 is divided into strips or
It has a comb-like shape. In Figure 1, the strip-shaped n _E layer 5
is shown cut in the width direction. The _pE layer 2 on the lower main surface of the semiconductor substrate 1 has an anode electrode 6, the _pB layer 4 on the upper main surface has a gate electrode 7 surrounding the _nE layer 5, and the _nE layer 5 has a cathode electrode. 8 are connected to each other with low resistance. A surface stabilizing film provided on the upper main surface other than the gate and cathode electrodes 7 and 8 is omitted in FIG.

At turn-off, a reverse bias voltage is applied to the pn junction J, and the current i _A flowing from the anode electrode 6 toward the cathode electrode 8 is drawn out from the gate electrode 7 as shown by the dotted line. In this case, if the lateral resistance R _PB of the p _B layer 4 directly under the n _E layer 5 is large, the voltage drop i _A ×R _PB in the p _B layer 4 will increase, and the current will concentrate at the center of the n _E layer 5 at turn-off. p-n junction J
becomes a forward bias state, and the GTO turns on in this part, leading to turn-off failure. In order to avoid turn-off failure, the impurity concentration of the _pB layer 4 is increased to reduce the lateral resistance _RPB . In particular, the p _B layer 4 is often created by impurity diffusion, so the surface impurity concentration of the p _B layer 4 is approximately 5×
It is quite high at 10 ¹⁷ to 2×10 ¹⁸ atoms/cc. As a result, the pn junction J has a low breakdown voltage, and the gate breakdown voltage of commercially available GTOs is about 10 to 20V. With such a gate breakdown voltage, it is difficult to quickly turn off a large current. One method of increasing the gate breakdown voltage is to form the p _B layer 4 or the n _E layer 5 using epitaxial technology, but this method results in high manufacturing costs.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a self-extinguishing switching semiconductor device that has a high gate breakdown voltage at a low manufacturing cost.

[Summary of the invention]

A feature of the present invention that achieves the above object is that a p _B layer is formed using a diffusion mask, and an n _E layer and a p _B layer are formed in a lateral diffusion region with a low impurity concentration under the diffusion mask. The end of the pn junction is formed and exposed on the main surface of the semiconductor body.

[Embodiments of the invention]

Hereinafter, the present invention will be explained according to an embodiment shown in the drawings.

Similar to FIG. 1, FIG. 2 shows a part of the semiconductor substrate 11 of the GTO. The semiconductor substrate 11 has a _pE layer 1
2, having an n _B layer 13, a p _B layer 14 and an n _E layer 15,
An anode electrode 16 is in low resistance contact with the _pE layer 12, a gate electrode 17 is in contact with the _pB layer 14, and a cathode electrode 18 is in low resistance contact with the _nE layer 15. This semiconductor substrate 11 is manufactured as follows. That is, the semiconductor substrate 1 with n-type conductivity
1 is prepared, no diffusion mask is provided on the lower main surface, and a diffusion mask (not shown) having a width indicated by the symbol L in the figure is provided on the upper main surface. Next, p-type impurities are diffused from both the upper and lower main surfaces. When boron is used as the p-type impurity, a silicon oxide film is used as a diffusion mask. The p _E layer 12 is formed flat, and the p _B layer 14
As shown in the figure, impurities are diffused in the lateral direction from both sides of the diffusion mask and are continuous. The area indicated by the dotted line in the figure is a continuous portion due to lateral diffusion. Next, in the p _B layer portion formed by lateral diffusion, an n-type impurity is diffused so that the end of the pn junction J, that is, the part that connects the main surface with the part parallel to the main surface of the pn junction, is located. Then, _{an E} layer 15 is formed. Finally, a metal serving as each electrode 16 to 18 is provided.

In the GTO having the above configuration, the lateral resistance _RPB of the _pB layer 14 directly below the _nE layer 15 is as low as that shown in FIG. Furthermore, it is exposed on the upper main surface.
Near the pn junction, the impurity concentration of the _pB layer is low due to lateral diffusion, so the withstand voltage of the pn junction can be increased.
Figure 3 shows an example of the relationship between the lateral distance y from the edge of the diffusion mask to the inside of the diffusion mask (see Figure 2) and the surface impurity concentration. ×10 ¹⁸ atoms/
cc, the diffusion depth of P-type impurity X _J (see Figure 2) is
This is the case of 60 μm. When the exposed end of the pn junction J is set at a position 25 μm inside (y=25 μm in FIG. 3) from the diffusion mask end (y=0 in FIG. 3), the surface impurity concentration of the p _B layer 14 here is 1×
10 ¹⁶ atoms/cc. On the other hand, Figure 4 shows the relationship between the impurity concentration and the breakdown voltage _VB , that is, the breakdown voltage, in a stepped junction, which is 1×10 ¹⁶ atoms/
In the case of cc, the withstand voltage is approximately 60V. In the GTO shown in Figure 1, where the diffusion conditions for the p _B layer are the same as those in Figure 3, the impurity concentration of the p _B layer at the pn junction J exposed on the upper main surface is 2 x 10 ¹⁸ atoms/cc. ,this
The withstand voltage of a pn junction is approximately 3V (see Figure 3).

5 and 6 show other embodiments of the present invention, FIG. 5 is a _partial cross-sectional view, and _FIG. layer 1
FIG. 5 is a plan view showing the positional relationship of 5 (point portions). This example shows that if the width of the _nE layer 15 is narrow, the entire _nE layer 15 can be provided within the lateral diffusion region of the _pB layer 14. Since the entire _nE layer 15 is in the low impurity concentration region of the _pB layer, the withstand voltage of the _pn junction J can be made higher than in the embodiment shown in FIG. 2 even if the nE layer 15 is made thinner.

In the embodiments shown in Figures 5 and 6, L = 0μm, 50μ
m and 60 μm, boron is diffused at a surface impurity concentration of 5 × 10 ¹⁷ atoms/cc until X _J = 60 μm, and n
When the width of the emitter layer W _oE = 10 μm and the diffusion depth is 11 μm, the gate breakdown voltage is 20 V, 33 V, and
It was 38V. As described above, in the present invention (when L=50 μm and 60 μm), the gate breakdown voltage can be increased by 1.5 to 2 times or more compared to the conventional GTO (when L=0 μm). As a result, in the present invention, the turn-off gate power supply voltage _EG can be increased, so the turn-off time can be shortened. As an example, pressure resistance
In a 1200VGTO (chip size 7.5mm x 2mm), the present invention (when L = 50μm) had an anode current of 10A, E _G = -30V and a turn-off time of 1μs, whereas the conventional GTO (when L = 0μm) had a turn-off time of 1μs. ), the anode current was 10 A, E _G = -17 V, and the turn-off time was 2 μS.

Above, we have explained the case where the present invention is applied to a GTO, but as in the case of a GTO, a reverse voltage is applied between the emitter (corresponding to the GTO cathode) and the base (corresponding to the GTO gate) to shorten the turn-off time. The present invention can also be applied to such a transistor.

In both embodiments, the p _B layer and the n _E layer are not created using a special diffusion technique, so the manufacturing cost does not increase.

〔Effect of the invention〕

As described above, according to the present invention, a self-extinguishing switching semiconductor device with increased gate breakdown voltage can be obtained without increasing manufacturing costs.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view of the semiconductor substrate of a conventional GTO, FIG. 2 is a partial cross-sectional view of the semiconductor substrate of a GTO according to an embodiment of the present invention, and FIG. 3 is a diagram showing the lateral distance in lateral diffusion. Figure 4 is a diagram showing the relationship between impurity concentration and breakdown voltage in a stepped junction. Figures 5 and 6 are parts of a semiconductor substrate of a GTO showing other embodiments of the present invention. FIG. 2 is a cross-sectional view and a plan view. 11...Semiconductor substrate, 12...p _E layer, 13...
n _B layer, 14...p _B layer, 15...n _E layer, 16... anode electrode, 17... gate electrode, 18... cathode electrode.

Claims (1)

[Claims] 1. A semiconductor substrate has at least three adjacent semiconductor layers having different conductivity types between a pair of main surfaces, and a first main electrode is provided on one of the main surfaces. In a semiconductor device in which a layer adjacent to the outermost layer in which an outer layer and a control electrode are provided is exposed and a second main electrode is provided on the other main surface, the adjacent layer is such that the entire bottom thereof becomes a lateral diffusion region. a diffusion layer formed using a diffusion mask of a certain size, and a portion connecting at least a portion parallel to the one main surface of the p-n junction formed by the outermost layer and the adjacent layer and the one main surface; is located in the lateral diffusion region. 2. The semiconductor device according to claim 1, wherein the entire pn junction is located in the lateral diffusion region of the adjacent layer.