JPH0218503B2 - - Google Patents
Info
- Publication number
- JPH0218503B2 JPH0218503B2 JP57226612A JP22661282A JPH0218503B2 JP H0218503 B2 JPH0218503 B2 JP H0218503B2 JP 57226612 A JP57226612 A JP 57226612A JP 22661282 A JP22661282 A JP 22661282A JP H0218503 B2 JPH0218503 B2 JP H0218503B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- cpu
- output
- control register
- abnormal signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Emergency Alarm Devices (AREA)
- Alarm Systems (AREA)
- Debugging And Monitoring (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明はCPU暴走監視回路、特にウオツチド
ツグタイマ回路を用いたCPU暴走監視回路に関
する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a CPU runaway monitoring circuit, and particularly to a CPU runaway monitoring circuit using a watchdog timer circuit.
(2) 従来技術と問題点
一般に、CPU（Central Processing Unit；中
央処理装置）が暴走したか否かを監視する場合
に、ウオツチドツグタイマ（Watch Dog
Timer；以下WDTと称する）回路が使用される
ことがある。(2) Prior Art and Problems In general, a watchdog timer is used to monitor whether a CPU (Central Processing Unit) has run out of control.
Timer (hereinafter referred to as WDT) circuit may be used.
このWDT回路は、第１のアクセスと第２のア
クセスとのインターバル時間を測定し、このイン
ターバル時間が所定の基準時間の下限以下または
上限以上の場合に、異常検出信号を出力するよう
になつている。 This WDT circuit measures the interval time between the first access and the second access, and outputs an abnormality detection signal when this interval time is less than or equal to the lower limit or more than the upper limit of a predetermined reference time. There is.
しかし、このWDT回路はモノステーブルマル
チバイブレータにより構成されている。従つて、
従来のようにWDT回路だけでCPU暴走監視回路
を組み立てた場合、電源のノイズ等が原因で
WDT回路が一度もアクセスされていないのに異
常信号を発生することがある。 However, this WDT circuit is composed of a monostable multivibrator. Therefore,
If you assemble a CPU runaway monitoring circuit using only the WDT circuit as in the past, power supply noise etc.
An abnormal signal may be generated even though the WDT circuit has never been accessed.
また、CPUによるソフトウエア処理時間中の
イニシヤルプログラム処理が長くなるとWDT回
路のアクセスインターバル時間が長くなり、
CPUが暴走していないにも拘らずWDT回路から
異常信号が出力することがある。 Additionally, if the initial program processing during the software processing time by the CPU becomes longer, the access interval time of the WDT circuit becomes longer.
An abnormal signal may be output from the WDT circuit even though the CPU is not running out of control.
(3) 発明の目的
本発明の目的は、WDT回路の出力側にゲート
回路を設けることにより正常処理時にはこのゲー
ト回路を閉じてWDT回路から異常信号が送出さ
れないようにしてCPU暴走監視回路の誤動作を
防止することにある。(3) Purpose of the Invention The purpose of the present invention is to prevent malfunction of the CPU runaway monitoring circuit by providing a gate circuit on the output side of the WDT circuit and closing this gate circuit during normal processing to prevent abnormal signals from being sent from the WDT circuit. The goal is to prevent
(4) 発明の構成
本発明によればバスを介してCPUとウオツチ
ドツグ回路を相互接続し、ウオツチドツグ回路か
ら出力される異常信号の有無によりCPUの暴走
を監視する回路において、ウオツチドツグ回路の
出力側にゲート回路が設けられていると共に該ゲ
ート回路の入力側と上記バス間には制御レジスタ
が設けられ、前記CPUのリセツト直後は前記制
御レジスタはリセツトされ異常信号が出力され
ず、前記CPUの初期動作終了後に前記制御レジ
スタにより前記ゲート回路が開かれて異常信号が
出力可能となるようになつていることを特徴とす
るCPU暴走監視回路が提供される。(4) Structure of the Invention According to the present invention, in a circuit that interconnects a CPU and a watchdog circuit via a bus and monitors runaway of the CPU based on the presence or absence of an abnormal signal output from the watchdog circuit, A gate circuit is provided, and a control register is provided between the input side of the gate circuit and the bus, and immediately after the CPU is reset, the control register is reset and no abnormal signal is output, and the initial operation of the CPU is There is provided a CPU runaway monitoring circuit characterized in that, after completion of the process, the gate circuit is opened by the control register so that an abnormal signal can be output.
(5) 発明の実施例
以下、本発明を実施例により添付図面を参照し
て説明する。(5) Embodiments of the Invention The present invention will now be described by way of embodiments with reference to the accompanying drawings.
図は本発明に係るCPU暴走監視回路の構成図
である。 The figure is a configuration diagram of a CPU runaway monitoring circuit according to the present invention.
図の回路は、WDT回路１３の出力側にゲート
回路１４が設けられこのゲート回路１４を制御レ
ジスタ１６で制御することにより、正常時であつ
てもWDT回路を所定の基準時間内にアクセスで
きない場合には異常信号USが出力されないよう
にしたものである。 In the circuit shown in the figure, a gate circuit 14 is provided on the output side of the WDT circuit 13, and this gate circuit 14 is controlled by a control register 16, so that the WDT circuit cannot be accessed within a predetermined reference time even in normal conditions. This prevents the abnormal signal US from being output.
CPU１８は、例えばマイクロプロセツサであ
り、該CPU１８はマイクロプロセツサバス１７
を介してROM１９，RAM２０と接続されてい
る。上記マイクロプロセツサバス１７にはアドレ
スバスインタフエイス回路１０及びデータバスイ
ンタフエイス回路１５が接続されてCPU側と
WDT回路１３側との間で相互接続が確保されて
いる。 The CPU 18 is, for example, a microprocessor, and the CPU 18 is connected to a microprocessor bus 17.
It is connected to ROM 19 and RAM 20 via. An address bus interface circuit 10 and a data bus interface circuit 15 are connected to the microprocessor bus 17 and communicate with the CPU side.
Interconnection with the WDT circuit 13 side is ensured.
アドレスバスインタフエイス回路１０の出力は
第１アドレスデコード回路１１と第２アドレスデ
コード回路１２へ供給される。またデコード回路
１１の出力はWDT回路１３へ、他方デコード回
路１２の出力は制御レジスタ１６へ供給される。
制御レジスタ１６はデータバスインタフエイス回
路１５を介して供給されるデータを上記デコード
回路１２の出力により保持し、ゲート回路１４を
制御する役割を有する。 The output of the address bus interface circuit 10 is supplied to a first address decode circuit 11 and a second address decode circuit 12. Further, the output of the decoding circuit 11 is supplied to the WDT circuit 13, and the output of the decoding circuit 12 is supplied to the control register 16.
The control register 16 has the role of holding data supplied via the data bus interface circuit 15 using the output of the decoding circuit 12, and controlling the gate circuit 14.
上記の構成を有する本発明に係るCPU暴走監
視回路は次のように動作する。 The CPU runaway monitoring circuit according to the present invention having the above configuration operates as follows.
制御レジスタ１６はCPU１８のリセツト直後
はリセツトされて異常信号が出力されず、前記
CPU１８の初期動作終了後に前記制御レジスタ
１６により前記ゲート回路が開かれて異常信号が
出力可能となるようになつている。 Immediately after the CPU 18 is reset, the control register 16 is reset and no abnormal signal is output, and the above-mentioned
After the initial operation of the CPU 18 is completed, the control register 16 opens the gate circuit so that an abnormal signal can be output.
今、電源が投入されてシステムが起動し、
CPUは正常に処理を行なつているが、ソフトウ
エアリセツト時で非常に長い時間イニシヤル処理
が行なわれていると仮定する。そうすると最初の
WDT回路１３へのアクセス時間が基準時間を越
えるので電源ノイズによりWDT回路１３のモノ
マルチが異常信号を発する。 Now, the power is turned on and the system starts,
Assume that the CPU is processing normally, but initial processing is being performed for a very long time at software reset. Then the first
Since the access time to the WDT circuit 13 exceeds the reference time, the monomulti of the WDT circuit 13 issues an abnormal signal due to power supply noise.
ところがROM１９に予め格納されたデータが
データバスインタフエイス回路１５、インタフエ
イス回路１０を経由してデコード回路１２の出力
により制御レジスタ１６に保持されている。従つ
てゲート回路１４は閉鎖された状態を維持し、異
常信号USは出力されない。 However, data previously stored in the ROM 19 is held in the control register 16 via the data bus interface circuit 15 and the interface circuit 10 by the output of the decode circuit 12. Therefore, the gate circuit 14 remains closed and the abnormal signal US is not output.
(6) 発明の効果
上記の通り、本発明によればWDT回路の出力
側にゲート回路が設けられ該ゲート回路が制御レ
ジスタにより制御されることにより、正常処理時
にはWDT回路から異常信号が送出されずCPU暴
走監視回路の誤動作が防止される。(6) Effects of the Invention As described above, according to the present invention, a gate circuit is provided on the output side of the WDT circuit and the gate circuit is controlled by a control register, so that an abnormal signal is not sent from the WDT circuit during normal processing. This prevents the CPU runaway monitoring circuit from malfunctioning.
図は本発明に係るCPU暴走監視回路の構成図
である。
１０……アドレスバスインタフエイス回路、１
１……第１アドレスデコード回路、１２……第２
アドレスデコード回路、１３……WDT回路、１
４……ゲート回路、１５……データバスインタフ
エイス回路、１６……制御レジスタ、１７……マ
イクロプロセツサバス、１８……CPU、１９…
…ROM、２０……RAM。
The figure is a configuration diagram of a CPU runaway monitoring circuit according to the present invention. 10...address bus interface circuit, 1
1...First address decoding circuit, 12...Second
Address decoding circuit, 13...WDT circuit, 1
4...Gate circuit, 15...Data bus interface circuit, 16...Control register, 17...Microprocessor bus, 18...CPU, 19...
...ROM, 20...RAM.
Claims (1)
相互接続し、ウオツチドツグ回路から出力される
異常信号の有無によりCPUの暴走を監視する回
路において、ウオツチドツグ回路の出力側にゲー
ト回路が設けられていると共に該ゲート回路の入
力側と上記バス間には制御レジスタが設けられ、
前記CPUのリセツト直後は前記制御レジスタは
リセツトされ異常信号が出力されず、前記CPU
の初期動作終了後に前記制御レジスタにより前記
ゲート回路が開かれて異常信号が出力可能となる
ようになつていることを特徴とするCPU暴走監
視回路。1. In a circuit that interconnects a CPU and a watchdog circuit via a bus and monitors runaway of the CPU based on the presence or absence of an abnormal signal output from the watchdog circuit, a gate circuit is provided on the output side of the watchdog circuit, and a gate circuit is provided on the output side of the watchdog circuit. A control register is provided between the input side of the circuit and the above bus,
Immediately after resetting the CPU, the control register is reset and no abnormal signal is output, and the CPU
2. A CPU runaway monitoring circuit, wherein the gate circuit is opened by the control register after the initial operation of the CPU is completed, so that an abnormal signal can be output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226612A JPS59119453A (en) | 1982-12-27 | 1982-12-27 | Cpu run-away monitoring circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57226612A JPS59119453A (en) | 1982-12-27 | 1982-12-27 | Cpu run-away monitoring circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59119453A JPS59119453A (en) | 1984-07-10 |
| JPH0218503B2 true JPH0218503B2 (en) | 1990-04-25 |
Family
ID=16847923
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57226612A Granted JPS59119453A (en) | 1982-12-27 | 1982-12-27 | Cpu run-away monitoring circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59119453A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61296443A (en) * | 1985-06-24 | 1986-12-27 | Mitsubishi Electric Corp | Watchdog timer |
| JPS6260038A (en) * | 1985-09-10 | 1987-03-16 | Hochiki Corp | Watchdog circuit |
| JPS6310248A (en) * | 1986-06-30 | 1988-01-16 | Nec Corp | Detecting system for abnormal state of microprocessor |
| JPH01211138A (en) * | 1988-02-19 | 1989-08-24 | Fujitsu Ltd | Resetting circuit for supervising circuit of computer system |
| JPH01172152U (en) * | 1988-05-24 | 1989-12-06 | ||
| JPH0325943U (en) * | 1989-07-24 | 1991-03-18 | ||
| US7432504B2 (en) * | 2005-09-27 | 2008-10-07 | Xerox Corporation | Dicorotron wire assembly removal and storage tool |
| JP5625949B2 (en) * | 2011-01-25 | 2014-11-19 | 日本電気株式会社 | System monitoring apparatus and system monitoring method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56103723A (en) * | 1980-01-23 | 1981-08-19 | Nippon Denso Co Ltd | Automatic reset method for computer |
-
1982
- 1982-12-27 JP JP57226612A patent/JPS59119453A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59119453A (en) | 1984-07-10 |
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