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JPH0218609B2 - - Google Patents
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JPH0218609B2 - - Google Patents

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Publication number
JPH0218609B2
JPH0218609B2 JP3418482A JP3418482A JPH0218609B2 JP H0218609 B2 JPH0218609 B2 JP H0218609B2 JP 3418482 A JP3418482 A JP 3418482A JP 3418482 A JP3418482 A JP 3418482A JP H0218609 B2 JPH0218609 B2 JP H0218609B2
Authority
JP
Japan
Prior art keywords
power supply
resistor
connection point
common connection
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3418482A
Other languages
Japanese (ja)
Other versions
JPS58151103A (en
Inventor
Masami Fujiwara
Tsukasa Nishino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Columbia Co Ltd
Original Assignee
Nippon Columbia Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Columbia Co Ltd filed Critical Nippon Columbia Co Ltd
Priority to JP3418482A priority Critical patent/JPS58151103A/en
Publication of JPS58151103A publication Critical patent/JPS58151103A/en
Publication of JPH0218609B2 publication Critical patent/JPH0218609B2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Description

【発明の詳細な説明】 本発明は増幅回路の改良に関する。[Detailed description of the invention] The present invention relates to improvements in amplifier circuits.

従来より、広帯域且つ低雑音特性を有するカス
コード増幅回路が広くもちいられている。
Conventionally, cascode amplifier circuits having wideband and low noise characteristics have been widely used.

しかしながらこの様な従来のカスコード増幅回
路では出力端子に高い直流電圧が生じている為、
次段との直結接続が自由に出来ない等の欠点を有
する。上記の如きカスコード増巾回路の優れた広
帯域低雑音特性を損うことなく、上述の欠点を除
き次段との直結接続が容易な第1図の様な増幅器
を、本出願人は特願昭56−80912号「増幅器」と
して提案した。
However, in such a conventional cascode amplifier circuit, a high DC voltage is generated at the output terminal, so
It has drawbacks such as not being able to freely connect directly to the next stage. The present applicant has proposed an amplifier as shown in Fig. 1, which can easily be directly connected to the next stage without impairing the excellent wide-band low-noise characteristics of the cascode amplification circuit as described above, and which eliminates the above-mentioned drawbacks. No. 56-80912 was proposed as "Amplifier".

第1図において、入力信号は、抵抗2で接地さ
れた入力端子1から第1のトランジスタの制御電
極即ちFET3のゲートに印加され、ドレインは
定電流源10を介して正電源+Bに接続されると
共に、ベース接地入力型となる第2のトランジス
タ即ちトランジスタ12のエミツタに接続され、
ソースは抵抗5を介して接地される。トランジス
タ12の制御電極即ちベースは直流電源6によつ
て所定の直流電圧が印加され、コレクタは抵抗1
4を介して負電源−Bに接続されると共に出力端
子15に接続される。
In FIG. 1, an input signal is applied from an input terminal 1 grounded through a resistor 2 to the control electrode of the first transistor, that is, the gate of FET 3, and the drain is connected to the positive power supply +B via a constant current source 10. and is connected to the emitter of a second transistor, that is, transistor 12, which is a common base input type,
The source is grounded via a resistor 5. A predetermined DC voltage is applied to the control electrode, that is, the base of the transistor 12 by the DC power supply 6, and the collector is connected to the resistor 1.
4 to the negative power supply -B and to the output terminal 15.

以上の構成に於て、従来のカスコード増幅器と
比較すると、FET3とトランジスタ12の極性
が異極性である点、トランジスタ12に接続され
た抵抗14が正電源でなく負電源−Bに接続され
ている点、そしてFET3とトランジスタ12の
共通接続点から正電源+Bに対して定電流源9が
接続されている点が異なるが、交流的は従来と等
価なカスコード動作をする。
In the above configuration, compared to a conventional cascode amplifier, the polarity of FET 3 and transistor 12 are different, and the resistor 14 connected to transistor 12 is connected to negative power supply -B instead of positive power supply. The difference is that a constant current source 9 is connected to the positive power supply +B from the common connection point of the FET 3 and the transistor 12, but the alternating current performs a cascode operation equivalent to the conventional one.

即ち、仮に入力端子1に正の信号が印加される
と、FET3の電流は増加する。従つてトランジ
スタ12の電流はこの増加分だけ減少し、出力端
子15のレベルは負となる。この様に交流動作は
従来と等しいカスコード動作の反転増巾器であ
り、カスコード増巾回路の広帯域低雑音特性等を
保有している。
That is, if a positive signal is applied to the input terminal 1, the current of the FET 3 increases. Therefore, the current in transistor 12 decreases by this increase, and the level at output terminal 15 becomes negative. In this way, the AC operation is the same as the conventional cascode operation inverting amplifier, and it has the broadband low noise characteristics of the cascode amplifier circuit.

次に直流動作について説明する。FET3の動
作電流は定電流源10によつて供給され、そして
該定電流源10の電流値からFET3の動作電流
を減算した電流値がトランジスタ12に供給され
る。トランジスタ12のベースには直流電源6に
よつて直流電圧が印加されているから、前記
FET3のドレイン電圧はほぼ直流電源6の電圧
値に等しい電圧に保持されFET3の直流動作は
従来のカスコード増幅器と等しくなる。又FET
3の動作電流は該FET3の特性と抵抗5の抵抗
値で定まる。そしてトランジスタ12のコレクタ
は抵抗14を介して負電源−Bに接続されている
から、増幅度の制約等で抵抗14の抵抗値が制約
されている場合でも定電流源10の電流値あるい
は負電源−Bの電圧値の設定次第で出力端子15
の直流電位を任意の電圧値に設定出来るし、当然
接地電位にも設定出来るので次段との直結接続も
容易である。
Next, DC operation will be explained. The operating current of the FET 3 is supplied by a constant current source 10, and a current value obtained by subtracting the operating current of the FET 3 from the current value of the constant current source 10 is supplied to the transistor 12. Since a DC voltage is applied to the base of the transistor 12 by the DC power supply 6, the above-mentioned
The drain voltage of FET 3 is maintained at a voltage approximately equal to the voltage value of DC power supply 6, and the DC operation of FET 3 is equivalent to that of a conventional cascode amplifier. Also FET
The operating current of FET 3 is determined by the characteristics of FET 3 and the resistance value of resistor 5. Since the collector of the transistor 12 is connected to the negative power supply -B via the resistor 14, even if the resistance value of the resistor 14 is restricted due to restrictions on the degree of amplification, the current value of the constant current source 10 or the negative power supply - Output terminal 15 depending on the setting of the voltage value of B.
Since the DC potential of can be set to any voltage value, and of course it can also be set to ground potential, direct connection to the next stage is easy.

第2図は上述の様な増幅器をプツシユプル接続
にすると共に、カスコードブートストラツプ接続
する為に、トランジスタ12及び13のベースに
接続された電源(定電圧素子)6及び7の他端を
FET3及び4のソースに接続したもので、通常
のカスコードブートストラツプ回路と同様の特長
を有しており、しかも、出力端子15の直流電位
を接地電位とすることが出来る。
Figure 2 shows the other ends of the power supplies (constant voltage elements) 6 and 7 connected to the bases of transistors 12 and 13 in order to make the above-mentioned amplifiers push-pull connected and to make cascode bootstrap connections.
It is connected to the sources of FETs 3 and 4, and has the same features as a normal cascode bootstrap circuit, and in addition, the DC potential of the output terminal 15 can be set to the ground potential.

しかし、第2図の様に電源を2つ必要とする欠
点がある。又図中に示された電源16及び17は
実際には理想的な直流電源ではなく、図中に示し
た如く電源16は理想的な直流電源E1とリツプ
ル成分や雑音成分等を含む電源e1、電源17は理
想的な直流電源E2とリツプル成分や雑音成分等
を含む電源e2に分けられる。ここで電源e1から流
れる電流は、電源e1→抵抗器8→定電圧素子6→
抵抗器5→接地→電源e1なる経路で流れる。一方
電源e2から流れる電流は電源e2→接地→抵抗器5
→定電圧素子7→抵抗器9→電源e2なる経路で流
れる。従つて、もし電源e1及びe2の電圧値が同振
幅逆位相であれば抵抗器5の両端にはリツプル成
分や雑音成分等は生じず、従つて出力端子15に
はリツプル成分や雑音成分特は生じない。しか
し、実際は電源e1及びe2の電圧値が同振幅逆位相
となり得ないので、抵抗器5の両端にはリツプル
成分や雑音成分等を生じ、従つて出力端子15に
はリツプル成分や雑音成分等を生じる欠点があつ
た。
However, as shown in FIG. 2, there is a drawback that two power supplies are required. Furthermore, the power supplies 16 and 17 shown in the figure are not actually ideal DC power supplies, and as shown in the figure, the power supply 16 is an ideal DC power supply E1 and a power supply e that includes ripple components, noise components, etc. 1 , the power supply 17 is divided into an ideal DC power supply E2 and a power supply e2 containing ripple components, noise components, etc. Here, the current flowing from the power source e 1 is as follows: power source e 1 → resistor 8 → constant voltage element 6 →
It flows through the following path: resistor 5 → ground → power supply e 1 . On the other hand, the current flowing from power supply e 2 is power supply e 2 → ground → resistor 5
→ Constant voltage element 7 → Resistor 9 → Power supply e It flows through the following path : 2 . Therefore, if the voltage values of the power supplies e 1 and e 2 have the same amplitude and opposite phase, no ripple component or noise component will occur at both ends of the resistor 5, and therefore no ripple component or noise component will occur at the output terminal 15. No special effects occur. However, in reality, the voltage values of the power supplies e 1 and e 2 cannot have the same amplitude and opposite phase, so ripple components and noise components are generated at both ends of the resistor 5, and therefore, ripple components and noise components are generated at the output terminal 15. There were some drawbacks such as:

本発明は、上述の様な欠点を除去すべく成され
たもので、電源の簡略な増幅回路、又は電源にリ
ツプル成分や雑音成分等が含まれていても、出力
にはリツプル成分や雑音成分等を生じない増幅回
路を提供する事を目的とするものである。
The present invention has been made to eliminate the above-mentioned drawbacks, and even if the power supply has a simple amplification circuit or the power supply contains ripple components or noise components, the output will still contain ripple components or noise components. The purpose of this invention is to provide an amplifier circuit that does not cause such problems.

以下、本発明を実施例に従つて詳細に説明す
る。
Hereinafter, the present invention will be explained in detail according to examples.

第3図は本発明の一実施例を示す回路図であ
り、第2図と対応する所は同一符号を付して説明
を省略するも、第2図と異つている所は第2図で
示された電源16及び17をフローテイング電源
18にした事である。他の部分については第2図
と同一である。
FIG. 3 is a circuit diagram showing one embodiment of the present invention. Parts corresponding to those in FIG. 2 are given the same reference numerals and explanations are omitted. The power supplies 16 and 17 shown are replaced by floating power supplies 18. Other parts are the same as in FIG. 2.

この場合でもフローテイング電源18が理想的
な直流電源ではなく、第3図に示された様に、理
想的な直流電源E3とリツプル成分や雑音成分等
を含む電源e3に分けられる。ここで電源e3から流
れる電流は、電源e3→抵抗器8→定電圧素子6→
定電圧素子7→抵抗器9→電源e3なる経路で流
れ、抵抗器5の両端にはリツプル成分や雑音成分
等は生じず、従つて出力端子15にもリツプル成
分や雑音成分は生じない。
Even in this case, the floating power supply 18 is not an ideal DC power supply, but is divided into an ideal DC power supply E 3 and a power supply e 3 containing ripple components, noise components, etc., as shown in FIG. Here, the current flowing from power supply e 3 is: power supply e 3 → resistor 8 → constant voltage element 6 →
The current flows through the constant voltage element 7→resistor 9→power supply e3 , and no ripple or noise components are generated at both ends of the resistor 5, and therefore no ripple or noise components are generated at the output terminal 15 either.

この次に入力端子1に入力信号eiを入力したと
きの出力端子15に現われる出力信号e0を求め
る。入力信号eiがFET3及び4のゲートに入力さ
れると、FET3及び4に流れる電流は抵抗器5
の抵抗値によつて決定される電流値となる。又、
FET3に流れる電流I1は、FET3→トランジス
タ12→抵抗器14→抵抗器5→FET3なる経
路で流れる。一方、FET4に流れる電流I2
FET4→抵抗器5→抵抗器14→トランジスタ
13→FET4なる経路で流れる。即ち、抵抗器
5に流れる電流は、全て抵抗器14に流れる事に
なる。(ここでFET3及び7のゲート・リーク電
流やトランジスタ12及び13のベース電流等は
無視している。)従つて抵抗器5及び14の抵抗
値をそれぞれR5及びR14とし、FET3及び4の相
互コンダクタンスを無視すると、出力信号e0は e0=−R14/R5eiとなる。
Next, when the input signal ei is input to the input terminal 1, the output signal e 0 appearing at the output terminal 15 is determined. When the input signal ei is input to the gates of FETs 3 and 4, the current flowing through FETs 3 and 4 is
The current value is determined by the resistance value of . or,
The current I 1 flowing through the FET3 flows through a path of FET3→transistor 12→resistor 14→resistor 5→FET3. On the other hand, the current I 2 flowing through FET4 is
It flows through the path FET4→Resistor 5→Resistor 14→Transistor 13→FET4. That is, all of the current flowing through the resistor 5 will flow through the resistor 14. (Here, we ignore the gate leakage currents of FETs 3 and 7, the base currents of transistors 12 and 13, etc.) Therefore, let the resistance values of resistors 5 and 14 be R 5 and R 14 , respectively, and Ignoring transconductance, the output signal e 0 becomes e 0 =−R 14 /R 5 ei.

又、第9図において定電圧素子6及び7の共通
接続点をFET3及び4のゲートに接続しても同
様の効が得られる。又上記共通接続点を接地すれ
ばカスコード増幅回路と同様の特性が得られ、電
源は1つでよい。
Furthermore, the same effect can be obtained by connecting the common connection point of constant voltage elements 6 and 7 to the gates of FETs 3 and 4 in FIG. Furthermore, if the common connection point is grounded, characteristics similar to those of a cascode amplifier circuit can be obtained, and only one power supply is required.

又、本発明で使用しているFETはバイポーラ
トランジスタでもよく、トランジスタはFETで
も良い事はもち論である。
Furthermore, it goes without saying that the FET used in the present invention may be a bipolar transistor, and the transistor may also be a FET.

以上説明した様に本発明によれば電源にリツプ
ル成分や雑音成分等を含んでいても、出力にはそ
の影響を生じないという優れた効果を得る事が出
来る。
As explained above, according to the present invention, even if the power supply contains ripple components, noise components, etc., it is possible to obtain the excellent effect that the output is not affected by the ripple components or noise components.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は本出願人が特願昭56−
80912号「増幅器」として提案した増幅器を示す
回路図、第3図は本発明の一実施例を示す回路図
である。 図中、3及び4はFET、6及び7は定電圧素
子、2,5,8,9及び14は抵抗器、18はフ
ローデイング電源、10及び11は定電流源であ
る。
Figures 1 and 2 were filed by the applicant in a patent application published in 1983.
A circuit diagram showing an amplifier proposed as "Amplifier" in No. 80912, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. In the figure, 3 and 4 are FETs, 6 and 7 are constant voltage elements, 2, 5, 8, 9 and 14 are resistors, 18 is a floating power supply, and 10 and 11 are constant current sources.

Claims (1)

【特許請求の範囲】[Claims] 1 ソース又はエミツタ同志が接続され第1の共
通接続点とすると共にゲート又はベース同志が接
続され入力端とした互いに導電型の異なるトラン
ジスタの第1の直列回路と、ドレイン又はコレク
タ同志が接続され第2の共通接続点とすると共に
出力端とした互いに導電型の異なるトランジスタ
の第2の直列回路と、第2の直列回路の各トラン
ジスタのゲート又はベースに上記第1の共通接続
点からそれぞれバイアス電圧を印加するバイアス
電圧印加手段と、上記第1の共通接続点を設地す
る第1の抵抗と、上記第2の共通接続点を設地す
る第2の抵抗と、上記第1及び第2の直列回路に
よる並列回路の両端にそれぞれ定電流源を介して
供給するフローテイング電源とを具備し供給され
る電源に含まれるリツプルや雑音が出力端に出力
されるのを防止したことを特徴とする増幅回路。
1. A first series circuit of transistors of different conductivity types, whose sources or emitters are connected together to form a first common connection point, and whose gates or bases are connected to form an input terminal; A second series circuit of transistors of different conductivity types which are used as a common connection point and an output terminal of the two transistors, and a bias voltage is applied from the first common connection point to the gate or base of each transistor in the second series circuit. a bias voltage applying means for applying a bias voltage, a first resistor for providing the first common connection point, a second resistor for providing the second common connection point, and a bias voltage applying means for applying the first and second It is characterized by having floating power supplies supplied via constant current sources to both ends of a parallel circuit made up of a series circuit, and preventing ripples and noise contained in the supplied power from being output to the output terminals. Amplification circuit.
JP3418482A 1982-03-04 1982-03-04 Amplifying circuit Granted JPS58151103A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3418482A JPS58151103A (en) 1982-03-04 1982-03-04 Amplifying circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3418482A JPS58151103A (en) 1982-03-04 1982-03-04 Amplifying circuit

Publications (2)

Publication Number Publication Date
JPS58151103A JPS58151103A (en) 1983-09-08
JPH0218609B2 true JPH0218609B2 (en) 1990-04-26

Family

ID=12407105

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3418482A Granted JPS58151103A (en) 1982-03-04 1982-03-04 Amplifying circuit

Country Status (1)

Country Link
JP (1) JPS58151103A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0471724U (en) * 1990-10-30 1992-06-25

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0471724U (en) * 1990-10-30 1992-06-25

Also Published As

Publication number Publication date
JPS58151103A (en) 1983-09-08

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