JPH0218610B2 - - Google Patents
Info
- Publication number
- JPH0218610B2 JPH0218610B2 JP21115981A JP21115981A JPH0218610B2 JP H0218610 B2 JPH0218610 B2 JP H0218610B2 JP 21115981 A JP21115981 A JP 21115981A JP 21115981 A JP21115981 A JP 21115981A JP H0218610 B2 JPH0218610 B2 JP H0218610B2
- Authority
- JP
- Japan
- Prior art keywords
- agc
- voltage
- fet
- amplifier
- shows
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/3005—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers
- H03G3/301—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being continuously variable
- H03G3/3015—Automatic control in amplifiers having semiconductor devices in amplifiers suitable for low-frequencies, e.g. audio amplifiers the gain being continuously variable using diodes or transistors
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は広い可変利得範囲にわたり直線性が良
好で雑音の少ないAGC増幅器に関す。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an AGC amplifier with good linearity and low noise over a wide variable gain range.
(2) 技術の背景
従来、ビデオ機器用のAGC増幅器としては入
出力特性のダイナミツクレンジが広く、雑音の少
いものが使用され、そのAGC回路素子に電界効
果トランジスタが使用されている。(2) Background of the technology Conventionally, AGC amplifiers for video equipment have been used that have a wide dynamic range of input/output characteristics and have low noise, and field-effect transistors have been used as the AGC circuit elements.
近年情報伝送の多様化と共に更に高品質、高解
像度のテレビが必要とされ、これの伝送用AGC
増幅器には更に直線性の優れたダイナミツクレン
ヂを有し、雑音の少いAGC増幅器が要望されて
いるが、現在の電界効果トランジスタではピンチ
オン特性が２乗特性を有するため十分な特性が得
られない欠点がある。 In recent years, with the diversification of information transmission, even higher quality and higher resolution televisions are required, and AGC for this transmission is needed.
There is a demand for AGC amplifiers with even better linearity, dynamic range, and less noise, but current field-effect transistors have pinch-on characteristics that are square-law characteristics, so sufficient characteristics cannot be obtained. There are no drawbacks.
(3) 従来技術と問題点
第１図は従来例のAGC増幅器のブロツク図を
示す。入力端子１より入力された入力信号VSは、
主増幅器２で増幅されその出力電圧V0は端子３
より出力される。(3) Prior art and problems Figure 1 shows a block diagram of a conventional AGC amplifier. The input signal V S input from input terminal 1 is
Main amplifier 2 amplifies its output voltage V 0 at terminal 3
It is output from
出力電圧V0の一部は検波器４で検出され、該
検出電圧VGは端子５を経てAGC素子６を制御し、
制御された電圧は主増幅器２のレベル変動を制御
して出力電圧V0を一定にする。 A part of the output voltage V0 is detected by the detector 4, and the detected voltage VG controls the AGC element 6 via the terminal 5,
The controlled voltage controls the level fluctuation of the main amplifier 2 to keep the output voltage V 0 constant.
第２図はAGC回路素子に電界効果トランジス
タ（以下FETと記す）を用いた従来例のAGC増
幅器である。 FIG. 2 shows a conventional AGC amplifier using field effect transistors (hereinafter referred to as FETs) as AGC circuit elements.
AGC回路素子に使用されているFETのドレイ
ン電流特性は第４図に示す如くピンチオン特性が
自乗特性になつている。広いダイナミツクレンヂ
で出力電圧をこのFETで制御する場合、ピンチ
オン電圧VP附近より使用することになるから
AGC特性の直線性が得られないことになる。 The drain current characteristic of the FET used in the AGC circuit element is such that the pinch-on characteristic becomes a square-law characteristic, as shown in FIG. When controlling the output voltage with this FET over a wide dynamic range, it will be used near the pinch-on voltage V P.
This means that linearity of AGC characteristics cannot be obtained.
第３図はAGC素子に差動対のトランジスタを
用いた場合の従来例を示す。 FIG. 3 shows a conventional example in which a differential pair of transistors is used as an AGC element.
主増幅器２としてのトランジスタTR１に流れ
る信号電流i0はAGC回路素子６であるトランジス
タTR２の制御電圧VG2により制御され、トラン
ジスタTR１の利得を可変するが、TR１に流す
直流バイアス電流I0は信号電流i0に比べて充分大
さくしないと直線性が劣化する。 The signal current i 0 flowing through the transistor TR1 as the main amplifier 2 is controlled by the control voltage V G2 of the transistor TR2, which is the AGC circuit element 6 , and varies the gain of the transistor TR1. If the current i is not made sufficiently large compared to 0 , linearity will deteriorate.
上記の如く信号電流i0が大きくなるとトランジ
スタTR２がエミツタ結合増幅器を構成するた
め、TR２自身が大きな雑音源となる。特にTR
２，TR３の信号電流i1i2のとき雑音が多くなる
等の欠点を有する。 As described above, when the signal current i 0 becomes large, the transistor TR2 constitutes an emitter-coupled amplifier, so that the transistor TR2 itself becomes a large noise source. Especially T.R.
2. It has drawbacks such as increased noise when the signal current of TR3 is i 1 i 2 .
(4) 発明の目的
本発明は上記の欠点に鑑み、広い利得可変範囲
にわたつて直線性が良好で、雑音の少ないAGC
増幅器を提供することを目的とする。(4) Purpose of the Invention In view of the above drawbacks, the present invention provides an AGC with good linearity over a wide variable gain range and with low noise.
The purpose is to provide an amplifier.
(5) 発明の構成
そして本発では前記目的を達成するため、直流
電流帰還形増幅回路の直列電流帰還素子として、
FETによる電圧制御抵抗素子を用いて、該FET
の一方のゲートに前記増幅回路の出力を検波して
得られる利得制御電圧を与えることにより自動的
に利得制御を行うAGC増幅器に於いて、
前記FETのもう一方のゲートに前記FETのド
レイン、ソース間電圧を１対１に分圧した電圧が
加わわるよう構成するものである。(5) Structure of the invention In order to achieve the above object, the present invention uses a series current feedback element of a DC current feedback amplifier circuit.
Using a voltage controlled resistance element using an FET,
In an AGC amplifier that automatically controls the gain by applying a gain control voltage obtained by detecting the output of the amplifier circuit to one gate of the FET, the drain and source of the FET are connected to the other gate of the FET. The structure is such that a voltage obtained by dividing the voltage between the two terminals in a one-to-one ratio is applied.
(6) 発明の実施例
以下本発明を図面によつて述べる。第５図は本
発明の原理を説明するためAGC回路素子の回路
図を示す。(6) Embodiments of the invention The present invention will be described below with reference to the drawings. FIG. 5 shows a circuit diagram of an AGC circuit element to explain the principle of the present invention.
第５図のAGC回路素子６′において、FET７の
第１ゲートG1にはドレイン電圧VDをR1，R2で分
圧した帰還電圧がバイアス電圧として与えられ、
第２ゲートにはAGC制御電圧VG′が入力されてい
る。 In the AGC circuit element 6' of FIG. 5, a feedback voltage obtained by dividing the drain voltage V D by R 1 and R 2 is applied to the first gate G 1 of the FET 7 as a bias voltage.
AGC control voltage V G ' is input to the second gate.
以上の如く、ドレイン電圧の一部を抵抗R1を
介して第１ゲートに帰還することにより、ドレイ
ン、ソース間抵抗の非直線を直線性に改善する。 As described above, by feeding back a portion of the drain voltage to the first gate via the resistor R1 , the non-linearity of the resistance between the drain and the source is improved to linearity.
FETのドレイン電流IDは第４図に示す如くピン
チオン領域付近では、
ID＝Ａ〔（VG−VP）VD−１／２VD 2〕 ……(1)
と近似出来る。但しVG：ゲート電圧、VP：ピン
チオン電圧、Ａ：定数とする。 As shown in FIG. 4, the drain current I D of the FET can be approximated as I D =A[(V G −V P )V D −1/2V D 2 ] (1) near the pinch-on region. However, V G is a gate voltage, V P is a pinch-on voltage, and A is a constant.
ここでドレイン、ソース間電圧の一部を第１ゲ
ートに帰還すると、
VG＝VG′＋kVD
（０ｋ１、ｋ＝R1／（R1＋R2）とする）よ
り、
ID＝Ａ〔（VG′−VP）VD＋（ｋ−１／２）VD 2〕
＝Ａ〔BVD＋（ｋ−１／２）VD 2〕
となる。ここでＢ＝（VG−VP）は定数とする。 Here , if part of the drain-source voltage is fed back to the first gate , then I D = A [ (V G ′-V P )V D +(k-1/2)V D 2 ]=A[BV D +(k-1/2)V D 2 ]. Here, B=(V G −V P ) is a constant.
ここでｋ＝１／２とすると（つまりドレイン、
ソース間電圧を１対１に分圧すると）rDSはrDS＝
VD／ID＝１／（Ａ・Ｂ）ドレイン、ソース間抵抗
rDSはrDS＝VD／ID＝１／Ａ・Ｂとなり、非直線歪発生項
となつている２次項の成分が除去され、直線性の
良好なAGC回路素子が構成される。 Here, if k = 1/2 (that is, the drain,
If the voltage between sources is divided 1:1) r DS is r DS =
V D /I D =1/(A・B) Drain-source resistance
r DS becomes r DS =V D /I D =1/A·B, and the second-order term component, which is a nonlinear distortion generation term, is removed, and an AGC circuit element with good linearity is constructed.
第６図は第５図で示したAGC回路素子を用い
た本発明の実施例を示す。 FIG. 6 shows an embodiment of the present invention using the AGC circuit element shown in FIG.
第６図において、入力信号は端子１より入力さ
れ、AGC増幅器２′を構成するトランジスタ８で
増幅されコンデンサC2を経て出力端子３より出
力される。出力電圧V0の一部は検波器４′で検波
され、その検出電圧はFET７の第２ゲートG2に
入力され、FET７を制御する。FET７の第一ゲ
ートには可変抵抗９によつて、ドレイン電圧VD
を分圧した電圧ｋ・VGが帰還されている。この
帰還によつてFET７のダイナミツクレンヂの直
線性が改善されることは前述の通りである。前記
の検出電圧は雑音特性の良いFET７を経て端子
１０から主増幅器２′のコンデンサC3を介してト
ランジスタ８のエミツタに入力され、主増幅器
２′の利得が一定になるように制御する。 In FIG. 6, an input signal is inputted from terminal 1, amplified by transistor 8 constituting AGC amplifier 2', and outputted from output terminal 3 via capacitor C2. A part of the output voltage V 0 is detected by the detector 4', and the detected voltage is input to the second gate G 2 of the FET 7 to control the FET 7. A variable resistor 9 connects the first gate of the FET 7 to the drain voltage V D
The divided voltage k·V G is fed back. As described above, this feedback improves the linearity of the dynamic range of the FET 7. The detected voltage is input from terminal 10 through FET 7, which has good noise characteristics, to the emitter of transistor 8 via capacitor C3 of main amplifier 2', and is controlled so that the gain of main amplifier 2' is constant.
第７図、第８図は第６図のAGC増幅器入出力
特性とＳ／Ｎを示すもので、第７図は入出力特性
のダイナミクレンヂの直線性を微分特性で示した
もので図でＩは従来例の特性、は本発明による
特性、は直線性のしきい値を示す。従来例に対
し、本発明実施例は約２倍のダイナミツクレンジ
（W1≒2W2）を有する。 Figures 7 and 8 show the input/output characteristics and S/N of the AGC amplifier in Figure 6, and Figure 7 shows the linearity of the dynamic range of the input/output characteristics as a differential characteristic. is the characteristic of the conventional example, is the characteristic according to the present invention, and is the linearity threshold. Compared to the conventional example, the embodiment of the present invention has about twice the dynamic range (W 1 ≈2W 2 ).
第８図はビデオ信号帯域での雑音特性を示すも
ので、入力レベルに対しＳ／N60dB以上が得ら
れる。 FIG. 8 shows the noise characteristics in the video signal band, and an S/N of 60 dB or more can be obtained with respect to the input level.
(7) 発明の効果
以上本発明によればFETのドレインからゲー
トに帰還をかけることによりダイナミツクレンヂ
の直線性を大幅に改善出来、またFETをAGC素
子に用いるので雑音特性も良くなる等の利点を有
する。(7) Effects of the Invention According to the present invention, the linearity of the dynamic range can be greatly improved by applying feedback from the drain of the FET to the gate, and since the FET is used as the AGC element, the noise characteristics can also be improved. has advantages.
第１〜３図は従来例のAGC増幅器のブロツク
図、第２図はAGC回路素子にFETを用いたもの、
第３図はAGC回路素子に差動対トランジスタを
用いたもの、第４図はドレイン電流特性、第５図
は本発明の原理を示す図、第６図は実施例、第７
図は本発明の微分特性、第８図は本発明のＳ／Ｎ
を示す。
図中、１，３，５は端子、２，２′は主増幅器、
４，４′は検波器、６，６′はAGC回路素子、７
はFET、８はトランジスタ、９は可変抵抗器、
１０はAGC入力端子を示す。
Figures 1 to 3 are block diagrams of conventional AGC amplifiers, Figure 2 is one using FETs as AGC circuit elements,
Fig. 3 shows an AGC circuit using differential pair transistors, Fig. 4 shows drain current characteristics, Fig. 5 shows the principle of the present invention, Fig. 6 shows an example, and Fig. 7 shows an example of the present invention.
The figure shows the differential characteristics of the present invention, and Figure 8 shows the S/N of the present invention.
shows. In the figure, 1, 3, 5 are terminals, 2, 2' are main amplifiers,
4, 4' are detectors, 6, 6' are AGC circuit elements, 7
is FET, 8 is transistor, 9 is variable resistor,
10 indicates an AGC input terminal.
Claims (1)
として、FET（電界効果トランジスタ）による電
圧制御抵抗素子を用いて、該FETの一方のゲー
トに前記増幅回路の出力を検波して得られる利得
制御電圧を与えることにより自動的に利得制御を
行うAGC増幅器に於いて、 前記FETのもう一方のゲートに前記FETのド
レイン、ソース間電圧を１対１に分圧した電圧が
加わわるようにしたことを特徴とするAGC増幅
器。[Claims] 1. A voltage controlled resistance element using an FET (field effect transistor) is used as a series current feedback element of a DC current feedback amplifier circuit, and the output of the amplifier circuit is detected at one gate of the FET. In an AGC amplifier that automatically performs gain control by applying a gain control voltage obtained from An AGC amplifier characterized by being designed to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21115981A JPS58114616A (en) | 1981-12-28 | 1981-12-28 | Agc amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21115981A JPS58114616A (en) | 1981-12-28 | 1981-12-28 | Agc amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58114616A JPS58114616A (en) | 1983-07-08 |
| JPH0218610B2 true JPH0218610B2 (en) | 1990-04-26 |
Family
ID=16601366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21115981A Granted JPS58114616A (en) | 1981-12-28 | 1981-12-28 | Agc amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114616A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0432214U (en) * | 1990-07-12 | 1992-03-16 |
-
1981
- 1981-12-28 JP JP21115981A patent/JPS58114616A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0432214U (en) * | 1990-07-12 | 1992-03-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58114616A (en) | 1983-07-08 |
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