JPH0219632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a solid-state imaging device.

Conventional configurations and their problems In recent years, the characteristics of solid-state imaging devices have improved significantly, and interline transfer type CCDs have not only been put into practical use, but some have even surpassed imaging tubes. However, the so-called smear phenomenon, which occurs when part of the charge generated by incident light enters the transfer means, still needs to be improved. The P-well structure is considered effective against this smear phenomenon.

FIG. 1 is a cross-sectional structural diagram of an imaging section of a conventional P-well structure interline transfer type CCD.
In the figure, signal charges accumulated in a photoelectric conversion element 1 are transferred to a vertical CCD channel 3 by applying an appropriate voltage to a transfer electrode 2, and are transferred therein. If excessive charge is generated due to strong incident light, an appropriate reverse bias voltage is applied between the n-type substrate 6 and the P-wells 5 and 4, and the photoelectric conversion element 1, -P-well 4-n Excess charge is transferred to the n-type substrate 6 by utilizing the punch-through effect between the type substrates 6.
Blooming is suppressed by discharging For this purpose, the thickness of the P well 4 under the photoelectric conversion element 1 must be thin (about 2 to 4 μm). On the other hand, the P-well 5 around the vertical CCD channel 3 must be thick (about 7 to 10 microns) for normal operation of the vertical CCD. In the P-well structure described above, it is first necessary to form a P-well with a two-stage concentration profile, and since the P-well 4 below the photoelectric conversion element 1 is located at a shallow position, the sensitivity decreases and In particular, the decrease in sensitivity to long wavelength light is remarkable. In addition, since the P-well 5 around the vertical CCD channel 3 is diffused to a deep position, as the pitch of the unit pixel becomes smaller due to the miniaturization of the device and the increase in the number of pixels, the deep P-well 5 becomes
It spreads to the region of the P well 4, and the shallow P well region decreases, making it difficult to control the formation of the shallow P well region. This means a decline or loss of the ability to suppress blooming, which is extremely serious.
Furthermore, if the deep P-well extends below the photoelectric conversion element, the charges generated by photoelectric conversion will be vertically
This is a big problem because it becomes easy to get mixed into the CCD channel 3 and smear increases.

Purpose of the Invention In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing a solid-state imaging device that can easily control the process even when the pixel pitch is small, suppresses smear and blooming phenomena, and can produce a highly sensitive solid-state imaging device. It provides:

Structure of the Invention In order to achieve this object, the method for manufacturing a solid-state imaging device of the present invention includes forming an impurity layer of an opposite conductivity type on a semiconductor substrate of one conductivity type, and forming an impurity layer of an opposite conductivity type on a semiconductor substrate of one conductivity type. The method includes forming an impurity layer, and further forming an impurity region of an opposite conductivity type in a part of the impurity layer of one conductivity type.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 2 shows the steps of a method for manufacturing a solid-state imaging device according to an embodiment of the present invention. FIG. 2A shows a P-type impurity layer 11 formed on an N-type substrate 10. FIG. FIG. 2b shows an n-type impurity layer 12 thereon.
This shows how it was formed. As for the formation method up to this point, diffusion by thermal diffusion and high-temperature treatment, or diffusion by ion implantation and high-temperature treatment can be used, but P-type impurity layer 11 and n-type impurity layer
If at least one of 2 is formed by epitaxial growth, controllability will be better. That is,
The state shown in FIG. 2b may also be achieved by epitaxial growth. FIG. 2c shows that a P-type impurity region 13 is further formed and connected to the P-type impurity layer 11.

The formation order up to this point has been formed one layer at a time for the sake of explanation, but when using the ion implantation method, if ions with an appropriate diffusion coefficient and an appropriate concentration are selected, the P-type impurity layer 11, n Type impurity layer 1
2. Two of the three regions of the P-type impurity region 13
It is possible to carry out ion implantation in advance to form one or three ions, and then diffuse them into a predetermined region by performing a single high-temperature heat treatment. For example, if appropriate concentrations of boron ions and arsenic ions are implanted into the n-type substrate 10 and treated at high temperature at the same time, the diffusion coefficient of arsenic ions is smaller than that of boron ions, so that the state shown in FIG. 2b is obtained. can be realized. Although FIG. 2c shows only the main parts related to the present invention, in the actual device, as shown in FIG. 3, it is necessary to form isolation regions 16, vertical CCD channels 15, etc. Since heat treatment may be necessary for formation, such heat treatment may be utilized.

The manufacturing method of the present invention has excellent controllability of the lateral diffusion of the P-type impurity region 13 around the vertical CCD, so that the shallow P-type impurity layer 11 under the photoelectric conversion element 17 can be formed without being narrowed. . Therefore, no deterioration of blooming suppression ability or increase of smear occurs. Further, in the manufacturing method of the present invention, since the n-region constituting the photoelectric conversion element 17 can be formed deeply, the shallow P-type impurity layer 11 underneath is also formed at a deep position from the surface. As a result, a decrease in sensitivity can be suppressed. Furthermore, in the manufacturing method of the present invention, the boundary 18 between the P-type impurity region 13 and the photoelectric conversion element 17 is vertical compared to the conventional example shown in FIG.
Since the CCD channel is formed in 15 directions,
The depletion layer in the vicinity also becomes a vertical CCD channel 15
It spreads in the direction, which makes it easier to collect charges generated in the periphery and reduces smear.

Although the above embodiments have been explained using a CCD type solid-state image sensor, the present invention can also be applied to a MOS type solid-state image sensor, and can further be applied to both one-dimensional and two-dimensional solid-state image sensors. be.

Effects of the Invention As described above, the present invention forms an impurity layer of the opposite conductivity type on a semiconductor substrate of one conductivity type, forms an impurity layer of one conductivity type thereon, and forms an impurity layer of the opposite conductivity type on the semiconductor substrate of one conductivity type. The process of forming an impurity region of the opposite conductivity type in a part of the impurity layer reduces smear without deteriorating the blooming suppression ability even when the unit pixel pitch becomes small, and makes it easy to create a high-sensitivity solid-state imaging device. can be obtained, and its practical effects are great. Furthermore, by forming an impurity layer of opposite conductivity type and an impurity layer of one conductivity type by an epitaxial growth method, an element with higher controllability can be easily realized.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional structural diagram of a conventional P-well structure interline transfer type CCD, FIGS. 2 a to c are diagrams for explaining the device manufacturing process in an embodiment of the present invention, and FIG. 3 is a diagram showing the implementation of the present invention. FIG. 2 is a cross-sectional structural diagram of a P-well structure interline transfer type CCD in an example. 1...Photoelectric conversion element, 2...Transfer electrode, 3...
Vertical transfer channel, 4, 5...P well, 6,
10...n type substrate, 11...p type impurity layer, 12
...N-type impurity layer, 13...P-type impurity region, 1
7...Photoelectric conversion element, 18...P-type impurity region 1
3 and the photoelectric conversion element 17.

Claims (1)

[Claims] 1. After forming a first impurity layer of a conductivity type opposite to the one conductivity type on a semiconductor substrate of one conductivity type, the one conductivity type is formed on the first impurity layer. forming a second impurity layer of the type, and then introducing an impurity of the opposite conductivity type from a part of the surface of the second impurity layer to a depth reaching at least the first impurity layer to form a second impurity layer of the opposite conductivity type. forming a type impurity region, using the second impurity layer into which the opposite conductivity type impurity is not introduced as a photoelectric conversion section, and then forming a charge transfer means in a portion of the impurity region near the photoelectric conversion section; A method for manufacturing a solid-state imaging device, characterized by: 2. The method of manufacturing a solid-state imaging device according to claim 1, wherein the first and second impurity layers are formed by an epitaxial growth method.