JPH0219976B2 - - Google Patents
Info
- Publication number
- JPH0219976B2 JPH0219976B2 JP56185357A JP18535781A JPH0219976B2 JP H0219976 B2 JPH0219976 B2 JP H0219976B2 JP 56185357 A JP56185357 A JP 56185357A JP 18535781 A JP18535781 A JP 18535781A JP H0219976 B2 JPH0219976 B2 JP H0219976B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- patterns
- recognition mark
- substrate
- position recognition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
- H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
- H10W72/07532—Compression bonding, e.g. thermocompression bonding
- H10W72/07533—Ultrasonic bonding, e.g. thermosonic bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/90—Bond pads, in general
- H10W72/931—Shapes of bond pads
- H10W72/932—Plan-view shape, i.e. in top view
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Control Of Position Or Direction (AREA)
- Structure Of Printed Boards (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】
本発明は位置認識方法、特にハイブリツドIC
（集積回路）における半導体素子や部品の搭載あ
るいはワイヤボンデイング等の組立時の位置認識
方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a location recognition method, particularly a hybrid IC.
The present invention relates to a position recognition method during assembly of semiconductor elements and components (integrated circuits), mounting of semiconductor elements and parts, wire bonding, etc.
ハイブリツドICの半導体素子や部品の搭載あ
るいはワイヤボンデイング等の作業を自動で行な
う場合には、その接続箇所を正確に位置認識する
必要がある。 When automatically mounting semiconductor elements and components of a hybrid IC or performing wire bonding, it is necessary to accurately recognize the positions of the connections.
一方、セラミツク基板は白色系のものが多用さ
れている。これは、セラミツク基板が黒色である
と、セラミツク基板表面に形成される抵抗色素が
黒色であることから、抵抗素子の形状、シヨート
有無状況等を外観検査によつて行なう際に充分認
識できないことから、一般には白色系のセラミツ
ク基板が使用されている。 On the other hand, white ceramic substrates are often used. This is because if the ceramic substrate is black, the resistive dye formed on the surface of the ceramic substrate is black, so the shape of the resistive element, the presence or absence of shots, etc. cannot be sufficiently recognized during visual inspection. Generally, a white ceramic substrate is used.
しかし、このように白色系のセラミツク基板を
使用すると、このセラミツク基板の主面に印刷あ
るいは写真製版技術によつて形成した配線層ある
いはコンデンサ、抵抗半導体素子などの電子部品
を搭載する搭載部は銀系の金属であるため、コン
トラストが低く光学的な検出が困難となる。 However, when a white ceramic substrate is used, the wiring layer formed on the main surface of the ceramic substrate by printing or photolithography, or the mounting area on which electronic components such as capacitors and resistor semiconductor elements are mounted, is made of silver. Because it is a metal, its contrast is low and optical detection is difficult.
したがつて、現実にはセラミツク基板のコーナ
ー部から機械的位置出しを行なつて作業を行なつ
ているが、配線層や搭載部の印刷精度はたとえば
±0.05mmと比較的低く、正確な位置認識ができな
い。このため、配線層や搭載部の微細化ができず
高集積化が図れない難点がある。 Therefore, in reality, work is performed by mechanically positioning from the corners of the ceramic substrate, but the printing accuracy of wiring layers and mounting areas is relatively low, for example, ±0.05 mm, and accurate positioning is difficult. I can't recognize it. For this reason, there is a problem in that it is not possible to miniaturize the wiring layer or the mounting portion, and it is difficult to achieve high integration.
したがつて、本発明の目的は精度の高い位置認
識ができる位置認識方法を提供することにある。 Therefore, an object of the present invention is to provide a position recognition method that allows highly accurate position recognition.
また、本発明の他の目的は位置認識精度の向上
を図ることによつて、セラミツク基板上に形成す
る印刷パターンの微細化を図り、ハイブリツド
ICの高集積度化を図ることにある。 Another object of the present invention is to improve the accuracy of position recognition, thereby achieving finer print patterns formed on ceramic substrates, and to improve the accuracy of hybrid printing.
The aim is to increase the degree of integration of ICs.
このような目的を達成するために本発明は、基
板の主面に第１パターンを形成し、その後、第１
パターンを光学的に検出して第１パターンの位置
を認識する方法において、あらかじめ前記基板の
主面に前記第１パターンに対してコントラストが
高い第２パターンを形成しておくとともに、前記
第１パターン形成時に同一マスクによつて前記第
２パターン上に第１パターンを部分的に重ね合せ
て認識マークを設けておき、位置検出時にはこの
認識マークを検出するものである。具体的には、
白色のセラミツク基板主面上に銀系金属で第１パ
ターンを形成する前に、セラミツク基板の主面に
抵抗材料からなる黒色の第２パターンを設けてお
き、第１パターン形成時に第１パターン形成用の
マスクを用いて第２パターン上に第１パターンを
部分的に重ね合せて認識マークを設けておき、位
置認識時にはこの認識マークを検出するものであ
つて、以下実施例により本発明を説明する。 In order to achieve such an object, the present invention forms a first pattern on the main surface of a substrate, and then forms a first pattern on the main surface of a substrate.
In the method of recognizing the position of a first pattern by optically detecting a pattern, a second pattern having a high contrast with respect to the first pattern is formed on the main surface of the substrate in advance, and During formation, a recognition mark is provided by partially overlapping the first pattern on the second pattern using the same mask, and this recognition mark is detected during position detection. in particular,
Before forming the first pattern of silver-based metal on the main surface of the white ceramic substrate, a second black pattern made of a resistive material is provided on the main surface of the ceramic substrate, and when the first pattern is formed, the first pattern is formed. A recognition mark is provided by partially overlapping the first pattern on the second pattern using a mask, and this recognition mark is detected during position recognition.The present invention will be explained below with reference to examples. do.
第１図ａ〜ｃは本発明の一実施例によるハイブ
リツドIC製造における位置認識方法を示す部分
平面図、第２図は同じく認識マーク部分の断面図
である。第１図ａに示すように、セラミツク基板
１の主面上に認識マーク形成用パターン（第２パ
ターン）２を印刷によつて２箇所に設ける。この
認識マーク形成用パターン２は、以後に設ける配
線層や半導体素子等の搭載部等からなる第１パタ
ーン３等を形成しない空領域に設けるものであ
り、認識マークよりも大きく、黒色の抵抗材料
（たとえばRuO2、AgO−PdO等）で形成する。 1A to 1C are partial plan views showing a position recognition method in manufacturing a hybrid IC according to an embodiment of the present invention, and FIG. 2 is a sectional view of a recognition mark portion. As shown in FIG. 1a, recognition mark forming patterns (second patterns) 2 are provided at two locations on the main surface of the ceramic substrate 1 by printing. This recognition mark forming pattern 2 is provided in an empty area where the first pattern 3 consisting of a wiring layer, a mounting part of a semiconductor element, etc. to be provided later is not formed, and is larger than the recognition mark and is made of black resistive material. (for example, RuO 2 , AgO-PdO, etc.).
つぎに、第１図ｂで示すように、セラミツク基
板１上にAg−Pd等からなる導体材料を印刷して
第１パターン３を形成する。この第１パターン３
は半導体素子４を載置する搭載部５およびこの搭
載部５の周囲に先端を臨ませる配線層６を有して
いる。さらに、この第１パターン３には前記第２
パターン２を縁取りするように部分的に重ね合わ
される認識マーク形成枠７を有する。これら、認
識マーク形成枠７、配線層６、搭載部５は同一の
マスクによつて形成する。このような方法によれ
ば、黒色の第２パターン２を白色系の認識マーク
形成枠７で縁取りするため、第２図に示すよう
に、露出する第２パターン部分からなる認識マー
ク８の周縁は周辺に対してコントラストが高くな
り、光学的検出が容易となる。 Next, as shown in FIG. 1b, a first pattern 3 is formed by printing a conductive material such as Ag--Pd on the ceramic substrate 1. As shown in FIG. This first pattern 3
has a mounting portion 5 on which a semiconductor element 4 is placed, and a wiring layer 6 whose tip is exposed around the mounting portion 5. Furthermore, this first pattern 3 has the second pattern
It has a recognition mark forming frame 7 which is partially overlapped so as to frame the pattern 2. These recognition mark forming frame 7, wiring layer 6, and mounting portion 5 are formed using the same mask. According to such a method, since the black second pattern 2 is framed by the white recognition mark forming frame 7, the periphery of the recognition mark 8 consisting of the exposed second pattern portion is as shown in FIG. The contrast with respect to the surroundings is increased, making optical detection easier.
そこで、半導体素子４の取り付け時には、この
黒色の認識マーク８を自動的に光学的方法で検出
して搭載部５を正確に認識し、搭載部５に固定す
る。また、ワイヤボンデイング時には、２つの認
識マーク８および半導体素子４の電極９を検出し
て、半導体素子４と配線層６との位置関係を認識
し、自動的に半導体素子４の各電極９とこれに対
応する配線層部分とをアルミニウムのワイヤ１０
で超音波ボンデイング方法によつて接続する。 Therefore, when mounting the semiconductor element 4, the black recognition mark 8 is automatically detected by an optical method to accurately recognize the mounting portion 5, and the semiconductor element 4 is fixed to the mounting portion 5. In addition, during wire bonding, the two recognition marks 8 and the electrodes 9 of the semiconductor element 4 are detected, the positional relationship between the semiconductor element 4 and the wiring layer 6 is recognized, and each electrode 9 of the semiconductor element 4 and this and the wiring layer portion corresponding to the aluminum wire 10.
Connected by ultrasonic bonding method.
このような実施例によれば、認識マーク８の区
画（認識マーク形成枠７）は配線層６および搭載
部５を形成する際、同一のマスクによつて同時に
形成される。したがつて、同一マスクであるため
に認識マーク８と配線層６および搭載部５との相
対的な位置ズレは全くなく、位置精度は略マスク
加工精度によつて決まる。マスクの加工精度は高
く、このため、認識マーク８と配線層６および搭
載部５との位置精度は数μｍ程度にすることがで
きる。 According to this embodiment, the divisions of the recognition mark 8 (recognition mark forming frame 7) are formed simultaneously using the same mask when forming the wiring layer 6 and the mounting portion 5. Therefore, since they are the same mask, there is no relative positional deviation between the recognition mark 8, the wiring layer 6, and the mounting portion 5, and the positional accuracy is determined approximately by the mask processing accuracy. The processing accuracy of the mask is high, and therefore the positional accuracy between the recognition mark 8, the wiring layer 6, and the mounting portion 5 can be on the order of several μm.
一方、認識マーク８はその周縁が周辺の白色に
対して高いコントラストを有する黒であることか
ら、明確となり、自動位置検出精度も高くなる。
このため、搭載部５や配線層６あるいは電極９の
中央に被接続物である半導体素子４やワイヤ１０
を接続することが可能となり、配線層６および搭
載部５の印刷位置精度の良否には関係なくなる。
したがつて、配線層６の幅や搭載部５の大きさを
小さくすることができ、パターンの微細化、すな
わち集積回路の高密度化（高集積度化）も可能と
なる。 On the other hand, since the peripheral edge of the recognition mark 8 is black with high contrast to the surrounding white, it is clear and the automatic position detection accuracy is also high.
Therefore, the semiconductor element 4 and the wire 10, which are the objects to be connected, are placed in the center of the mounting portion 5, the wiring layer 6, or the electrode 9.
This makes it possible to connect the wiring layer 6 and the mounting portion 5 regardless of whether the printing position accuracy is good or not.
Therefore, the width of the wiring layer 6 and the size of the mounting portion 5 can be reduced, and it is also possible to miniaturize the pattern, that is, to increase the density of the integrated circuit (high integration degree).
なお、本発明は前記実施例に限定されない。す
なわち、認識マークは黒色系領域を白色系導体層
で縁取りして、認識マークの外周縁を位置検出の
対象としたが、黒色系領域の中央に白色系導体層
を部分的に印刷して、認識マークの内周縁を位置
検出の対象としてもよい。ただし、この場合に
は、黒色系領域の外周縁の光学的検出を位置検出
情報としないような制御系での操作が必要とな
る。 Note that the present invention is not limited to the above embodiments. That is, the recognition mark has a black area bordered by a white conductor layer, and the outer edge of the recognition mark is the object of position detection, but by partially printing a white conductor layer in the center of the black area, The inner periphery of the recognition mark may be the object of position detection. However, in this case, it is necessary to operate the control system so that optical detection of the outer periphery of the blackish area is not used as position detection information.
以上のように、本発明によれば、位置認識精度
の向上を図ることができるので、セラミツク基板
上に形成する印刷パターンの微細化が図れる。こ
の結果、ハイブリツドICの小型化あるいは高集
積度化が図れる。 As described above, according to the present invention, it is possible to improve the accuracy of position recognition, so that it is possible to miniaturize the printed pattern formed on the ceramic substrate. As a result, the hybrid IC can be made smaller or more highly integrated.
第１図ａ〜ｃは本発明の一実施例によるハイブ
リツドIC製造における位置認識方法を示す部分
平面図、第２図は同じく認識マーク部分の断面図
である。
１……セラミツク基板、２……第２パターン、
３……第１パターン、４……半導体素子、５……
搭載部、６……配線層、７……認識マーク形成
枠、８……認識マーク、９……電極、１０……ワ
イヤ。
1A to 1C are partial plan views showing a position recognition method in manufacturing a hybrid IC according to an embodiment of the present invention, and FIG. 2 is a sectional view of a recognition mark portion. 1... Ceramic substrate, 2... Second pattern,
3...First pattern, 4...Semiconductor element, 5...
Mounting section, 6... Wiring layer, 7... Recognition mark forming frame, 8... Recognition mark, 9... Electrode, 10... Wire.
Claims (1)
ーン及び他の所望パターンを形成し、その後前記
第１パターンを光学的に検出して第１パターンと
所望パターンとの相対位置関係を認識し処理する
方法であつて、あらかじめ前記基板の主面の一部
に前記それぞれの第１パターンに対してコントラ
ストが高い第２パターンを複数形成し、しかる
後、第１パターン及び他の所望パターン形成のた
めの一つのマスクを用いて前記それぞれの第２パ
ターン上一部に第１パターンを重ね合わせて形成
することにより位置認識用のマークを設け、その
マークを光学的検出することにより位置認識する
ことを特徴とするハイブリツドICを得るための
位置認識方法。 ２ 前記基板は白色系セラミツク基板より成り、
第１パターン及び他の所望パターンはAg−Pd系
導体材料より成り、そして第２パターンはRuO2
またはAgO−PdOから選択された一つの材料よ
り成ることを特徴とする特許請求の範囲第１項記
載のハイブリツドICを得るための位置認識方法。[Scope of Claims] 1. A plurality of first patterns for position recognition and other desired patterns are formed on the main surface of a substrate, and then the first patterns are optically detected to distinguish between the first pattern and the desired pattern. A method of recognizing and processing the relative positional relationship of the substrate, wherein a plurality of second patterns having a high contrast with respect to each of the first patterns are formed on a part of the main surface of the substrate in advance, and then the first pattern A mark for position recognition is provided by overlapping and forming a first pattern on a portion of each of the second patterns using one mask for forming another desired pattern, and the mark is optically detected. A position recognition method for obtaining a hybrid IC characterized by position recognition by 2. The substrate is made of a white ceramic substrate,
The first pattern and other desired patterns are made of Ag-Pd based conductive material, and the second pattern is made of RuO 2
A position recognition method for obtaining a hybrid IC according to claim 1, characterized in that the hybrid IC is made of one material selected from AgO-PdO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185357A JPS5887838A (en) | 1981-11-20 | 1981-11-20 | Recognition of position |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56185357A JPS5887838A (en) | 1981-11-20 | 1981-11-20 | Recognition of position |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5887838A JPS5887838A (en) | 1983-05-25 |
| JPH0219976B2 true JPH0219976B2 (en) | 1990-05-07 |
Family
ID=16169367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56185357A Granted JPS5887838A (en) | 1981-11-20 | 1981-11-20 | Recognition of position |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5887838A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0770551B2 (en) * | 1986-02-20 | 1995-07-31 | ロ−ム株式会社 | Method for confirming die bonding position of semiconductor chip |
| JPS63155733A (en) * | 1986-12-19 | 1988-06-28 | Fujitsu General Ltd | Method for charging semiconductor chip |
| JP2512827B2 (en) * | 1990-08-31 | 1996-07-03 | 松下電器産業株式会社 | Printed circuit board manufacturing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56146242A (en) * | 1980-04-16 | 1981-11-13 | Hitachi Ltd | Positioning method of bonding position at fixed position on substrate |
-
1981
- 1981-11-20 JP JP56185357A patent/JPS5887838A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5887838A (en) | 1983-05-25 |
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