JPH0220034B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile encoding circuit, and in particular, to an encoding circuit for a facsimile device that performs two-dimensional encoding of image information using the MR (Modified Read) method, etc. It has a line memory equivalent to a line, and by loading the address value of the line memory for writing the encoded line into the address counter of the line memory for reading the reference line, it is possible to speed up the detection of changing points on the reference line. The present invention relates to a two-dimensional encoding circuit capable of high-speed operation.

Conventionally, two-dimensional encoding circuits aimed at high-speed operation as mentioned above have generally been configured in hardware, and even if high-speed operation can be achieved, power consumption and heat dissipation will suffer due to increased implementation scale. The circuit itself has drawbacks such as low versatility. Such problems can be addressed by using firmware based on a microprocessor, but the processing speed is slow and the original purpose cannot be achieved.

The present invention focuses on the above technology, and by using an ultra-high-speed microprogram sequencer for most of the encoding process, it can significantly improve the drawbacks of the encoding circuit with the above-mentioned hardware configuration and enable high-speed processing. This realizes a highly efficient encoding circuit.

FIG. 1 shows the block configuration of a high-speed encoding circuit with a conventional hardware configuration based on the MR (Modified Read) method.

Reference numeral 11 in FIG. 1 represents a memory device or CCD scanner that can be controlled by the readout clock of the encoder. Line memories 12 and 13 store information for one scanning line. These are control signals (R/W) from the mode control circuit 31 to the selector 1.
7, selector 18, selector 19, selector 20
Read Address Counter (RAC) 2
1 and the write address counter (WAC) 22, the image information of the encoded line is inputted to one side, and the image information of the reference line is read out from the other side. Reference numeral 14 denotes a change point detection circuit for a coding line (current line) that receives image information from the memory or scanner 11 pixel by pixel and determines whether the color is different from the color of the previous pixel. .
Also, 15 is line memory 12 or line memory 1
Selector 1 selects the image information of the reference line stored in 3.
This is a reference line change point detection circuit that receives the information through the reference line 8 and detects the change point of pixels in the image information. 16 is an inversion gate that inverts the address value of the read address counter 21; 24 is the read clock of the memory or scanner 11 when detecting a change point in the encoded line or when reading out the number of effective pixels on the same line is completed (at the end of one scan); Forbidden AND
Gate 26 indicates an OR gate that inhibits the operation of the read address counter 21 when detecting a change point on the reference line or when reading out the number of effective pixels on the reference line is completed. 23 is an adder for calculating the difference between the address value of the write address counter 22 and the inverted value of the address value of the read address counter 21, and the output of the adder 23 is input to the comparator 27, The device 27 judges whether the output value of the adder 23 is 4 or more, 1 or more, 0, -1 or less, or -4 or less, and the judgment result is used for mode control. It is output to the circuit 31. 28 is a selector for switching between the address value of the read address counter 21 and the address value of the write address counter 22; 29;
3 shows an address latch for calculating a relative address value, 30 an inverter, and 32 an adder for calculating a relative address value.

31 determines the vertical, horizontal, and pass modes and EOL of the MR (Modified Read) encoding method from the relative address value, and the code transmission control circuit 3
This is a mode control circuit that generates various control signals in order to make an encoding request to 3. Reference numeral 38 indicates a circuit for detecting the end of a valid reference line from a read address value, and reference numeral 39 indicates a circuit for detecting an end of a valid encoding line from a write address value.
34 is the encoding mode 2 bits (representing pass mode, vertical mode, horizontal mode, and EOL) output from the mode control circuit 31, the relative address 4 bits in vertical mode, and the upper 6 bits of the relative address in horizontal mode.
and a selector that switches the lower 6 bits of the three types of signals according to the 2-bit signal (run length (RL)/encoding mode, make-up/termination (M/T) during run length) output from the code transmission control circuit 33. It is. 35 is the mode code (V,
H, P, EOL), a ROM that generates a run-length code and each code length, and 36 a shift register that performs parallel-to-serial conversion of the code assigned by the ROM 35. A counter 37 measures the code length of the variable length code allocated by the ROM 35, and notifies the code sending control circuit 33 that the shift register 36 has completed sending out serial data. 33 is mode code (V, P, H), EOL
This is a code sending control circuit that generates various control pulses for sending codes and run-length codes.

As shown in FIG. 2, the operation flow of the mode control circuit 31 in the block diagram of FIG. 1 is as follows: At the beginning of one line, the addresses of the read address counter 21 and write address counter 22 are set to 0, A white pixel is set as a reference pixel in the encoding line change point detection circuit 14 and the reference line change point detection circuit 15. Next, to the code sending control circuit 33
It issues a mode signal indicating EOL, turns the code sending request “ON”, and waits for the code sending response signal to turn “ON”. When this signal turns "ON", the encoded line change point request signal and the reference line change point request signal are turned "ON", the write address counter 22 and the read address counter 21 are operated, and image information is read out from the memory 11. When a change point on the encoded line is detected, the encoded line change point detection circuit 14 turns the detection signal “ON” and notifies the mode control circuit 31, and also controls the operation of the write address counter 22 and the memory 11. Cancel reading. Similarly, when the reference line change point detection circuit 15 detects a change point, it turns the detection signal "ON", notifies the mode control circuit 31, and stops the operation of the read address counter 21. Here, if one line ends before the changing point is detected, it is assumed that the changing point has been detected at that point and the process moves to the next operation.

The mode control circuit 31 checks the output signal of the comparator 27 at the time when the two change point detection signals of the encoded line and the reference line are both in the "ON" state, and (1) if it is larger than +3 (second a When the reference line change point request signal is turned “ON” and the reference line change point detection signal is turned “ON”, the output signal of the comparator 27 is further checked, and (a) the output of the comparison circuit 27 is is larger than 0 (state shown in Figure 2a), it is determined to be pass mode, and the code transmission control circuit 3
3, outputs a signal indicating the pass mode, outputs a code sending request signal, and waits for the code sending response from the code sending control circuit 33 to turn "ON". When the code sending response becomes “ON”, selector 2 is activated in preparation for the next encoding.
8 is read out, switched to the address side, and the read address value is latched in the latch circuit 29. Here, the mode control circuit 31 turns the reference line change point request signal "ON" and returns to the state shown in FIG. 2a.

(b) When the output signal of the comparator circuit 27 is 0 or less (the state shown in Figure 2a), it is determined that the mode is horizontal, the code sending request signal is turned “ON”, and the code sending response from the code sending control circuit 33 is “ON”. ” Wait for it to become. The code sending control circuit 33 turns the code sending response "ON" when sending the horizontal mode code and loading data of the _{0 to 1} run length code is completed. Upon receiving this, the mode control circuit 31 selects the write address using the selector 28 and latches it in the address latch 29. Next, turn the encoding line change point request signal “ON”
Then, the read/write address counter 22 of the memory 11 is operated, and it waits for the change point detection signal from the encoded line change point detection circuit 14 to turn "ON". When this signal turns "ON", the mode control circuit 31 turns a code sending request signal "ON" to the code sending control circuit 33, requesting encoding of the run lengths a ₁ and a ₂ . When the code sending response signal turns "ON", the write address is latched in the address latch 29 in preparation for the next encoding, and the state shifts to the state shown in FIG. 2a.

Next, the mode control circuit 31
Check the output signal of (a) If it is less than 0 (state in Figure 2a), move to the state in Figure 2a.

(b) When larger than 0 (state in FIG. 2a) At the same time as loading the value of the write address counter 22 into the read address counter 21, the reference line change point detection circuit 15
The reference color is loaded from the encoded line change point detection circuit 14, preparations are made to detect the change point of the reference line, and the state shifts to the state of FIG. 2a.

Here, the read address counter 21
By loading the address value of the write address 22 into , the processing time is greatly reduced.

(2) When the output signal of the comparator circuit 27 is 3 or less and -3 or more (state in Fig. 2a), it is determined that the mode is vertical mode, and the mode control circuit 31
sends a vertical mode signal to the code sending control circuit 33, turns on the code sending request signal, and waits for a response. When the code sending response signal becomes "ON", the selector 28 selects the write address counter 22 in preparation for the next encoding, latches it in the address latch 29, and shifts to the state of FIG. 2a.

(3) When the output signal of the comparison circuit 27 is smaller than -3 (state in Fig. 2a), the mode control circuit 31 determines that it is the horizontal mode, sends a horizontal mode signal to the code sending control circuit 33, and sends the code The transmission request signal is turned "ON" and a response from the code transmission control circuit 33 is awaited. When the code sending control circuit 33 completes sending the horizontal mode code and loading data of the a ₀ a ₁ run length code, it turns the code sending response signal "ON". When this is received, the write address is selected by the selector 28 and latched into the address latch 29 in preparation for the next encoding. Next, turn the encoding line change point request signal “ON” and the memory 11
Starts the operation of the read and write address counters and waits for the encoded line change point detection signal to turn "ON". When this signal turns “ON”, the mode control circuit 31 turns the code sending request signal “ON” to the code sending control circuit 33, and causes the code sending control circuit 33 to encode the run length of a ₁ a ₂ . request and wait for the code transmission response signal from the same circuit to turn “ON”. When the code sending response signal turns "ON", the write address is latched into the address latch 29 in preparation for the next encoding (state in FIG. 2a).
(b) If it is larger than 0, load the address value of the write address counter 22 into the read address counter 21 and at the same time load the address value of the reference line change point detection circuit 1.
5, the reference color is loaded from the encoded line change point detection circuit 14, and the state shifts to the state of FIG. 2a in preparation for detection of the next change point on the reference line.

(b) When the value is 0 or less: Turn the encoded line change point request signal “ON” and proceed to Figure 2a.

The two-dimensional encoding circuit described above has a high processing speed, and in the past, its characteristics could not be utilized unless the circuit was constructed using hardware. On the other hand, when a circuit is constructed using hardware, problems such as power consumption and heat dissipation measures arise due to an increase in the scale of implementation, and the circuit itself has drawbacks such as low versatility.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the prior art, and an object of the present invention is to perform most of the encoding process by using an ultra-high-speed microprogram sequencer.
A new encoding circuit that can reduce the implementation scale without sacrificing the high-speed performance of the high-speed processing two-dimensional encoding circuit mentioned above, consumes less power, has easy heat dissipation measures, and is highly versatile has been incorporated into the firmware. The goal is to realize it.

In order to achieve the above object, an encoding circuit according to the present invention provides a circuit for two-dimensionally encoding image information using a modified read method, etc., in which a scanning image signal is output in response to an image signal readout request signal for each pixel. an image information source that can output one pixel at a time, a line memory that can write one line of image information, and an image signal from the image information source selectively stored in either of the two line memories. an input signal selector for switching to write, a read address counter selectively connected to one of the two line memories, a write address counter connected to the other line memory, and the read address counter and the write address counter. an address selector that can be connected to switch the output of the line memory to the two line memories, a current line change point detection circuit that detects a change point of output pixels from the image information source, and a current line change point detection circuit that is connected to the read address counter. A reference line change point detection circuit detects the change point of the output pixel of the line memory, and the change point detection signals from the two change point detection circuits and the address values of the read address counter and the write address counter are inputted in advance. The encoding control circuit includes a storage means for storing predetermined processing and an arithmetic processing circuit that operates according to the processing procedure stored in the storage means, and the encoding control circuit Each time both of the two change point detection signals are activated, the difference between the read address counter value and the write address counter value is calculated, and a code to be sent is determined and sent based on the calculation result. It is said that

Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

An embodiment of the present invention is shown in FIG. As can be seen from FIG. 3, the portion surrounded by the broken line in FIG. 1 is comprised of a microprogram system that operates at high speed.

This microprogram system is broadly divided into a microinstruction control section and a data manipulation section. The microinstruction control unit is composed of a sequencer 42 and a microprogram ROM 43 in FIG. 3, and controls the microinstruction to be executed in the next cycle. The sequencer 42 is
Controlled by microinstructions stored in 44 pipeline registers, 4
Controls the address of the microprogram ROM in step 3. The microprogram ROM 43 is a memory that stores a sequence of microinstructions, and the microinstructions read from the microprogram ROM 43 under the control of the sequencer 42 are read out at the next rising edge of the clock signal. It is written to the next pipeline register 44 and executed. With such a pipeline register configuration, the fetch cycle and execution cycle of a microinstruction can be executed simultaneously, thereby speeding up system operation.

The data manipulation unit (operation unit) 45 is controlled by microinstructions and address signals stored in the pipeline register 44.
The data transferred through the data bus and data register is stored in an internal register, arithmetic processing is performed, and the result is output.

51 is a latch circuit for each signal of encoding line change point detection, reference line change point detection, reference line end, encoding line end, and code sending response;
The sequencer 42 always monitors these signals when it is not performing data arithmetic processing through the selectors 40, and when it finds a signal, it reads the starting address of the microprogram ROM 43 in which the sequence for that signal is stored within one clock. Outputs the address and begins executing the sequence. 52
is a latch circuit for a flag from the data manipulation unit 45, which the sequencer 42 monitors through the selector 41 during data manipulation, and performs sequence control in accordance with the flag. 46 is
An input port 47 inputs the address value of the read address counter 21 into the CPU when a change point of the reference line is detected, and inputs the address value of the write address counter 22 when a change point of the encoded line is detected. The input ports for input to the CPU are shown.

48 is an output port for outputting the calculation result, code sending request, black pixel or white pixel mode (EOL signal, vertical mode, horizontal mode, pass mode) to the code sending control circuit 33, and 49 is a run length selector. Output port for outputting to 34,
50 is an output port for an encoding line change point request, a reference line change point request, a read/write selection signal to the selectors 17, 18, 19, and 20, a clear signal to the read/write address counter, and an address load signal of the reference line address counter, respectively. show.

The microprogram sequencer (sequencer 42, microprogram
As shown in FIG. 4, the operation flow of the ROM 43, pipeline register 44, and arithmetic unit 45 is as shown in FIG. A white pixel is set as a reference pixel in the conversion line change point detection circuit 14 and the reference line change point detection circuit 15. Next, the mode signal indicating EOL and the code sending request are turned "ON" from the output port 48 to the code sending control circuit 33, and it waits for the code sending response signal to be turned "ON". When this signal turns "ON", the encoded line change point request signal and the reference line change point request signal are turned "ON", the write address counter 22 and the read address counter 21 are operated, and image information is read from the memory 11. When a change point on the encoded line is detected, the encoded line change point detection circuit 14
turns the detection signal “ON” and stops the operation of the write address counter 22 and the readout of the memory 11. Similarly, when the reference line change point detection circuit 15 detects a change point, it turns the detection signal "ON" and stops the operation of the read address counter 21. Here, if one line ends before the changing point is detected, it is assumed that the changing point has been detected at that point and the process moves to the next operation.

The micro program sequencer is selector 4.
0, the latch 51 is monitored, and the two change point detection signals of the encoded line and reference line are “ON”.
When it is found that the output port 50 has changed, the encoded line change point request and the reference line change point request are turned OFF, and the read address counter 21 value (b ₁ ) and the write address are read from the input ports 46 and 47. Take in the value (a ₁ ) of the counter 22, calculate the relative address a ₁ - b ₁ with the arithmetic unit 45, and (1) If it is greater than +3 (state in Figure 4a), turn the reference line change point request signal “ON”. When the change point detection signal of the reference line becomes "ON", the address value (b ₂ ) is taken into the arithmetic unit 45 from the input port 46, and the relative address a ₁
Looking at the arithmetic unit output of -b ₂ , (a) When a ₁ -b ₂ > 0 (state in Figure 4a), it is determined to be pass mode, and the encoding control circuit 33
It outputs a signal representing the pass mode and a code transmission request signal from the output port 48, and waits for the code transmission response from the code transmission control circuit 33 to turn "ON". When the signal becomes “ON”, the read address counter 21
The value of _a0 is stored in the register in the arithmetic unit, and the microprogram sequencer turns the reference line change point request signal "ON" and outputs it from the output port 50, returning to the state of FIG. 4a.

(b) When a ₁ - b ₂ ≦0 (state shown in Figure 4a) It is determined that the mode is horizontal, and the code transmission control circuit 3
3 outputs a signal indicating the horizontal mode and a code transmission request signal from the output port 48, and
A signal representing the run length of a ₀ a ₁ (i.e. a ₁ −
The result of calculating a ₀ by the calculating unit 45) is output from the output port 49 to the selector 34. Note 1
At the beginning of the line, the register in the arithmetic unit 45 is initialized with a ₀ =0. When the encoding control circuit 33 completes sending out the horizontal mode code and sending out the code corresponding to the run length of _{0 to 1} , it turns on the code sending response. Upon receiving this, the microprogram sequencer selects the write address with the selector 19, stores the address value of _a1 from the input port 47 into the register in the arithmetic unit 45, and turns the encoding line change point request signal "ON". and monitor the change point detection signal turning “ON”. When this signal turns “ON”, the microprogram sequencer inputs the value _a2 of the write address counter 22 at that time to the input port 47.
The calculation unit 45 calculates a run length of _{2 1} , outputs a code transmission request signal to the code transmission control circuit 33 from the output port 48, and outputs a signal representing the _{2 1} run length code from the output port 49. It outputs it to the selector 34 and waits for the code sending response to become "ON". When the code sending response becomes “ON”, the 4th a
The state shifts to the state shown in the figure, and the arithmetic unit 45 calculates the value of a ₂ -b _1. If the value is (a) less than or equal to 0 (state in FIG. 4a), the state shifts to the state in FIG. 4a.

(b) When larger than 0 (state in Figure 4a) Write the value of the address counter 22 to the read address counter 21 and output the reference address load from the output port 50,
At the same time, the reference line change point detection circuit 15 and the encoded line change point detection circuit 14
A reference color is loaded from the output port 50 to prepare for detecting a change point, and the state shifts to the state of FIG. 2a.

(2) When the output signal of the arithmetic unit 45 is 3 or less and -3 or more (state in FIG. 4a), the vertical mode is determined, and the microprogram sequencer tells the code sending control circuit 33 to
The vertical mode signal is outputted from the output port 48, and the vertical mode run length is outputted from the output port 49 to the code sending control circuit 33 and the selector 34, respectively, and the code sending request signal is turned "ON" to wait for a response. When the response becomes "ON", in preparation for the next encoding, a ₁ is defined in the arithmetic unit 45 as a ₀ at the time of the next encoding and stored in the register, and the state shifts to the state shown in FIG. 4a.

(3) When the output signal of the arithmetic unit 45 is smaller than -3 (state in FIG. 4a), the microprogram sequencer determines that it is in the horizontal mode, and sends the horizontal mode signal and code from the output port 48 to the code sending control circuit 33. Turn the sending signal “ON” and output it to output port 4.
9 outputs a run length of ₀ to ₁ to the selector 34, and monitors until the code sending response signal turns "ON". When the microprogram sequencer finds the same signal, it stores the address value of a ₁ in the register in the arithmetic unit 45, turns on the encoding line change point request signal, outputs it from the output port 50, and stores the address value of a 1 in the memory 11. The operation of the read/write address counter 22 is started, and it is monitored that the encoded line change point detection signal becomes "ON". When the microprogram sequencer detects that this signal is turned "ON," it stops the write address counter 22, takes in the address value _a2 from the input port 47, and calculates the run length _{of 21} using the arithmetic unit 45. , outputs the result from the output port 49, and simultaneously turns on the code sending request and monitors until the code sending response turns on. The same signal is “ON”
When it is found that , a ₂ - b ₁ is calculated by the arithmetic unit 45, and the result is (a) If it is larger than 0 (state in Figure 4a), the address value of the write address counter 22 is written to the read address counter 21. At the same time, the reference line change point detection circuit 1
5. Load the reference color into the encoded line change point detection circuit 14, and shift to the state of FIG. 4a in preparation for detection of the next change point on the reference line.

(b) When the value is 0 or less (state in Figure 4a), turn the encoding line change point request signal “ON”
The signal is then output from the output port 50 and the process moves to FIG. 2a.

The present invention is constructed and operates as described above.According to the present invention, by using a microprogram processor for the control portion of the encoding process, the amount of hardware can be reduced. This makes it advantageous in terms of implementation problems and costs. In addition, by configuring the change point detection circuit with hardware and adopting a configuration that allows the address value of the encoded line address counter to be directly loaded into the reference line address counter, the change point detection process can be speeded up. has had a great effect on Furthermore, in the configuration of the encoding processor, various states of the change point detection process are received as input signals, and necessary processing is executed in the next clock according to the signals, and the address value of the write address counter and the read address counter are By making it possible to directly input the address value to the arithmetic unit, it was possible to construct an encoding circuit that is much faster than a conventional encoding circuit using a microprocessor.

Although the present invention has been described above with reference to one preferred embodiment thereof, this is merely an example, and the present invention is not limited only to the embodiment described herein, and all within the scope thereof. Of course, it includes modifications and changes.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of a conventional circuit, Figure 2 is a block diagram showing an example of a conventional circuit.
Figures a to 2c are diagrams showing the operation flow of the conventional circuit shown in Figure 1, Figure 3 is a block configuration diagram showing an embodiment of the present invention, and Figures 4a to 4c are diagrams showing the operation flow of the conventional circuit shown in Figure 1.
3 is an operation flowchart of the microprogram sequencer according to the present invention shown in the figure. 11...Memory, 12, 13...Line memory, 14...Encoding line change point detection circuit, 15
... Reference line change point detection circuit, 16 ... Inverter, 17, 18, 19, 20, 28, 34, 4
0, 41... Selector, 21... Read address counter, 22... Write address counter, 23, 32... Adder, 24... AND gate, 25, 26... OR gate, 27... Comparator, 29 ... Address latch, 30 ... Inverter,
31...Mode control circuit, 33...Code transmission control circuit, 35...ROM, 36...Shift register, 37...Counter, 38...Reference line end detector, 39...Encoding line end detector, 42
...Sequencer, 43...Microprogram
ROM, 44...Pipeline register, 45...
...Arithmetic unit, 46, 47...Input port, 48, 4
9, 50...output port, 51, 52...latch circuit.

Claims (1)

[Scope of Claims] 1. In a circuit that two-dimensionally encodes image information using a modified read method, etc., a pixel capable of outputting a scanning image signal pixel by pixel in response to a pixel-by-pixel image signal readout request signal. An information source, two line memories into which one line of image information can be written,
an input signal selector for switching to selectively write an image signal from the image information source into either of the two line memories; and a write address counter selectively connected to one of the two line memories. , is selectively connected to the other line memory, and loads the value of the write address counter by an address load signal by connecting a preset value input terminal to the output of the write address counter corresponding to the bit order of the address. an address selector capable of switching and connecting the outputs of the read address counter and the write address counter to the two line memories; A current line change point detection circuit that detects a change point, a reference line change point detection circuit that detects a change point of an output pixel of the line memory connected to the read address counter, and an instruction that specifies a process to be executed. Microprogram ROM that stores
a pipeline register that stores the output of the microprogram ROM every cycle; and a sequencer that is controlled by the output of the register and outputs the address of a processing instruction to be executed in the next cycle to the microprogram ROM. a selector that receives the change point detection signal as an input, and the selector selects one from a plurality of inputs according to the instruction stored in the pipeline register and outputs a condition signal to the sequencer. The sequencer includes an encoding control circuit comprising a microprogram system that determines the next address to the microprogram ROM according to the condition signal, and the encoding control circuit receives both of the two change point detection signals. 1. A facsimile encoding circuit characterized in that each time a facsimile is activated, the difference between the value of the read address counter and the value of the write address counter is calculated, and a code to be sent is determined and sent based on the calculation result. 2. The encoding control circuit is activated by the two change point detection signals, and as a result of an operation for calculating the difference between the address value of the read address counter and the address value of the write address counter, the write address is determined. Claim 1, further characterized in that the address load signal is output when the value of the counter is larger than the value of the read address counter, and the address value of the write address counter is loaded into the read address counter. The facsimile encoding circuit according to item 1.