JPH0221196B2 - - Google Patents

Description

Detailed Description of the Invention "Field of Industrial Application" This invention relates to a method for refreshing reproduced images in order to prevent the spread of image quality deterioration caused by transmission path code errors in the interframe coding method of television signals. This relates to a periodic refresh method.

``Prior art'' The television signal transmission system sends 30 frames per second, and the time difference between two consecutive frames is only 33 milliseconds.
There is little change in the image between these frames. Particularly in the case of a television signal showing a conference scene, two consecutive frames of images often look very similar because the movements of conference participants are small.

The interframe coding method utilizes the correlation between frames to increase efficiency by transmitting only information about the area in which the subject is moving, and usually uses the difference signal between two consecutive frames to transmit The signal is quantized and encoded and transmitted, and the receiving side reproduces the television signal by accumulating the received interframe difference values. Therefore, if a transmission line code error occurs, the interframe difference value transmitted on the transmitting side and the interframe difference value received on the receiving side will differ, making it impossible for the receiving side to reproduce the correct television signal. It disappears. The influence of such a transmission path code error propagates until the cumulative value is reset (refreshed) to the same value between transmitting and receiving.
A periodic refresh method is a method for removing the influence of transmission line code errors.

In this periodic refresh method, the television screen is divided into multiple blocks each consisting of m lines x n pixels as shown in Fig. 1, and each frame is divided into p=k x l blocks per frame. Less impact of image quality deterioration due to transmission line code errors than inter-coding method
Perform PCM encoding or intraframe encoding,
A method has been proposed in which the positions of the p blocks are sequentially shifted to refresh a plurality of frames or the entire screen. In this type of system, it is necessary to synchronize the position of the block to be refreshed between the transmitting and receiving sections, and it is conceivable to transmit block address information for this purpose, but in this case, the code is divided by the amount of the address information. The disadvantage was that the conversion efficiency was reduced.

``Means for Solving the Problems'' According to the present invention, in an interframe coding transmission system for television signals, one screen of the television signal is divided into a plurality of (p) blocks of m lines x n pixels. Then, the block address generating means sequentially generates address signals of the separated blocks at a rate of q blocks (q<p) for each frame, and transmits the block specified by the block address signal as refresh information. A block address generating means is also provided on the receiving side, and the refresh information received for the block specified by the address signal of the block address generating means is decoded to refresh the corresponding part of the frame memory on the receiving side. Block address generation means generates a predetermined number of blocks,
For example, every time a full block address signal is generated, it is transmitted as synchronization information to cause both the block address generation means on the transmitting side and the receiving side to operate synchronously.

In this way, it is not necessary to transmit information indicating the address of the block for each block, and more bits can be used for transmitting the television signal.

"Embodiment" Sending side FIG. 2 shows an embodiment of the present invention. A television signal input from a television signal input terminal 1 is band-limited in a low pass filter (LPF) 2 and then supplied to an AD conversion circuit 3 and a sync separation circuit 4. The synchronization separation circuit 4 separates the horizontal synchronization signal according to the encoding method, and the clock generation circuit 5 generates various clocks necessary for encoding that are phase-synchronized with this horizontal synchronization signal. are supplied to the respective circuits. Clock generation circuit 5 also generates multiplex control signals necessary for controlling multiplex circuit 6.
In the AD conversion circuit 3, an analog television signal is sampled, and each sample value is converted into a PCM signal of 8 bits per pixel. This PCM
The output value of the switching circuit 8 is subtracted from the signal in a subtraction circuit 7, and the difference value is quantized in a quantization circuit 9 based on a predetermined quantization characteristic. The quantized output is added to the output of the switching circuit 8 in an adder circuit 11 to obtain a locally decoded signal.

This locally decoded signal is stored in the frame memory 12 and used as a predicted signal in subsequent encoding. The frame memory 12 delays the input signal by one frame period and supplies it to the switching circuit 8, resulting in interframe signal conversion.

In this invention, the periodic refresh control circuit 13
is provided and generates a control signal to periodically refresh one block at a time consisting of m lines x n pixels, for example, one block at a time for each frame. In this example, a one-pixel memory 14 is provided which delays the input signal by one sample period when the refresh is transmitted after being inter-frame encoded. The periodic refresh control circuit 13 operates in response to the clock from the clock generator 5, and when one block is being refreshed, the switching circuit 8 is switched to the frame memory for each line of that block for the n pixels. 12 to the output side of the 1-pixel memory 14. The output side of the adder circuit 11 is also connected to the input side of the 1-pixel memory 14, so that during the refresh period, the prediction code composed of the subtracter circuit 7, the quantizer circuit 9, the adder circuit 11, and the 1-pixel memory 14 is used. Intra-frame previous value DPCM encoding is performed by the encoding loop.

As will be explained later, a periodic refresh control circuit is also provided on the reception side, and in order to synchronize the periodic refresh control circuit on the reception side with the periodic refresh control circuit 13 on the transmission side, one block is refreshed. Each time, the built-in block address counter is incremented by one step, and when all blocks, that is, p blocks, are refreshed, this block address counter is reset, and this block address counter reset information is sent to the multiplexing circuit 6 as synchronization information. do.

The quantization circuit 9 supplies a code representing the quantization level to the variable length encoding circuit 15. In the variable length encoding circuit 15, when the quantized output of all pixels in a block consisting of m lines x n pixels shown in Fig. 1 is zero, this block is regarded as an invalid block and only 1 bit of invalid block information is output. Then, the other blocks are treated as valid blocks, and for the valid block, following one bit of valid block information, the quantization level of all pixels included in the valid block is generated based on predetermined variable length code assignment. A short code is assigned to a quantization level with a high probability of occurrence, and a long code is assigned to a quantization level with a low probability of occurrence, and these are output to the multiplexing circuit 6. The multiplexing circuit 6 receives the encoded output of the variable length encoding circuit 15, the block address counter reset information output from the periodic refresh control circuit 13, and the encoding control circuit 1.
The encoding mode information outputted by the encoder 6 is time-division multiplexed and supplied to the buffer memory 17. The buffer memory 17 temporarily stores input data, reads out the stored information at a constant transmission speed, configures a transmission frame, converts it into a code format on the transmission path, for example, an AMI code, and outputs it digitally via the data output terminal 18. It is sent to the transmission line 19.

The encoding control circuit 16 detects the data storage amount of the buffer memory 17, and as this storage amount increases, the quantization characteristics of the quantization circuit 9 are made coarser. Alternatively, perform encoding control such as switching from all-pixel encoding mode to sub-sample mode where every other pixel is thinned out and encoded, or from all-field encoding mode to field frame dropping mode where frames are dropped every other field, By reducing the amount of information generated, overflow of the buffer memory 17 is prevented.

Receiving Side On the receiving side, data input from the data input terminal 21 through the transmission line 19 is converted from AMI code into a signal format that can be processed by digital signal processing, and after decomposing the transmission frame, it is sent to the buffer memory 2.
Store in 2. The clock generation circuit 23 extracts clock information from the data series branched and outputted from the buffer memory 22, generates various clocks necessary for decoding based on this, and supplies these clocks to circuits that require them. The code discontinuation circuit 24 sequentially reads data from the buffer memory 22 according to the decoding speed, decodes the encoding mode information and sends it to the decoding control circuit 25, and decodes the block address counter reset information to the periodic refresh control circuit 26.
Furthermore, invalid/valid block information and variable length coded data are decoded and supplied to the variable length code decoding circuit 27. The decoding control circuit 25 controls the decoding mode corresponding to the encoding mode on the transmitting side, ie, sub-sample mode, field frame dropping mode, etc., in accordance with the input encoding mode information.

The periodic refresh control circuit 26 resets a built-in block address counter according to the input block address counter reset information, and generates a periodic refresh control signal in synchronization with the periodic refresh control circuit 13 on the transmitting side. Switching control of the switching circuit 28 is performed based on this periodic refresh signal. The variable length code decoding circuit 27 decodes the invalid/valid block information and the variable length code, and outputs a signal in the same format as the quantized output that is the output of the quantization circuit 9 on the transmitting side. The adder circuit 29 adds the output of the variable length code decoding circuit 27 and the output of the switching circuit 28 to obtain a decoded signal, which is then
DA conversion circuit 31, frame memory 32 and 1
It is supplied to the pixel memory 33. Frame memory 32
delays input data by one frame period, and one-pixel memory 33 delays input data by one sample period. The switching circuit 28 selects the output of the 1-pixel memory 33 during the refresh period according to the output of the periodic refresh control circuit 26, selects the output of the frame memory 32 during other periods, and adds the selected data. Supplied to circuit 29. As a result, during the refresh period, the outputs of the adder circuit 29 and the one-pixel memory 33 are added together, and the contents of the frame memory 32 are refreshed using the obtained decoded signal. As a result, even if a transmission path code error occurs before that, and as a result, the contents of the frame memory 32 are affected by the error, causing mismatch between transmission and reception, it can be removed. The DA conversion circuit 31 receives the PCM decoded data supplied from the addition circuit 29 and converts it into an analog signal. This analog television signal is passed through a low pass filter (LPF).
The signal is band-limited at 34 and sent to a television signal output terminal 35.

In the above explanation, the case of a simple interframe coding method has been described, but it is clear that periodic refresh can be similarly achieved in the case of other coding algorithms that introduce motion compensation prediction, etc., and the present invention This does not specify any special interframe coding algorithm.

"Effects of the Invention" As explained above, according to the present invention, block address generation means for generating address signals of blocks that perform periodic refresh are installed on the transmitting side and the receiving side, respectively, and both block address generation means are installed on the transmitting side and the receiving side. Since periodic refresh is performed by synchronizing transmission and reception by operating in synchronization, only the block address counter reset information is sent, and the transmission of block address information for specifying the block to perform periodic refresh is not possible. This has the advantage that the amount of information allocated to information for conveying the movement of the subject can be increased accordingly, and high-quality encoding can be performed.

Note that the refresh is not limited to one block per frame, but may be performed in multiple blocks, and all blocks in one frame may be refreshed in each multiple frames. You can also refresh one block at a time. Further, as for the synchronization information, a reset signal may be sent as the synchronization information after all block address signals are generated a plurality of times, or the synchronization information may be sent every time a predetermined number of block address signals are generated.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of dividing a television screen into areas, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1... Television signal input terminal, 4... Synchronization separation circuit, 5... Clock generation circuit, 6... Multiplexing circuit, 9... Quantization circuit, 12, 32... Frame memory, 13, 26... Periodic refresh control circuit, 14, 33...1 pixel memory, 15...
...Variable length encoding circuit, 16...Encoding control circuit,
17, 22...Buffer memory, 18...Data output terminal, 19...Digital transmission line, 21...
Data input terminal, 24... Code decoding circuit, 27...
. . . variable length code decoding circuit, 23 . . . clock regeneration circuit, 25 . . . decoding control circuit.

Claims (1)

[Scope of Claims] 1. Based on a coding method that utilizes the correlation between frames of a television signal to perform interframe encoding and transmission, thereby reducing the influence of ripple propagation of image quality deterioration due to transmission path coding errors, etc. In the interframe coding method, in which encoded data is periodically transmitted from the transmitting side to the receiving side as periodic refresh information, the transmitting side stores a locally decoded signal in one switching terminal of a switching circuit for one frame period. The output side of a frame memory to be delayed is connected to the other switching terminal, and the output side of a one-pixel memory to which a locally decoded signal is stored and delayed by one sample period is connected to the other switching terminal, and the output of the switching circuit is connected to a subtracter and an adder, respectively. On the receiving side, as on the transmitting side, the input sides of the frame memory and 1 pixel memory are both connected to the output side of the adder, and the output side of the frame memory is connected to the switching circuit. and the output side of the 1-pixel memory is connected to the other switching terminal, and the output of the switching circuit and the output of the variable modulation code decoding circuit are added by the adder to decode the interframe code. The transmission side and the reception side each divide one screen of the television signal into a plurality of blocks each consisting of m lines x n pixels (m and n are positive integers), and Block address generation means for sequentially generating address signals of the blocks that have been received are installed, and synchronization information for synchronizing both block address generation means is sent from the transmitting side to the receiving side for each plurality of blocks, and on the transmitting side, the transmitting side For the block designated by the block address generation means, the switching circuit on the transmitting side is switched from the output side of the frame memory to the output side of the one-pixel memory, the periodic refresh information and synchronization information are transmitted, and the synchronization is performed on the receiving side. For a block that receives information and is specified by the receiving block address generation means, the receiving side switching circuit is switched from the output side of the frame memory to the output side of the 1-pixel memory, and the received periodic refresh information is decoded. A periodic refresh method in interframe coding characterized by: