JPH0221615B2 - - Google Patents

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory bank selection device that improves the efficiency of accessing memory banks. [Technical background of the invention and its problems] In a computer system having a large capacity memory, the memory device is divided into a plurality of banks to enable parallel data access, thereby increasing the apparent access speed. Efforts are being made to speed it up. Usually, the lower bit data of the memory address information is used to select which of the plurality of banks is selected. For example, when the memory device is composed of 2 ^m (m=2, 4) banks 1, 2, 3, and 4 as shown in FIG. 1, the data processing device 5 uses the address information shown in FIG. Using the lower 2 bits of
When it becomes (0, 0), bank 1 is selected, when it becomes (0, 1), bank 2 is selected, when it becomes (1, 0), bank 3 is selected, and when it becomes (1, 1), bank 4 is selected. There is. In this way, for example, when sequentially accessing the addresses of a memory device, it is possible to access bank 1 and access bank 2 during the access process, thereby increasing the apparent access speed. It's on. This access control method is usually called an interleave method, and the access address is
Each time the number of banks increases, adjacent banks can be accessed repeatedly, and a plurality of banks can equivalently be accessed at the same time. However, the data handled by the data processing device 5 is not necessarily stored in each address of the memory device in order. For example, when handling matrix data as shown in FIG. There are times when you want to determine the access order, such as... However, in the above-described bank selection using the lower two bits, one bank is always selected consecutively in this example, and as a result, the next access must be made until the previous access is completed. Such an example often appears in matrix multiplication operations, etc., and the problem is that it is not possible to effectively utilize a plurality of banks to speed up access. As a result, there was a problem in that it was not possible to speed up calculation processing. [Object of the Invention] The present invention has been made in consideration of the above circumstances, and its purpose is to randomly select a memory bank without regard to the memory access address pattern and to increase the access speed. An object of the present invention is to provide a memory bank selection device with a high degree of freedom in bank selection. [Summary of the Invention] The present invention uses n-bit (n is an integer) address information for a memory device consisting of 2 ^m banks (m is an integer) to address one of the 2 ^m banks. In the memory bank selection device for selection, the (i+k·m)th bit position of the address information (i is an integer of 0, 1, ..., m-1; k is an integer of 0, 1, ..., an exclusive OR circuit group comprising m sets of exclusive OR circuits that calculates the exclusive OR of data (an integer of n/m-1) and outputs it as the i-th output data; The present invention is characterized by comprising a decoder for selectively designating one of the 2 ^m banks from m sets of output data obtained from the sum circuit group. [Effects of the Invention] Thus, according to the present invention, 2 ^m memory banks can be arranged by taking into consideration not only the lower m bits of address information but also the data of the upper bits thereof.
Since the selection is made according to the m-bit data obtained by performing an exclusive OR with the data at the bit position where the bits are different, the memory access is almost unaffected by the memory access address pattern It becomes possible to select banks almost at random. In other words, accesses can be distributed to all banks, and as a result, effects such as speeding up memory access can be achieved. Moreover, its control form is simple and has high practical advantages. [Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the present invention, when a memory device is composed of 2 ^m banks, address information of k·m bits (k, m: integer) for the memory device can be mutually m
Data at different bit positions are subjected to exclusive OR processing, and the m-bit data obtained from the respective OR results is used as selection information for the 2 ^m banks. In other words, data at bit positions that differ by m bits from the 0th digit (2° bit position) of the address data shown in Figure 4, the m-th digit, the 2m-th digit, etc. Similarly, the first digit, m+
Exclusive OR processing is performed on the data of 1st digit, 2m+1 digit, etc., and then the m-1st digit, 2m-1st digit, 3m-th digit
Exclusive OR processing is performed on 1-digit data, and these m
m-bit data is obtained from the exclusive OR processing result of the set. Due to the nature of exclusive OR, the m-bit data obtained in this way is obtained corresponding to the lower m bits of the address data and its upper bit data, and any one bit changes. Even if the m bits output from this exclusive OR change, the bank to be selected changes as a result, so that one bank will not be selected unbiasedly. FIG. 5 shows a schematic configuration of the device of this embodiment when m is 2, that is, the memory device is configured with 2 ^m =4 banks. In this case, exclusive OR circuits (EX-OR circuits) 7 are provided hierarchically to perform exclusive OR processing on bit data that differs by m = 2 bits in the address data stored in the register 6, and these EX-OR circuits are provided hierarchically. -2 of 7 groups of OR circuits
The device is configured to input the two output data to the decoder 8 and obtain a selection signal for selectively selecting one of the memory banks 1, 2, 3, and 4. The decoder 8 can easily obtain one of the four selection signals by decoding the 2-bit data obtained from the EX-OR circuit. With this configuration, the value of at least one bit of the m-bit output data (exclusive OR result) changes due to a change in at least one bit of continuous m-bit data. , the same bank will not be selected consecutively. Then, banks 1, 2, 3, and 4 selected according to such data are accessed using the data of the upper bits excluding the lower m bits of the address information stored in the register 6 as an address. This makes it possible to perform memory accesses similar to conventional memory accesses without accessing the same address in the same bank using different address information. By the way, if the upper bits excluding the lower m bits of multiple address information are different, even if the same bank is accessed consecutively with the multiple address information, the addresses for that bank are different, so the same address will not be accessed twice. There's nothing to do. Furthermore, if the upper bits excluding the lower m bits are the same, the lower m bits are always different even if the upper bits are the same, so the addresses for banks are always different even if they are the same for each bank. Since the bank is selected, the same bank will not be accessed. Therefore, the same address in the same bank will not be accessed using different address information. In the above discussion, the address of the bank is the one excluding the lower m bits, but as long as the m bits are consecutive, it does not necessarily have to be the lower m bits due to the nature of exclusive OR, but can be at any position. It is also clear that even if data excluding consecutive m bits is used as a bank address, the same address in the same bank will not be accessed with different address information. The following table shows the banks selected when the address bit pattern changes continuously under such control.

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Claims (1)

[Claims] 1 Select one of the 2 ^m banks using n-bit (n is an integer) address information for a memory device consisting of 2 ^m banks (m is an integer). In the memory bank selection device for an exclusive OR circuit group comprising m sets of exclusive OR circuits that calculates an exclusive OR of data (an integer of m-1) and outputs it as i-th output data; and this exclusive OR circuit. A memory bank selection device comprising: a decoder for selectively specifying one of the 2 ^m banks from m sets of output data obtained from the group.