JPH0221695B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a small capacity storage element for storing serial digital information and a delay circuit used for the purpose of time adjustment.

Conventional delay circuits utilize the strain propagation delay characteristics of metal wires. Therefore, when the delay time is increased, a long metal wire is required, resulting in a disadvantage that the device becomes larger. Further, since the length cannot be freely changed, it is difficult to set an arbitrary time.

An object of the present invention is to provide a digitally controlled delay circuit that can be made compact regardless of the length of the delay time, and can also set an arbitrary delay time.

To achieve the above object, the digital delay circuit according to the present invention includes a clock circuit for incrementing time, a first-in first-out memory for temporarily storing data and a time added to each predetermined unit of the data, and a first-in first-out memory for setting a delay time. a delay time setting section and an addition circuit that adds the time output from the first-in, first-out memory and the delay time set in the delay time setting section;
The comparator circuit compares the incremented time of the clock circuit with the output of the adder circuit, and when the comparison values match, reads the corresponding data from the first-in, first-out memory.

According to the above configuration, the object of the present invention is completely achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of a digital delay circuit according to the present invention.

In the figure, 1 is a first-in-first-out (FIFO) memory that temporarily stores input data and time, 2 is a clock circuit that advances the time, 3 is a delay time setting unit for setting a delay time, and 4 is the time output from FIFO memory 1. 5 is a comparison circuit that compares the output of the adder circuit 4 and the output of the clock circuit 2, 6 is a buffer circuit, and 7 is output data.

FIG. 2 is a time chart for explaining the operation of FIG. 1. Input data is “A”, “B”,
Times "1", "2", "3", . . . are added to each "C" unit and stored in the FIFO memory 1. First, data "A" is written into the FIFO memory 1 along with time "1" by the signal "SI" from the clock circuit 2.
Since the FIFO memory 1 is a first-in, first-out memory, the data is output to the output terminal "OD" and a signal "OR" indicating that this data is valid is set. The clock circuit 2 updates the time to "2" after issuing a write instruction to the FIFO memory.

It is assumed that "14" is set in the delay time setting section 3. Since the output of the delay time setting section 3 is "14" and the time is "1", the calculation result of the adder circuit 4 is "15" and is output to the comparator circuit 5. The comparator circuit 5 confirms that the "OR" signal is output from the FIFO memory 1, and compares the output "2" of the clock circuit 2 with the output "15" of the adder circuit 4. As a result of the comparison, there is no match, so a wait is performed.

On the other hand, clock circuit 2 receives input data B and time “2”.
The following information is written to FIFO memory 1 one after another. And when clock circuit 2 advances to “15”,
Since the output of the adder circuit 4 and the output of the clock circuit 2 match, the comparator circuit 5 connects the FIFO memory 1 to the buffer 6.
Instructs to hold the output of FIFO memory 1
is instructed to discard the current data "A" and time "1" and output the next data "B" and time "2". As a result of this operation, data "A" is output with a time delay of "14" from the output of the buffer 6.

Next, since the time "2" is output to the FIFO memory 1, the output of the adder circuit 4 becomes "16", which coincides with the next increment time "16" of the clock circuit 2, so the comparator circuit 5 outputs "16". Next, buffer 6 is instructed to hold data “B”, and FIFO memory 1
is instructed to discard the current data "B" and time "2" and output the next data "C" and time 3. Thereafter, data "A", "B", "C", etc. delayed by time "14" are outputted by the same operation.

The delay time setting section of the delay circuit in the present invention includes:
The setting value can be easily changed.

As described in detail above, according to the present invention, an arbitrary delay time can be easily set, and since the delay time is digitally controlled, the device can be made compact regardless of the length of the delay time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital delay circuit according to the present invention, and FIG. 2 is a time chart for explaining the operation of FIG. 1... FIFO memory, 2... Clock circuit, 3...
Delay time setting section, 4...Addition circuit, 5...Comparison circuit, 6...Buffer, 10...Input, 11...Output.

Claims (1)

[Claims] 1. A clock circuit that increments time, a first-in, first-out memory that temporarily stores data and time added to each predetermined unit of the data, a delay time setting section for setting a delay time, and output from the first-in, first-out memory. An adding circuit that adds the time and the delay time set in the delay time setting section compares the incremented time of the clock circuit with the output of the adding circuit, and when the comparison values match, the corresponding data is added. A digital delay circuit comprising a comparison circuit that reads from the first-in first-out memory.