JPH0221704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides data buffering, packet assembly/disassembly, and network access control in a local network system that interconnects computer equipment such as cash registers distributed over a relatively narrow area. The present invention relates to a data transmission control device that performs such operations.

Generally, in a local network system, data transmission control is performed using the following procedure.

First, each terminal connected to the transmission line reads the destination terminal address written at the beginning of the data packet, and if it matches its own address, it reads the following data. If there is no error as a result of the CRC check, an ACK packet is sent to the sending terminal. If there is an error, the received data is discarded. The transmitting terminal uses a timer to measure the time after transmission, and if there is no ACK within a certain period of time, it retransmits. Furthermore, when performing even stricter transmission control, a RACK packet is transmitted to the transmitting terminal when an ACK packet is received.

Conventionally, in the data transmission control described above, execution of this control was performed by an application program prepared for each terminal, and the controller connecting the main system of the terminal and the transmission line was
It simply assembled packets and converted data levels (conversion between voltage level and logic level). However, as the load on the main system increases as more application programs are required, the efficiency of task processing decreases, and the application programs located higher in the hierarchy have to retransmit data and generate packets. Therefore, error recovery processing and collision prevention could not be performed efficiently and quickly, and sufficient reliability and high speed could not be obtained.

Furthermore, when the receive buffer is full, even if the data to be transmitted is of high priority, the transmission will not be successful and the transmission line will return to its initial state. The drawback was that it took a long time to receive the message.
Furthermore, since there was only one receiving buffer in the controller, the data processing order in the main system followed the order of received data, which caused the inconvenience that even if there was high priority data, it could not be processed immediately.

The purpose of this invention is to reduce the load on the host side of the main system, etc., to enable high-speed and efficient transmission control, and to sequentially process received data starting from the highest priority in accordance with the requirements of the main system. The object of the present invention is to provide a data transmission control device for a local network system that can be used as a local network system.

In summary, the present invention includes a reception control means for determining the packet format of data received from a data transmission line and creating a response packet based on the determination result; The transmission line includes a transmission control means for transmitting data onto the transmission line at the computer, and a transmission and reception data transfer control means for controlling the transmission and reception data transfer between the reception control means and the transmission control means and the main system. Access, packet generation, data buffering, retransmission control, etc. are performed at the level of the interface (data transmission control device) that connects the main system and the transmission line, rather than at the upper level (application program). Further, the reception control means is provided with a plurality of reception buffers for storing received data according to channel numbers specified in the header part of the data packet, and the transmission/reception data transfer control means is configured to transfer data from the main system to the specified channel. The device shall be equipped with a means for transferring the data of the corresponding reception buffer to the main system side, and will distribute the received data to the reception buffer according to its type, and will also transfer the data to the reception buffer according to the state of the main system side (for example, the one with the highest priority). This makes it possible to extract data from high-speed channels from the reception buffer.

According to this invention, since control regarding data transmission is directly performed by the data transmission control device,
The above controls, such as conversion between reception mode and transmission mode and response preparation based on packet generation/disassembly in each mode, can be executed extremely quickly, and data with high priority and data with low priority can be buffered separately from the main system's perspective. Furthermore, the main system can import arbitrary data from multiple receiving buffers according to task requirements. In other words, if you want to take in data from channel 1 with priority while executing a certain task, you can give priority to data from that reception buffer, and you can also take data from channel 10, which has the highest level. If it is set to receive priority data, it is possible to import the data into the main system as soon as it enters the reception buffer.

Further, since a plurality of reception buffers are provided in the reception control means, even if the processing operation of the main system is slow, it is possible to prevent a situation where the buffer becomes full and data cannot be received. Therefore, transmission efficiency can be improved, and the main system does not need to be high-speed.

FIG. 14 is a conceptual diagram of main parts of the data transmission control device of the present invention.

The data packet on the transmission line L is sent to the receiving section 20.
The data is transferred to reception buffers DSB1 to DSBn for each channel specified in the header section. Each reception buffer DSB functions as a reception data save buffer that saves data from a buffer (not shown) included in the reception unit 20.
Its capacity is m bytes at most, and it is filled in sequentially starting from the first byte data transfer area B0.
In the main system, data is extracted from any of the receiving buffers DSB1 to DSBn according to the application being executed.

If the receiving buffer corresponding to the channel specified in the header section of the data packet is not available, the receiving section 20 sends a buffer-full response to the transmitting terminal (described later). If the receiving buffer corresponding to the specified channel is free, an ACK packet is transmitted and the received data is transferred to the receiving buffer corresponding to the specified channel. In this way, the receiving section 2
0 controls data transmission independently of the main system operation.

Note that the transmitter 21 operates when transmitting data packets and response packets.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a local network system implementing the present invention. In the figure, terminal devices A to N, which are the main system, are
Transmission interface I/F of the embodiment of this invention
The terminals are connected to a data transmission line L consisting of a coaxial cable, so that various data can be freely transmitted and received between the respective terminals. FIG. 2 is a block diagram of the transmission interface I/F, and FIG. 3 is a more detailed block diagram thereof.

The transmission interface I/F includes a transmission control circuit 10, a reception control circuit 11, and a transmission/reception data transfer control circuit 12. Transmission control circuit 1
0 sends the transmission data or response packet onto the transmission line in a predetermined packet format, and the reception control circuit 11 determines the packet format of the data received from the transmission line L, and applies the determination result to the transmission line. Create a response packet based on the Furthermore, it includes the above-mentioned receiving buffers DSB1 to DSBn. Also,
The transmission/reception data transfer control circuit 12 controls the transfer of transmission/reception data between the reception control circuit 11, the transmission control circuit 10, and the terminal device.

In FIG. 3, the transmission/reception data transfer control circuit 12 is comprised of a transmission data transfer control circuit 1 and a reception data transfer control circuit 2. The transmission data transfer control circuit 1 includes a register a that temporarily stores data sent from the terminal device side byte by byte when transmitting various data, and a flag that is set when permitting writing to the register a. WEN
and a flag WED that is set when the terminal device has transferred all transmission data. Also,
The reception data transfer control circuit 2 transfers the reception data on the interface side to one when receiving various data.
A capture register b is used to transfer each byte to the terminal device, a flag REN is used to notify the terminal device for each channel that there is received data, and a flag REN is used to notify the terminal device that the terminal device has captured all received data for each channel. It has a flag RED to notify the interface side.

The above transmission control circuit 10 and reception control circuit 1
1 includes the above-mentioned receive buffer DSB for saving received data for each channel, a memory 4 for storing an interface control program as well as a transmitting buffer for saving transmitted data, a timer at the transmitting/receiving stage, and a control for controlling the interrupt function. A DMAC that performs DMA transfer of data between the circuit 6 and the memory 4 and the transmission/reception data transfer control circuits 1 and 2.
3. C for controlling transmitting and receiving operations and for transmitting and receiving buffer.
A link controller 7 having shift registers D and E for transmission and reception, and a line control circuit that modulates transmission data and sends it onto the line during transmission, and also includes a collision detection circuit that detects whether access requests are received from multiple terminals at the same time. a line control circuit 9 that receives a signal on the line, demodulates the signal, and transfers it to the link controller 7; and a sub CPU that controls the entire interface according to a control program stored in the memory 4.
Consists of 5.

FIG. 4 is a circuit diagram of a collision detection circuit provided in the line control circuit 8. As shown in the figure, the modulated signal and the pre-demodulation signal are applied to an exclusive OR circuit 81, whose output is used as a set signal for a flip-flop 82. By doing this, when the transmitted data and the received data are different, that is, at the time of a collision, the collision detection signal is
CO is obtained.

FIG. 5 is a circuit diagram of a carrier detection circuit provided in the line control circuit 9. FIG. 6 is a timing chart of the carrier detection circuit.
In this embodiment, a carrier signal CD1 indicating that there is a flow of data on the line and a signal CD2 indicating that there is no carrier signal CD1 for a certain period of time are obtained. That is, a receive clock a is created from a signal received from the line by a demodulation circuit 90, a binary counter 91 and a latch circuit 9.
2 to obtain signals CD1 and CD2. 6th
As shown in the figure, when the receive clock disappears, the CL (clear) terminal of the binary counter 91 is released, the count advances according to the basic clock φ, and the carrier signal CD1, which is a mirror image signal of the carrier wave, is obtained. As the count progresses further, a signal CD2 is obtained which is obtained by adding a preset processing time t to the period of the clock φ.

Each terminal individually detects the signal CD1 and the signal CD2, and uses a circuit not shown to send out a data packet only when the signal CD2 is "low" (logical 0), and the ACK packet or RACK packet is a signal. It is controlled so that it can be transmitted only when CD1 is "low" (logical 0). By controlling transmission and reception while checking signals CD1 and CD2 in this way, ACK and
Collision with data packets from other terminals is also prevented with respect to RACK packet transmission. 7th
The figure shows the relationship between the signals on the line and the signals CD1 and CD2. In the figure, time t represents a certain period of time when there is no carrier signal on the line. This time is set at least longer than the allowable ACK packet retransmission time, and the ACK packet is
If the line is not sent within the specified period, the line is deoccupied and new access from other terminals is permitted.

FIG. 8 shows the basic transmission procedure in this local network. Figure A shows the procedure when both the transmitting terminal and the receiving terminal are in a normal state. First, a data packet including a header section such as a flag and an address is transmitted from a transmitting terminal to a destination.
When this data packet is received normally, the data packet receiving terminal transmits an ACK packet.
The data packet transmitting terminal that has received the ACK packet transmits a response packet (RACK packet) in response to the ACK packet. When the receiving terminal is not ready to accept the data packet, the receiving terminal transmits an NRDY packet and ends the process, as shown in FIG. 2B. Also,
If the receiving buffer corresponding to the channel of the transmitted data packet is blocked,
The process ends by sending an NRDY packet with a buffer statement as shown in the figure below.

FIG. 9 is a diagram showing a packet format.
This packet consists of a format that separates data into flags (leading flags) and flags (trailing flags). Both flag codes are 7E (hexadecimal). The destination address DA specifies the receiving station. Source address SA specifies the transmitting station. data type
TYPE specifies the type of transfer frame. There are four types: data, ACK, RACK, and NRADY. The channel number CH.NO specifies the channel type of the packet. Line status DLS
Write the statement when sending NRADY packet. The statements include "receiving not possible" and "receiving buffer full." bite counter
BCL and BCH specify the number of bytes of data. The data field DATA sets the data to be transferred. This data field DATA exists only in data packets. CRC provides an error detection code.

Next, the operation of the interface shown in Figure 3 is as follows.
This will be explained with reference to FIGS. 10 and 11.

(1) Transmission Operation FIGS. 10A to 10C are flowcharts showing the data transmission operation.

Now, suppose that specific data is to be transmitted from terminal device A to terminal device N.

First, at step n1 (hereinafter step ni will simply be referred to as ni), terminal device A writes 1 byte of data to write register a of transmission data transfer control circuit 1, and sets flag WEN. At this time, the terminal device A sends the transmission data length (number of bytes) and channel information CHn specifying which channel to use for handling the data together with the data and sets it in a predetermined area.

The transfer control circuit 1 that received these data,
Select the DRQ3 channel (the channel used for data transfer within the interface), which is the DMA transfer channel for the transmit data, and send the DMA to DMAC3.
Instruct transfer (n2). Upon receiving this instruction, the DMAC 3 sets a transfer destination address in the memory 4 (n3), and transfers the data in register a to the transmission buffer A at that address (n4). When the transfer of 1 byte is completed, the flag WEN is reset (n5). Terminal device A monitors the flag WEN, and when it learns that it will be reset (n21), returns to n20 and sends the next 1 byte of data to register a. In this way, terminal device A monitors flag WEN and writes 1 byte of data to register a each time the flag is reset, while on the interface side, DMAC writes register a.
The data is sequentially DMA-transferred to transmission buffer A. When all data transfer is completed, terminal device A goes to set flag WED (n22). When this flag WED is set, the control circuit 1
Use n7 and n8 to check the specified number of bytes and check the send command, and if correct, proceed to n9.
DMAC3 executes DMA transfer of data from buffer A to buffer B at n9 and n10. When the transfer is completed, the flag WED is reset to indicate that the transmission buffer is free (n11).
When terminal device A learns that flag WED is in the reset state, it transfers the transmission data to buffer A in the same manner as described above if there is data to be transmitted next.

On the other hand, when the transmission data is prepared in the transmission buffer B as described above, the CPU 5, which controls the movement of the interface, issues a transmission instruction (n30) and sets the link controller 7 to a transmission ready state (n31). At this time, the link controller 7 checks the signal CD2 obtained by the carrier detection circuit CD, and
If it is "low", the leading flag F, which is the first data of the packet, is immediately sent out onto the line via the line control circuit 8 (n32). continue
The CPU 5 sets the start address and the number of data bytes of buffer B in the memory 4 in the DMAC 3 (n33,
n34), instructs data transfer from buffer B to link controller 7. During this time, the link controller 7 continues to send out the above-mentioned leading flag F, but after completing n34, it stops sending out the same flag F (n35). Next, when the transmission buffer C of the link controller 7, which is the data transfer destination, is in an empty state (n36), and the link controller 7 sends a data transfer enable signal to the buffer C to the DMAC 3 (n37), One byte of data is transferred from buffer B to buffer C at n38. The link controller 7 further transfers the data transferred to the buffer C to the shift register D, and transfers 1 byte to the shift register D (n40).
Return to n37 again and execute DMA transfer,
The data in the shift register D is sent to the line control circuit 8 and sent to the line after modulation (n41 to n44).
As will be explained later, if the above operations are performed simultaneously on two or more terminals, a collision will occur at least when sending the source address of the data, but this collision will be detected by the collision detection circuit CO. If so, proceed from n44 to n60 and prohibit transmission. now,
Assuming there is no collision, link controller 7
sequentially transfers data from buffer C to shift register D, and sequentially sends data transferred by DMA to buffer C to line control circuit 8 as described above.
This operation (n37 to n45) is repeated, and when the specified data length has been sent, the DMAC 3 increments its built-in byte counter, thereby notifying the link controller 7 that the frame has been sent (n46). Upon receiving this, the link controller 7 attaches a CRC and completes sending one frame of data. Then, the link controller 7 sends an interrupt signal to the CPU 5 indicating that data transmission of one frame has been completed (n47), and the CPU 5 sends a trailing flag F to the line control circuit 8 via the link controller 7. Instruct (n48). Trailing flag F
The flag continues to be sent until the CPU 5 performs transmission completion processing (n49) and reception preparation processing (n50), and when these processings are completed, flag sending is stopped (n51) and the interface is received. Set to mode (n52).

Next, in n44, the operation when data packets collide will be explained.

Data packet collisions occur when two or more terminals attempt to transmit at the same time in a common channel scheme where each terminal has equal access. Although the signal CD2 prevents collisions when the access timings are completely different, since there is a large propagation delay between mutually distant terminals, it takes time to detect the transmission of another terminal. As a result, collisions are more likely to occur. Generally, in a local network system that employs a common channel method, in order to solve the above problem, data is retransmitted after waiting a certain period of time after a collision is detected. This processing is called back-off processing. Below n60 is the procedure for performing this back-off process.

When a collision is detected by the collision detection circuit CO, all terminals that have sent data packets stop transmitting (n60). The line is then raised high (n61) so that other terminals can easily detect that a collision has occurred. Next, the falling edge of the signal CD2 is detected (n62), and at that falling timing, the random number table TBL provided in the memory 4 is
A predetermined back-off timer value is read from (n63), and the value is set in the timer T of the control circuit 6 (n64). Subsequently, when the predetermined time set in this manner has elapsed (n65), the CPU 5 detects the state of the signal CD2 again, and if the level is "low" and access is possible, returns to n30. Repeat the above-described transmission operation. If the level of signal CD2 is "high" and line use is not permitted, proceed to n67 and start the back-off timer again at the timing when signal CD2 falls (n64), and the time when the timer elapses is set as signal CD2. Wait until the switch is turned off.

FIG. 12 shows the operation when terminals A, B, and C attempt to access almost simultaneously (with some errors due to propagation delays, etc.) and a collision occurs. A,
When each terminal B and C detects a collision as shown in the figure, they immediately stop transmitting, and at the falling timing of signal CD2, each terminal sets the back-off timer values t1, t2, and t3 generated by the random number table. Start. When time t1 has elapsed, terminal A detects the state of signal CD2. At this time, terminal B and terminal C cannot transmit because the timer values t2 and t3 have not elapsed. Therefore, unless there is access from other terminals, the signal CD2
Since it is in the off state, retransmission from terminal A is possible. This example shows a case where a data packet is transmitted from terminal A to terminal B. Regarding the other B terminals and C terminals that could not transmit due to the collision, retransmission is attempted after the A terminal's transmission is successful. This method is carried out in the same manner as above. In other words, the timer values t2 and t3 are started at the falling timing of the signal CD2, and the B terminal
When t2 has elapsed, the state of signal CD2 is checked, and if it is off, it is retransmitted. Furthermore, the C terminal checks the signal CD2 when time t3 has elapsed, and if it is off, retransmits it. In this way, the order of transmissions from colliding terminals is sorted out while performing back-off processing.

As described above, in this embodiment, the starting point of the back-off timer is set at the falling timing of the signal CD2, so that it starts at the same timing regardless of the type of terminal. For this reason,
This has the advantage of reducing the probability that a collision will occur again and improving the accuracy of the back-off timer. In addition,
The backoff timer value set by n64 is set to the same value the next time it is set by n64 unless a new collision occurs.

FIG. 13 shows the structure of the data packet sent out on the line by the above operation.

As shown in the figure, m leading flags F are located at the beginning of the packet, and j trailing flags F are located at the end of the packet. As mentioned above, m flags are sent from n32 to n35,
j flags are sent at n48 to n51. By consecutively sending flags at the beginning and end of a packet in this way, the transmitting terminal can prepare for reception at the time when the end flag is continuously sent, and the receiving terminal can prepare for reception while receiving the consecutive leading flags. The mode can be set to normal reception mode.

The receiving terminal is set to normal receiving mode in the following cases. For example, if a receiving terminal receives signals from two or more transmitting terminals at the same time, a collision is detected when the source address is received. At this time, since the receiving terminal has already received the reading flag and the receiving mode has not been reset, it is in a data waiting state. but,
The two transmitting terminals that have collided have terminated their transmission and are waiting for the next chance. Therefore, when a new data packet is transmitted from either terminal or another terminal, the receiving terminal in the data waiting state regards the first leading flag as the trailing flag (the leading flag and the trailing flag are both "7E"). ), and upon receiving the reading flag, it detects that the format of the packet is incorrect (the format length is short) and performs error processing. Therefore, in such a case, if there is only one reading flag, there is a possibility that the received data after error processing will be treated as having no leading flag and error processing will be performed.

On the other hand, if an appropriate number of leading flags are consecutively added to a data packet, the receiving terminal will, when receiving the first leading flag,
Error processing is performed at the next and subsequent flag reception times, and when the normal reception mode is reached, it becomes possible to process the still continuing leading flag as a flag for the next packet.

That is, m leading flags and j
By adding trailing flags,
The sending terminal and the receiving terminal can always be in a state where they can normally receive packets.

(2) Reception operation FIGS. 11A to 11C are flowcharts showing the data reception operation.

The data packet sent onto the line as described above is received by the line control circuit 9 on the terminal device N side (n70), demodulated (n71), and guided to the shift register E of the link controller 7 (n72). The link controller 7 determines whether the first byte of the received data is a flag or something other than a flag, and if it is a flag, guides the next byte of data to the shift register E. If it is other than a flag, the destination address
Read the DA and determine whether the address is the own address (n75), and if it matches the own address, proceed to n76. n76 transfers the received data of shift register E to receive buffer F,
Instructs DMAC3 that there is data to be received (n77). At the same time, DRQ1 is selected as the channel for transferring data to buffer G. The DMAC 3, which has received the instruction that there is data to be received, sequentially transfers the received data in the reception buffer F to the buffer G in the memory 4. There are as many buffers G as there are channels, and the received data is transferred to the portion corresponding to the channel number specified in the packet. This transfer is performed byte by byte of data guided to register E, and when a flag indicating a data break (trailing flag) is detected, it is determined that reception is complete (n79), and the link controller 7 sends the data to the CPU 5.
A reception completion instruction is given to (n80). Upon receiving this instruction, the CPU 5 prohibits the reception mode and determines the type of the transmitted data. If it is data information, it is determined by the flag RDY in the received data transfer control circuit 2 whether the terminal device is in a ready state at the time of reception and can receive it (n89). This flag RDY is controlled by the terminal device and is set when the terminal device is in a receiving state. If it is possible to receive it, then select the specified channel (CH in Figure 9).
(specified by No.) receive buffer G (memory 4
) is free or not (n90). As mentioned above, this reception buffer G is provided with a number of channels, and the flag REN in the reception data transfer control circuit 2 indicates whether each channel is in an empty state.
In other words, if the receive buffer of any channel is free, the flag corresponding to that channel
REN is set. Conversely, if the channel is in a buffer full state, the flag corresponding to that channel
REN is reset. If the receiving buffer of the channel specified by n90 is free, an ACK packet is sent to the terminal that sent the data packet (n91). Although not shown in Figure 11,
This ACK packet is assembled by the CPU 5.
As is clear from FIG. 9, the assembly of the ACK packet is extremely simple, and the other data except the destination address DA are fixed codes. There is no need to create a destination address itself, and the source address SA of the sent data packet can be used as is.
After transmitting the ACK packet, the CPU 5 sets the data present flag REN (of the designated channel) in the reception data transfer control circuit 2 (n92), and is set to re-reception mode.

If the terminal device N is unable to receive data at n89, it transmits an NRDY packet at n93 and returns to the re-receiving mode. Also, if the reception buffer is full on n90, the flag corresponding to the specified channel
If REN is set, the n94 sends a buffer full (NRDY) packet and returns to re-reception mode.

On the other hand, in terminal device A, in terminal device N, the above
Since the ACK packet transmitted at n91 is received, the process proceeds to n82→n83→n95. In normal cases, after transmitting a data packet, the state transitions to an ACK packet wait state, so the process proceeds from n95 to n96, transmits a RACK packet to the ACK packet transmitting terminal, that is, terminal device N (n96), and sets the transmit/receive controller to receive mode. (n97)

Note that ACK packet transmission in n91 and n96
All RACK packet transmissions are time-managed by a transmission timer T1, and error handling is performed when ACK packet transmission fails a predetermined number of times, or when a RACK packet cannot be transmitted even after transmitting ACK packets a predetermined number of times. I am trying to make sure that this is done.

When terminal device A sends a RACK packet as described above, terminal device N sends n82→n83→
Proceed as n84→n98. When normal state transition occurs
Since the ACK packet transmission has already been completed when the RACK packet is received, proceed to n98→n97 to set the reception mode. If a RACK packet is received without transmitting an ACK packet, the ACK packet is retransmitted (n99) and the reception mode is set (n97). Further, if the received packet at n85 is an NRDY packet, the process proceeds from n85 to n100. Normally, when receiving an NRDY packet, it is after the data packet has been sent, so the process proceeds from n100 to n101, and the terminal device indicates that the other party is in the NRDY state (a state in which data cannot be accepted).
to set the reception mode (n97).

Transmission of response packets is performed below n82 as described above, but when a data packet is normally received and an ACK packet is transmitted, the received data is transferred to and from the terminal device via the transmit/receive data transfer control circuit. Transfer processing is performed. This procedure is shown below n110.

At n110, the terminal device N sets a flag corresponding to the channel specified by the main CPU (not shown).
Check whether REN is set. If the flag REN corresponding to that channel is set,
A received data read command is given to the received data control circuit 2 (n111). And above flag REN
(n112), the CPU 5 also resets the start address and received data length (number of bytes) of the buffer G (of the specified channel number) in the memory 5.
Set to DMAC3 and prepare for DMA transfer (n113). Further, the CPU 5 sets the channel used for data transfer (different from the specified channel described above, refers to a data transfer channel within the interface) to DRQ2 (n114), and instructs DMA transfer (n115). Then from buffer G to register b
One byte of data is transferred to the terminal device N (n116), and an interrupt signal is output to the terminal device N (n117). When the terminal device N receives this interrupt signal, it proceeds from n130 to n131 and takes in the data transferred to register b. On the other hand, since the data presence flag REN has been reset at n112, one new byte of data is transferred from buffer F to buffer G at n78. At the same time, reset the flag REN using n77. Therefore, n110 and below are executed again,
The next 1 byte of data is set in register b at n116, and the terminal device N takes in the data at n131. Repeat this operation, and when all the data in buffer G is fetched via register b, the DMA transfer is completed and the process moves from n119 to n120.
DMAC3 stops operating.

The terminal device N side checks whether the number of bytes of the received data matches the number of bytes of the actually captured data, and if they match, processes the captured data into the desired format (n133), and the processing process is completed. When completed (n134), the flag RED of the reception data transfer control circuit 2 is set (n135) to notify the interface side of the completion of the fetching. When the CPU 5 on the interface side detects that the flag RED is set (n121), it resets the flag RED (n122) and prepares for the next data transmission/reception.

In the above manner, from terminal device A to terminal device N
Specific data is sent to.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a local network system implementing the present invention. Figure 2 is a block diagram of the transmission interface I/F.
FIG. 3 is a more detailed block diagram. FIG. 4 is a circuit diagram of a collision detection circuit provided in the line control circuit 8. FIG. 5 is a circuit diagram of a carrier detection circuit provided in the line control circuit 9. FIG. 6 is a timing chart of the carrier detection circuit. FIG. 7 shows the relationship between the signals on the line and the signals CD1 and CD2. FIG. 8 shows the basic transmission procedure in this local network. FIG. 9 is a diagram showing a packet format. FIGS. 10A to 10C are flowcharts showing the data transmission operation. FIGS. 11A to 11C are flowcharts showing the data receiving operation. FIG. 12 shows the operation when terminals A, B, and C attempt to access almost simultaneously and a collision occurs. FIG. 13 shows the structure of a data packet sent out on the line. FIG. 14 is a conceptual diagram of main parts of the data transmission control device of the present invention. (Fig. 2) 10-transmission control circuit, 11-reception control circuit, 12-transmission/reception data transfer control circuit, (Fig. 3) 1-transmission data transfer control circuit, 2-reception data transfer control circuit, 3-DMAC ( direct memory access controller), 4-memory, 5
- Sub CPU, 6 - Control circuit, 7 - Link controller, 8 - Line control circuit (transmission), 9 - Line control circuit (reception).

Claims (1)

[Claims] 1 A device connected between the main system that processes the contents of transmitted and received data and the data transmission line that constitutes the local network, which determines the packet format of the data received from the data transmission line, and uses the determination result to determine the packet format of the data received from the data transmission line. a reception control means for creating a response packet using a predetermined packet format; a transmission control means for transmitting the transmission data or the response packet onto a transmission line in a predetermined packet format; the reception control means and the transmission control means; and the main system. a transmitting/receiving data transfer control means for controlling the transfer of transmitting/receiving data between the transmitting and receiving data, and the receiving controlling means includes a plurality of receiving buffers for storing received data according to channel numbers specified in the header part of the data packet; A data transmission control device for a local network system, wherein the transmission/reception data transfer control means includes means for transferring data in a reception buffer corresponding to a specified channel from the main system to the main system side.