JPH022188B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an image processing system that uses an image memory that can simultaneously access continuous data in both vertical and horizontal directions in an image space. Regarding image processing methods for speeding up data transfer between input/output devices, in particular serial processing that performs data shift operations required when writing data to or reading data from image memory during data transfer. The present invention relates to an image processing method that eliminates the processing time required for data shifting by importing data during a parallel conversion operation.

[Technology background]

First, the principle of the image memory to which the present invention is directed will be explained.

FIG. 1 shows the image space, that is, the logical space of the image memory. The pixel position in space is given by row address i and column address j with the origin at the upper left corner.
is expressed as (i, j). In addition, in the figure,
, . . . are serial numbers when raster scanning is performed on all pixels in the space.

In this image space, image memory simultaneously accesses a fixed number of pixels (e.g. 8 or 16) in the row or column direction, starting with a pixel at an arbitrary or restricted position. It is possible to do so.

FIG. 2 shows an example of the configuration of a physical memory that implements the above image memory. Generally, in order to enable simultaneous access to a group of pixels located at arbitrary positions in the vertical and horizontal directions, the bits corresponding to those pixels must be distributed and stored on different memory chips in physical memory. . This is because only one bit of a memory chip can be accessed at a time. Therefore, it is necessary to store the data in the image space shown in FIG. 1 in each memory chip with a predetermined shift applied to each row or column, and to restore the data by inversely shifting the data when reading the data.

Figure 2 shows the circular shift in the column direction for each row of image data, sequentially 0, 1, 2,
By giving 3,... bits each, each chip is 1, 2,
3, 4, etc. As a result, for example, the horizontal pixel columns, . and also the first
The vertical pixel columns, ,... in the figure are stored in a distributed manner on each chip, as indicated by the diagonally broken lines in Figure 2, and can similarly be accessed simultaneously. .

However, for this purpose, it is necessary to provide a data shift means between the image memory and the data bus, to perform a predetermined data shift when writing, and to perform data shift for restoration when reading.

FIG. 3 shows an example of the configuration of a conventional image processing system including such an image memory.

In FIG. 3, 1 is a main processing unit, 2 is a circular shifter, 3 is an image memory, 4 is a data bus, 5 and 6 are adapters, 7 is an image output device such as a display or printer, 8 is an image input device, and 9 is an image input device. 10 is a parallel/serial conversion circuit, 11 is a serial/parallel conversion circuit, and 12 is a buffer.

Circular shifter 2 performs the above-described data shift operation bidirectionally between image memory 3 and data bus 4 in accordance with a shift control signal from main processing device 1 . When the image memory and data bus 4 are configured to have a width of 8 bits, for example, the shift amount is given by the remainder of (i+j)/8, that is, (i+j)8. This remainder is
There are eight types from 0 to 7.

The input/output device adapters 5 and 6 are adapters for controlling DMA transfer and matching data formats between the input/output device and the image memory. The input/output device adapter 5 is connected to the data bus 4
The parallel format data is converted into serial format data by a parallel/serial conversion circuit 10 and supplied to an image output device 7 such as a display or a printer.
The input/output device adapter 6 is an image input device 8
The serial format data outputted from the serial/parallel converting circuit 11 converts the serial format data into parallel format data and supplies it to the data bus 4.

In such a system, when performing DMA transfer between the image memory 3 and the input/output device adapter (5 or 6), the memory access time becomes longer due to data shifting in the circular shifter 2, Since the data conversion operation in the output device adapter (5 or 6) is added in series, there is a problem that the transfer speed becomes slow.

[Object and structure of the invention]

An object of the present invention is to reduce memory access time when transferring data between an image memory and an input/output device, and therefore, data shift operations can be integrated into serial/parallel conversion or parallel/serial conversion operations. By focusing on this, it eliminates the need for special time for data shifting.

The configuration of the present invention is such that a group of continuous image data in the vertical or horizontal direction specified by the row address and the column address can be accessed simultaneously in either direction. An image processing system equipped with an image memory that shifts data according to one address and stores it in a distributed manner, an adapter for an input/output device having a serial/parallel conversion function or a parallel/serial conversion function, an input/output device, and a processing device. In this method, the input/output device adapter is provided with means for simultaneously shifting data during the process of serial/parallel conversion or parallel/serial conversion, and the data is transferred between the image memory and the input/output device via the input/output device adapter. The present invention is characterized in that, when performing transfer, the data shift required for reading or writing to the image memory is executed in the input/output device adapter.

[Examples of the Invention] The details of the present invention will be described below with reference to Examples.

FIG. 4 is a block diagram of a system according to an embodiment of the present invention, which corresponds to the conventional system shown in FIG. 1, and shows the state of DMA transfer processing. In the figure, 1 is a main processing unit, 2 is a circular shifter, 3 is an image memory, 5 and 6 are input/output device adapters, 7 is an image output device such as a display or printer, 8 is an image input device, and 9 and 12 are buffers. , 13 is a parallel/serial conversion and shift circuit;
14 is a serial/parallel conversion and shift circuit, 15 is a
DMA controller, 16 represents a DMA data bus.

In this embodiment, the parallel/serial conversion and shift circuit 13 or the serial/parallel conversion and shift circuit 14 in the input/output device adapter is
It performs the same function as Circular Shifter 2 during transfer.

Figure 5 shows parallel/serial conversion and shift circuit 1.
FIG. 3 is a detailed configuration diagram of No. 3. In the figure, the buffer 9 includes data from the image memory 3 to the DMA data bus 16.
Array of unshift-corrected image data read out above, , , ,
,, are illustrated. In this data, a bit must originally be placed at the top position on the left end. Therefore, it is necessary to perform a 2-bit left circular shifter for restoration.

An 8-1 data selector 17 sequentially selects one designated output from among the eight outputs of the buffer 9 according to the output of the counter 18, and outputs it as a video signal in serial format data. The counter 18 is a 3-bit counter whose initial value is preset by shift control data sent in advance from the main processing unit, and then counts the video output clock shown in FIG. 6 and increments by +1 from that value. A scan signal 18a for sequentially transmitting the eight outputs of the buffer 17 is output.

FIG. 6 is a timing diagram of the circuit of FIG. 5, and shows the counter output and the 8-1 data selector 17 in the case of the image data array illustrated in FIG.
The video signal selected and output from the buffer 9 is shown. In this example, the initial value of the counter 18 is set to "010", so that the parallel format data array in the buffer 9 receives a 2-bit left circular shifter and is simultaneously converted to serial format data as shown in the figure. , , . . . is output as a corrected data array.

FIG. 7 is a detailed configuration diagram of the serial/parallel conversion and shift circuit 14 of the input/output device adapter 6 which performs an operation opposite to that of the input/output device adapter 5.
In the figure, 19 is an addressable latch circuit,
Input data in serial form is sequentially set in the latches addressed by the output value of counter 20.
The figure shows an example of providing a 2-bit right circular shifter.

The counter 20 corresponds to the counter 18 in FIG. 5, and similarly has an initial value preset by shift control data ("010" in this example). This value corresponds to the necessary 2-bit shift amount for the image memory 3. The video reception clock is counted from this initial value and an address signal 20a is output.

Addressable latch circuit 19 is controlled by counter 20 to distribute successive bits of serial format input data to appropriate shift positions on buffer 12 and set as parallel format data.
The data set in the buffer 12 is output in parallel onto the DMA data bus 16 as 2-bit right circular shifted data and written into the image memory 3.

In this way, a circular shifter can be performed simultaneously in a parallel/serial conversion or serial/parallel conversion operation.

〔Effect of the invention〕

As described above, according to the present invention, the shift operation required for writing or reading image memory is carried out in serial/parallel format when data is transferred to/from an input/output device that operates using serial format data. Since the data is captured during the conversion or parallel/serial conversion operation and is processed simultaneously, the image memory access time can be significantly shortened and the DMA transfer speed can be improved.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an image space, FIG. 2 is an explanatory diagram showing an image arrangement on a physical memory, and FIG. 3 is a configuration diagram of an example of a conventional image processing system.
FIG. 4 is a block diagram of one embodiment of the present invention, FIG. 5 is an embodiment diagram of a parallel/serial conversion and shift circuit, and FIG.
The diagram shows the operation timing diagram of the circuit shown in Figure 5, and the circuit shown in Figure 7.
The figure is an example diagram of a serial/parallel conversion and shift circuit. In the figure, 1 is a main processing unit, 2 is a circular shifter, 3 is an image memory, 5 and 6 are input/output device adapters, 7 is an image output device such as a display or printer, 8 is an image input device, 9
13 represents a parallel/serial conversion and shift circuit, and 14 represents a serial/parallel conversion and shift circuit.

Claims (1)

[Claims] 1. Shift data onto multiple memory chips using one address so that a group of continuous image data in the vertical or horizontal direction specified by a row address and a column address can be accessed simultaneously in either direction. Image memory for distributed storage and serial/parallel conversion or parallel/
An input/output device adapter with a serial conversion function,
In an image processing system equipped with an input/output device and a processing device, an adapter for the input/output device is provided with means for simultaneously performing data shifting during the process of serial/parallel conversion or parallel/serial conversion, and the image memory and the input/output device are An image processing method characterized in that when data is transferred between the input and output device adapters, the data shift required for reading or writing to an image memory is executed in the input/output device adapters.