JPH0222436B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a coin sorting device in which a plurality of coin detectors are provided in a coin passage to determine the authenticity of inserted coins and whether the coins are continuously inserted. It is suitable for use in vending machines, etc.

[Conventional technology]

The coin sorting method of this type of coin sorting device consists of a sorting coil as a coin detector, a standard impedance element and two other fixed elements that are compared after the sorting coil, and a bridge circuit is constructed. The bridge circuit method detects the equilibrium point of the bridge circuit, the frequency detection method uses the selection coil as a resonant element to configure an oscillation circuit, and detects changes in the oscillation frequency of the oscillation circuit when a coin passes, and the selection coil is used as an oscillation coil and a receiving coil. These coils are arranged opposite to each other with the coin passage in between, and when a coin passes through the intermediate position between both coils,
An induced voltage detection method that detects a voltage change induced in a receiving coil is known. These sorting methods are similar in that they are sorted based on whether or not a sorting signal based on the output of a sorting coil that detects the material, thickness, etc., diameter, and shape of the input coin is within a predetermined coin discrimination standard range. There is.

For example, when coins are sorted using a bridge circuit system, when a genuine coin (hereinafter referred to as a genuine coin) is inserted, the bridge is balanced and the bridge output becomes zero. However, if a counterfeit coin that is made of the same material as a genuine coin and has a larger diameter than the genuine coin (hereinafter referred to as a counterfeit coin) is inserted, the impedance change of the sorting coil is greater than the impedance change for genuine coins, so the bridge circuit Equilibrate twice. That is, the amount of change in impedance of the sorting coil in the case of counterfeit money is larger than the amount of change in impedance of the sorting coil in the case of genuine money. Eventually, there will be only two points where the impedance value of the selection coil matches the impedance value of the selection coil that satisfies the equilibrium condition of the bridge circuit. As a result, the bridge circuit generates a bridge output similar to that when genuine coins are inserted only twice, resulting in an error. Such errors also occur in the frequency detection method or the induced voltage detection method.

Furthermore, in a device that sorts coins of multiple denominations, it is necessary to determine the denomination of the input coins and to sort the coins by denomination. However, if coins of different denominations are continuously thrown in and these coins are rolling at a predetermined interval or less, the sorting member for sorting the coins by denomination will not be able to sort the coins that were first thrown in. A situation occurs in which the second input coin is distributed following the first input coin before the state changes from the state to the distribution of the next input coin. As a result, for example, if an inserted coin is stored in a coin tube in which coins used as change are stacked and stored, there is a possibility that coins of different denominations will be stored in the coin tube.
Furthermore, in this case, if the diameter of the next coin thrown in is larger than the diameter of the first coin thrown in, coin jams will occur.

For this purpose, the applicant previously proposed the following device in Japanese Patent Application No. 52-66971 (see Japanese Patent Application Laid-open No. 54-2196).
and Japanese Patent Application No. 52-66972 (see Japanese Patent Application Laid-open No. 54-2197). That is, in these methods, first and second coin detectors are arranged at a predetermined distance apart along the coin path before and after the sorting coil, and
It is a device that confirms the rolling position of coins. In this device, the period from when the inserted coin is detected by the first coin detector to when it is detected by the second coin detector is defined as the input coin sorting period, and within this sorting period, the sorting coil When the signal falls within the genuine coin determination standard range only once, the inserted coin is determined to be genuine coin. Therefore, during the sorting period, the signal from the sorting coil is 2.
If the coin falls within the standard range more than once, or if it does not fall within the standard range at all, it is determined to be a counterfeit coin. In addition, in the device, in order to detect that the inserted coins are consecutively placed at a predetermined interval or less, the first inserted coin is detected by the first coin detector, and then the coin is detected by the second coin detector. Until the coin is inserted, the next coin inserted will be the first coin.
It is determined whether or not the coin is detected by the coin detector. That is, if the next inserted coin is detected by the first coin detector before the first inserted coin is detected by the second coin detector, it is determined that continuous insertion is performed.

Then, when the results of these continuous insertion determinations and authenticity determinations indicate that the inserted coins can be accepted (when genuine coins are inserted instead of consecutively), the normally inserted coins are returned in the return direction. By changing the sorting member that is in the sorting state to the state of sorting the inserted coins in the storage direction, the inserted coins are sorted into either the return direction or the storage direction.

[Problem that the invention seeks to solve]

By the way, when determining continuous insertion by providing the first and second coin detectors as described above, the interval between these two coin detectors should be long to prevent missorting of inserted coins. It would be better to leave it there, but if it were too long, it would have to be fed at intervals, which would make it less convenient to use.

For this reason, it is necessary to make the interval between the two coin detectors as short as possible within a range that does not hinder the sorting of coins.

However, the rolling speed of the coin varies depending on the conditions when it is inserted and is not constant, so if the speed of the subsequent coin is faster, it will not pass through the first and second coin detectors. There is a risk that the subsequent coins will catch up with the preceding coins that are being distributed as genuine coins, making it impossible to distribute these coins by denomination.

In view of the above-mentioned points, it is an object of the present invention to provide a coin sorting device in which subsequent coins are returned when a preceding coin is being sorted as genuine coins.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention includes a rolling path on which a coin inserted from a coin input slot rolls, and a system that is sequentially provided along the rolling path to detect the properties or passage of the inserted coin. multiple coin detectors,
an acceptability determining circuit that integrates the outputs of the plurality of coin detectors and determines acceptability based on continuous input of the input coins and authenticity; a flip-flop that is set based on the acceptability determination of the circuit; a timer for resetting the flip-flop a predetermined time after the flip-flop is set; a distributing member that distributes the input coins by being brought into the first state by the reset output of the flip-flop and brought into the second state by the set output; a return path to which the inserted coins are guided in accordance with the first state; a receiving path to which the inserted coins are guided in accordance with the second state of the sorting member; It is characterized by comprising a reset means for detecting the output from the last stage of the flip-flops and resetting the flip-flop.

[Effect]

In the present invention, the acceptability determination circuit determines whether or not the inserted coins can be accepted (i.e., continuous input and authenticity determination), and when it is determined that the coins can be accepted (i.e., genuine coins are not continuously input The flip-flop is set when it is determined that the
state, and the inserted coins are guided to the receiving passage.

When the sorting member is in the second state, that is, when the flip-flop is set, when an output is generated from the final stage coin detector, the flip-flop is reset and the sorting member is brought to the first state. .

Here, the sorting member is set to the second state when it is determined that the coin can be accepted, that is, it is not at least continuously inserted, so the preceding coin is accepted when the preceding coin is detected by the last coin detector. At the time when the coin passes through and the determination of acceptability is completed, the coin is separated from the subsequent coin by a predetermined distance or more, and at this time, the sorting member is kept in the second state for a predetermined period of time in order to accept the preceding coin. .

Therefore, the fact that an output is generated from the final stage coin detector when the sorting member is in the second state to accept the preceding coin means that the subsequent coin that was separated by a predetermined interval or more has a high speed. This indicates that the coin passes through the final stage coin detector and the determination as to whether or not it is acceptable is completed, and that the determination may indicate that the coin is acceptable. However, since there is a concern that such subsequent coins may be missorted, the reset means resets the flip-flop to put the sorting member in the first state and guide the subsequent coins to the return path.

Note that when the sorting member is set to the first state by the reset means, the preceding coins are being sorted into the receiving path. By appropriately determining the distance between the last stage coin detector and the last stage coin detector) and the distance between the last stage coin detector and the sorting member, the time point at which the sorting member is set to the first state by the reset means can be determined by the preceding coin. This can be ensured after being guided to the receiving passage.

〔Example〕

Next, one embodiment of the present invention will be described in detail based on the drawings.

Figure 1 is a schematic configuration diagram of a coin sorter, Figure 2 is a circuit diagram showing a bridge type sorting circuit using a sorting coil, and Figure 3 is a circuit diagram showing a coin detection unit that specifically detects specific coins with different diameters. Figure 4 is a circuit diagram for determining the authenticity of coins using the bridge method, Figure 5 is a circuit diagram for determining specific coins and continuous insertion, and Figure 6 is a circuit diagram for determining whether coins are genuine or counterfeit. 7 and 8 each show a waveform diagram of a specific circuit voltage.

In FIG. 1, 1 is a coin sorting machine main body, 11 is a coin input port, 12 is a rolling path that protrudes from the coin sorting machine main body 1 and forms a coin passage in which the inserted coins roll;
2 is connected to the iron core of an electromagnetic device (not shown) so as to be able to appear and retract from the main body 1 of the coin sorting machine.
It is arranged so that it can appear and retract from the top, and the inserted coins can be stored in the storage direction (acceptance path) A or the return direction (return path) B.
3 is a sorting coil arranged along the rolling path 12 of the input coins, SW ₁ is a coin detector with a receiving coil, SW ₂ and SW ₃ are coin detectors composed of light emitting diodes and phototransistors. Show the container. Here, the sorting coil 3, SW ₁ and SW ₂ are used as a coin detector for detecting the properties and passage of inserted coins to determine authenticity and continuous insertion. Then, the selection coil 3
As shown in the figure, the impedance _L0 on one side of the bridge circuit is configured. Further, as shown in FIG. 3, the coin detector SW ₁ includes a transmitting coil 42 connected to an oscillating circuit 41 and a receiving coil (hereinafter simply referred to as receiving coil SW ₁ ) facing the transmitting coil 41. When a coin is not present, a predetermined induced voltage is generated in the receiving coil SW ₁ , and when a coin is present between it and the transmitting coil 42, the induced voltage changes depending on the nature, diameter, and shape of the coin. It is configured. Coins inserted from the coin input port 11 shown in FIG.
The receiving coil SW ₁ is connected to the receiving coil SW 1 along the path shown by the dotted line above.
The coins pass through the sorting coil 3 and the coin detector SW ₂ in order to determine whether they are genuine or not and whether they have been continuously inserted.After that, if the inserted coins are genuine coins and are not continuously inserted, that is, if they can be accepted, the sorting member 2 passes the coins. Since the main body 1 is depressed from above, it is guided in the storing direction of arrow A and falls through the position of the coin detector SW ₃ , and if the inserted coins are counterfeit coins or continuous coins, that is, if the coins are not accepted, the sorting member 2 Since it remains protruding above the main body 1, it is guided in the return direction of arrow B.

The bridge circuit with the selection coil 3 as one side is the second
It is configured as shown in the figure. In Fig. 2, L ₀ is the impedance of the sorting coil 3, L ₁ ,
R ₁ is a standard inductance and a standard resistance determined according to the properties of the coins to be sorted, and these are used as standard impedance. Connection point of resistors r ₁ and r ₀ and impedance L ₀ and impedance L ₁
An oscillator ω ₀ is connected to the connection point of . The output end of the bridge circuit is connected to the operational amplifier through the resistor _R3 .
It is connected to one input of OP ₁ , and the input of this operational amplifier is grounded. A diode D 2 is connected between the output of the operational amplifier OP ₁ and one input of its amplifier OP ₁ , and a diode D ₂ is connected between the cathode of the diode D ₁ connected to the output of the operational amplifier OP 1 and one of the inputs of its amplifier OP _{1 .} A smoothing capacitor with one end grounded and a resistor _r4 connected between it and one input terminal.
C ₁ is connected. This operational amplifier OP ₁ , resistor
A rectifying and smoothing circuit 31 is configured by r ₃ , r ₄ , diodes D ₁ , D ₂ and smoothing capacitor C ₁ .
The output of the rectifying and smoothing circuit 31 is connected via a resistor _r5 to one input terminal of an operational amplifier _OP2 , and the other input terminal of this operational amplifier _OP2 is connected to a predetermined reference voltage via a resistor _r6 . COM is applied and connected to its output via resistor _r7 . A comparator circuit 32 is constituted by the operational amplifier _OP2 . In the circuit shown in Figure 2, the bridge circuit outputs a large unbalanced voltage when there is no coin at the position of the sorting coil 3, and when a genuine coin passes the position of the sorting coil 3, the impedance of the sorting coil increases.
L ₀ changes and balances, and the output of the bridge circuit becomes zero. The output of the bridge circuit is rectified and smoothed in a rectification and smoothing circuit 31, and compared with a predetermined reference voltage COM close to zero potential in a comparison circuit 32.
When the output of the bridge circuit approaches zero potential and becomes lower than a predetermined reference voltage COM, the comparison circuit 32 outputs a selection signal S.

FIG. 3 shows a circuit diagram of a coin detection unit equipped with the receiving coil SW ₁ shown in FIG. 1. In FIG. 3, the receiving coil SW ₁ is arranged opposite to the transmitting coil 42 connected to the oscillator 41, and the inserted coin CN can pass between the receiving coil SW ₁ and the transmitting coil 42. One end of the receiving coil SW ₁ is grounded, and the other end includes an operational amplifier OP ₆ , resistors r ₁₁ , r ₁₂ , and a diode.
A rectifying and smoothing circuit 43 consisting of D ₃ , D ₄ and a smoothing capacitor C ₃ is connected, and the induced voltage generated in the receiving coil SW ₁ is rectified and smoothed. Rectifier smoothing circuit 43
The output of is connected to a window comparator 44 and a comparison circuit 45. The window comparator 44 receives the output of the rectifying and smoothing circuit as one input, and receives a predetermined first reference voltage COM ₁ and a second reference voltage as the other input, respectively.
Two operational amplifiers OP ₃ , OP ₄ given COM ₂
The output ends of the amplifiers OP ₃ and OP ₄ are connected to the connection point between the resistor R and the capacitor C ₂ connected in series between the positive power supply +V and the negative power supply -V. This window comparator 44 is a rectifier smoothing circuit 43
The output voltage of amplifier OP ₃ is the first reference voltage COM ₁
and the second reference voltage COM ₂ of the amplifier OP ₄ , and if this state lasts for a time determined by the time constants of the resistor R ₂ and the capacitor C ₂ , it will issue an output. Also, a comparison circuit consisting of an operational amplifier OP ₅ with the output of the rectifying and smoothing circuit 43 as one input and a predetermined third reference voltage COM ₃ given as the other input, and resistors r ₈ , r ₉ , r ₁₀ The circuit 45 generates an output when the output voltage of the rectifying and smoothing circuit 43 falls below the third reference voltage _COM3 . The output of this comparison circuit 45 is connected to one input terminal of a NOR circuit NOR ₁ via an inverting circuit NOT ₁ , and the output terminal of the window comparator 44 is connected to the other input terminal of this NOR circuit NOR ₁ . connected via. The output SP ₁ of this NOR circuit NOR ₁ is used as an input coin detection signal and a specific coin selection signal.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the waveform diagram shown in FIG. 7a shows the output V ₁ of the rectifying and smoothing circuit 43, FIG. 7b shows the output V ₂ of the window comparator 44, FIG. 7c shows the output V ₄ of the Schmitt trigger circuit 46, and FIG. 7d shows the comparison circuit 45.
The output V ₃ and Figure 7 e are the outputs of the NOR circuit NOR ₁ .
Showing SP ₁ . In Figure 7a, the horizontal axis is time t,
The vertical axis indicates the output voltage, and V _C indicates the standby voltage induced in the receiving coil SW 1 in the standby state when there is no inserted coin between the transmitting coil 42 and _{the receiving coil SW 1 .} V _COM3 is a voltage slightly lower than the standby voltage V _C and represents the third reference voltage COM ₃ of the comparator circuit 45. V _COM1 and V _COM2 are window comparators 44
represents the first and second reference voltages COM ₁ and COM _{2 of COM 1 and COM 2} .

Transmitting coil 42 and receiving coil SW ₁ shown in Fig. 3
When there is no inserted coin between the receiving coil SW 1 and the receiving coil SW 1 , a standby voltage V _C is induced in the receiving coil SW ₁ by the magnetic field formed by the transmitting coil 42 . When a specific coin enters the magnetic field formed by the transmitting coil 42, the voltage induced in the receiving coil _SW1 by the specific coin gradually attenuates. At this time, the output V ₁ obtained by rectifying and smoothing the voltage induced in the receiving coil SW ₁ by a specific coin is shown by a solid line in Figure 7a, and the voltage induced in the receiving coil SW ₁ by a coin with a small diameter unlike the specific coin is shown by a solid line. The output V ₁ obtained by rectifying and smoothing the voltage is shown by a dashed line, and the output V ₁ obtained by rectifying and smoothing the voltage induced in the receiving coil SW ₁ by a large-diameter coin is similarly shown by a dotted line. The voltage induced in the receiving coil SW ₁ due to the entry of a specific coin is attenuated, and the output V ₁ becomes the third reference voltage of the comparator circuit 45.
When the voltage falls below COM ₃ , the comparator circuit 45 generates an output V ₃ as shown in FIG. 7d. Next, the specific coin passes between the transmitting coil 42 and the receiving coil SW ₁ , the voltage induced in the receiving coil SW ₁ is attenuated, and the output is
A state in which V ₁ is lower than the second reference voltage COM ₂ of the window comparator 44 and does not fall below the first reference voltage COM ₁ , that is, the output V ₁ is at the first reference voltage.
If the condition existing between COM ₁ and the second reference voltage COM ₂ continues for a predetermined time determined by the time constants of resistor R ₂ and capacitor C ₂ , the window comparator 44 outputs a signal as shown in FIG. 7b. Output V ₂ is emitted. Output of window comparator 44
_V1 is waveform-shaped into a rectangular wave by the Schmitt trigger circuit 46, and an output _V4 as shown in FIG. 7c is guided from the Schmitt trigger circuit 46 to one input terminal of the NOR circuit _NOR1 . Since the signal obtained by inverting the output V ₃ of the comparator circuit 45 by the inverting circuit NOT ₁ is led to the other input terminal of the NOR circuit NOR ₁ , the NOR circuit
The output SP ₁ of NOR ₁ becomes two pulse signals as shown in FIG. 7e. The output of this NOR circuit NOR ₁
SP ₁ is used as a detection signal to detect the passage of a coin, and when two pulse signals appear as this detection signal, it is determined as a specific coin. An example will be explained. In the case of a coin other than a specific coin, for example, if the output V _{1 of} the waveform shaping circuit 43 changes as shown by the dashed line in FIG _. A single pulse having a width equal to the period of rotation is transmitted as the detection signal _SP1 via the NOR circuit _NOR1 . Furthermore, if _the output V ₁ changes as shown by the dotted line in FIG.
A pulse having a width corresponding to the period during which the third reference voltage COM ₃ is below the third reference voltage COM 3 is transmitted as a detection signal.
At this time, the output V ₁ shown by the dotted line has a period that exists between the first reference voltage COM ₁ and the second reference voltage COM ₂ of the window comparator 44, but this period is between the resistor R ₂ and the capacitor C ₂ . Since the time is shorter than the predetermined time determined by the time constant of , the output V ₂ is not generated or is small. Therefore, since the output V ₂ does not reach the trigger level of the Schmitt trigger circuit 46, the output V ₄ of the Schmitt trigger circuit 46 is not generated. In this manner, the coin detection section detects the inserted coin and issues a detection signal, emitting two pulses when a specific coin is inserted, and emitting one single pulse when other coins are inserted.

Next, the determination of the authenticity of coins will be explained. First, a case will be described in which the authenticity is determined by detecting the passing position of the inserted coin and setting a sorting period. Fourth
The figure shows an authenticity determination circuit, and the terminal IN is connected to the output terminal of the comparison circuit 32 shown in FIG. terminal
SW ₁₁ and SW ₂₁ indicate the input terminals for the coin detection signal, and the terminal SW ₁₁ is connected to the NOR circuit NOR ₁ in Fig. 3.
terminal SW ₂₁ is connected to the output end of the coin detector.
Connected to SW ₂ . The terminal IN is connected to a clock pulse input terminal CL of a JK flip-flop FF ₁ (hereinafter referred to as FF ₁ ), and the J and K terminals of FF ₁ are connected to a positive power supply +V and a negative power supply -V, respectively. The Q terminal of FF ₁ is connected to one input terminal of an AND circuit AD ₁ , and the other input terminal of this AND circuit AD ₁ is connected to the clock pulse input terminal CL of FF ₁ .
The signal input to the is guided.
The output terminal of the AND circuit AD ₁ is connected to the S terminal of the R-S flip-flop FF ₂ (hereinafter referred to as FF ₂ ), and the terminal of this FF ₂ is an AND circuit whose one input is the output from the Q terminal of FF ₁ . Connected to the other input end of AD ₂ . Terminal for inputting coin detection signal SP ₁
SW ₁₁ is connected to the S terminal of FF ₃ , and the Q terminal of FF ₃ is connected to the input terminal of timer _TM1 .
On the other hand, the terminal SW ₂₁ is connected to the other input terminal of an OR circuit OR ₁ which has the output of the timer TM ₁ as one input, and the output terminal of this OR circuit OR ₁ is connected to the R terminal of FF ₃ and also serves as an inverting circuit. AND circuit through NOT ₂
Connected to one input end of AD ₃ . The output of the terminal of FF ₃ is led to the other input terminal of this AND circuit AD ₃ , and the output terminal of the AND circuit AD ₃ is connected to FF ₁ and
Connected to the R terminal of FF ₂ .

To explain the operation of this circuit, in the standby state, the output of the OR circuit OR ₁ is in the logic signal "0" state (hereinafter simply referred to as "0"), and the FF ₁ is in the reset state, so the AND circuit The AND condition of AD ₃ is satisfied. As a result, R of FF ₁ and FF ₂
Logic signal “1” on the terminal (hereinafter simply referred to as “1”)
is given, FF ₁ and FF ₂ are in the reset state. When a coin is inserted into the coin slot ₁₁ shown in FIG.
Since it passes through the position of , the NOR circuit shown in Figure 3
From NOR ₁ , a detection signal SP ₁ as shown in section () in FIG. 8a is led to terminal SW ₁₁ . Detection signal SP _1
FF3 is set by This will cause the timer
TM ₁ starts time-limited operation and “0” is applied to the FF ₃ terminal.
appears, so the reset input applied from the AND circuit _AD3 to _FF1 and _FF2 is canceled (the reset signal RES disappears). After the reset inputs of FF ₁ and FF ₂ are released, the selection period begins as shown in FIG. 8d. The above coin is inserted into the receiving coil.
After passing through the SW ₁ position, the selection coil 3 is reached, so the balanced state of the bridge circuit is detected by the circuit shown in Figure 2, and a selection signal as shown in Figure 8e is sent from the comparison circuit 32 to the terminal IN. S is given.
When the selection signal S is led to the clock pulse input terminal CL of FF ₁ via the terminal IN, FF ₁ is set and sends "1" to one input terminal of each of the AND circuits AD ₁ and AD ₂ . Since the AND condition is satisfied on the condition that FF ₂ is not set, the AND circuit AD ₂ outputs a determination signal SJ as shown in FIG. 8(f). At this time, when FF ₂ is inserted with a coin that is made of the same material as the genuine coin and has a diameter larger than that of the genuine coin, the bridge circuit is balanced twice and two pulses are sent to the terminal IN as the sorting signal S. Since you will be inputting
Set on that second pulse. That is, FF ₁ is set when the selection signal S appears only once, and FF ₂ is set when the selection signal S appears twice or more. Therefore, the selection signal S is 2
If it appears more than once, _FF2 is set, so the AND circuit _AD2 no longer sends out the determination signal SJ.
When FF ₁ is set, a judgment signal SJ is sent from the AND circuit AD ₂ , and this judgment signal SJ is processed by performing an AND operation with the coin detector SW ₂ .

When the input coin that has passed through the position of the sorting coil 3 is next moved to the position of the coin detector SW ₂ , the coin detector
A detection signal SP ₂ is applied from SW ₂ to a terminal SW ₂₁ .
This detection signal SP ₂ is guided to the R terminal of FF ₃ via an OR circuit OR ₁ , and is also guided to one input terminal of an AND circuit AD ₃ via an inverting circuit NOT ₂ . _FF3
At the same time as is reset, "1" is applied from that terminal to the other input terminal of the AND circuit AD ₃ , but since the AND circuit AD ₃ is provided with the inverted signal of the detection signal SP ₂ , the AND circuit In AD ₃ , the AND condition is not satisfied until the detection signal SP ₂ disappears. After the detection signal SP ₂ disappears, the AND condition of the AND circuit AD ₃ is satisfied, and as a result, the reset signal RES is sent to FF ₁ and FF ₂ . When FF ₁ and FF ₂ are reset, the selection period ends as shown in section () in FIG. 8d. In this way, only FF ₁ is set during the selection period from when the detection signal SP ₁ is generated and FF ₁ and FF ₂ are reset to when FF ₁ and FF ₂ are reset by the detection signal SP ₂ . The truth or falsity is determined based on whether or not both FF ₁ and FF ₂ are set. Note that the time limit of the timer TM ₁ is set longer than the sorting period, and is used when the inserted coin does not reach the position of the coin detector SW ₂ . When the return lever that is operated when the user wishes to return the inserted coin is operated, the inserted coin is returned without reaching the position of the coin detector SW ₂ , so in such a case, the timer TM ₁ is not activated. It transmits the output TIM to reset the up-down counter UD shown in FIG. 5, and also resets FF ₃ via the OR circuit OR ₁ to return to the standby state.

Next, the determination of a specific coin and the determination of continuous insertion based on the detection signal from the coin detection section shown in FIG. 3 will be described below. FIG. 5 shows such a determination circuit, in which SW ₁₁ and SW ₂₁ again represent the input terminals of the detection signal SP ₁ and the detection signal SP ₂ ,
TIM represents the output signal of timer _TM1 shown in FIG. Terminal SW ₁₁ is connected to the other input terminal of OR circuit OP ₂ which has one input as the output of AND circuit AD ₄ , and the output of this OR circuit OR ₂ is connected to clock pulse input terminal CL of up-down counter UD. There is. Output Q ₁ of up-down counter UD,
The Q ₂ and Q ₃ terminals are connected to the inputs of the NOR circuit NOR, and the output of this NOR circuit is the judgment signal.
The inversion circuit is simultaneously transmitted as CNT NOT ₄
The judgment signal CNT is applied to one input terminal of the AND circuit _AD4 via the circuit AD4. The other input terminal of the AND circuit _AD4 is connected to a terminal _SW21 , and its output terminal is connected to an addition/subtraction command terminal U/D of an up-down counter UD via an inverting circuit _NOT3 . The reset terminal R of the up-down counter UD has a fourth
The output TIM of timer _TM1 shown in the figure is derived.

When no coins are inserted from the coin slot 11 shown in Fig. 1, the up-down counter UD is
Since "0" appears at the Q ₁ , Q ₂ , and Q ₃ terminals, the output of the NOR circuit NOR ₂ is "1", and this output is sent to one input of the AND circuit AD ₄ via the inverting circuit NOT ₄ . is given "0". Since the detection signal SP ₂ is not input via the terminal SW ₂₁ , the output of the AND circuit AD ₄ is "0", and therefore the up-down counter is input via the inverting circuit NOT ₃ .
"1" is given to the addition and subtraction command terminal U/D of UD. Here is the updown counter UD
When "1" is input to addition/subtraction command terminal U/D, addition operation is performed, when "0" is input, subtraction operation is performed, and in the above state, addition operation is performed. . Coin slot 1 shown in Figure 1
_{If only one specie coin is inserted from 1 to 1, and this coin reaches the position of receiving coil SW 1 ,} a detection signal as shown in the section of FIG. SP ₁ connects up/down counter via terminal SW ₁₁ and OR circuit OR ₂
The up-down counter is given to the UD terminal CL.
UD adds this. As a result, "1" appears at the Q terminal of the up-down counter UD, so the output of the NOR circuit NOR ₂ becomes "0" and becomes an inverting circuit.
“1” is applied to one terminal of the AND circuit AD ₄ via NOT ₄ . Next, the inserted coin is detected by the coin detector.
When the position SW ₂ is reached, a detection signal SP ₂ as shown in the section of FIG. 8b is applied to the AND circuit AD ₄ , so that the AND condition of the AND circuit AD ₄ is satisfied.
When the AND condition of the AND circuit _AD4 is established, "0" is input to the addition/subtraction command terminal U/D of the up-down counter UD via the inverting circuit NOT ₃ , and the up-down counter UD enters the subtraction mode. on the other hand,
The output of the AND circuit _AD4 is applied to the terminal CL via the OR circuit _OR2 , causing the up-down counter UD to be subtracted. This causes the up-down counter UD
``0'' appears at the Q <sub>1</sub> terminal of , and the output of the NOR circuit NOR <sub>2</sub> becomes ``1''. Detection signal SP ₂ disappears or
Or, at the same time when the output of the NOR circuit NOR becomes "1", the AND condition of the AND circuit _AD4 no longer holds true, so its output becomes "0", and "1" is sent to the addition/subtraction command terminal U/D of the up-down counter UD. Give it, put it in addition mode, and return to standby state.

Next, when a specific coin is inserted from the coin slot 11 shown in FIG.
When the position of SW ₁ is reached _, two pulse detection signals SP ₁ as _shown in the section in _FIG . It is led to the clock pulse input terminal CL of UD. As a result, the up-down counter UD adds up the detection signal _SP1 and sends "1" from its _Q2 terminal, so the output of the NOR circuit _NOR2 becomes "0". receiving coil
When the coin that has passed through the position SW ₁ reaches the position of the coin detector SW ₂ , a single pulse detection signal SP ₂ as shown in the section of FIG. 8b is input to the terminal SW ₂₁ .
As a result, the AND circuit _AD4 satisfies the AND condition, so it applies "0" to the addition/subtraction command terminal U/D of the up-down counter UD via the inverting circuit NOT ₃ , thereby placing the up-down counter UD in a subtraction mode. On the other hand, the output "1" of the AND circuit _AD4 is led to the up-down counter UD via the OR circuit _OR2 , so the up-down counter UD receives the detection signal.
SP ₂ is subtracted, but the up-down counter UD is the detection signal SP ₂ is subtracted, but the up-down counter is
The count content of UD is not zero and "1" is sent to the _Q1 terminal. As a result, the output of the NOR circuit NOR ₂ remains at "0". Therefore, by ANDing the output of the NOR circuit NOR ₂ and the detection signal SP ₂ , it can be determined that the detection signal SP ₁ has occurred twice or more. The above explained the operation when a specific coin is inserted, but before the detection signal SP ₂ is generated from the coin detector SW ₂ , two pulses are transmitted as the detection signal SP ₁ from the receiving coil SW ₁ . The same applies when coins are continuously inserted at such intervals.

The acceptability of the inserted coins is determined based on the above-mentioned determination of the authenticity of the inserted coins, determination of specific counterfeit coins, and determination of continuous insertion. The sorting member 2 shown in is controlled to sort the inserted coins into the storage direction A or the return direction B. Next, control of the distribution member 2 will be explained using the circuit diagram shown in FIG. 6. FIG. 6 shows the distribution control circuit of the distribution member 2, and in the figure, SW ₂₁ and SW ₃₁ are detection signals transmitted from coin detectors SW ₂ and SW ₃ , respectively.
The input terminals of SP ₂ and SP ₃ , SJ ₁ are the input terminals of the judgment signal SJ connected to the output terminal of the AND circuit AD ₂ shown in Fig. 4, and CNT ₁ is the NOR circuit shown in Fig. 5.
It is connected to the output terminal of NOR ₂ and indicates the input terminal of the judgment signal CNT. Input terminals SW ₂₁ , SJ ₁ , and CNT ₁ are each connected to an input terminal of an AND circuit AD ₅ , and an output terminal of this AND circuit AD ₅ is connected to a clock pulse input terminal CL of FF ₄ . The J and K terminals of FF ₄ are connected to the positive power supply +V and negative power supply -V, respectively.
The Q terminal of FF ₄ is the control signal sending terminal G and timer.
AND circuit AD ₆ is connected to the input end of TM ₂ , and one input end is connected to terminal SW ₂₁ , and one input end is connected to terminal SW ₃₁ .
Connected to the other input of AD ₇ . The R terminal of FF ₄ has the output of timer TM ₂ and the AND circuit AD _6.
When the outputs of are respectively input, the output terminal of the OR circuit OR ₃ is connected. The output terminal of the AND circuit _AD7 is connected to the S terminal of the FF ₅ , and the Q terminal of the FF ₅ is connected to the coin counting signal sending terminal _CN10 and also to the input terminal of the timer _TM3 . The output terminal of timer _TM3 is connected to the R terminal of _FF5 .

In such a distribution control circuit, FF ₄ and FF ₅ are in a reset state in a standby state.
A specie coin is inserted from the coin slot 11 and the eighth coin is inserted.
The judgment signal SJ as shown in the division in figure f is sent to terminal SJ _1.
, and a judgment signal CNT as shown in the section h in Figure 8 is input to terminal CNT ₁ .
When the inserted coin reaches the position of coin detector SW ₂ , the 8th
The detection signal SP ₂ as shown in the division in figure b is the terminal
By inputting to SW ₂₁ , the AND condition of AND circuit AD ₅ is established. As a result, FF ₄ is set, so that "1" is sent from its Q terminal to G as a control signal as shown in the section j of FIG. 8, and the distribution member 2 shown in FIG. The separator body 1 is depressed by the device. Therefore, the inserted coins fall in the storage direction A without being prevented from falling by the sorting member 2.
When the position of the coin detector SW ₃ is reached, a detection signal SP ₃ as shown in the section of FIG. 8c is applied to one input terminal of the AND circuit AD ₇ via the terminal SW ₃₁ . At this time, the other input terminal of AND circuit _AD7 is
Since "1" is applied to the Q terminal of FF ₄ , the AND condition is satisfied and FF ₅ is set. When FF ₅ is set, "1" is sent from the Q terminal to the terminal CN ₁₀ as a coin signal as shown in section k of FIG. 8, and the timer TM ₃ starts time-limiting operation.
Reset FF ₅ after a predetermined time. FF ₄ Q
The timer TM ₂ , which starts its time-limited operation after "1" is generated at the terminal, resets the FF ₄ after a set time limit that is slightly longer than the time required for the inserted coin to pass through the position of the sorting member 2 has elapsed. .

Next, when a specific coin is inserted or coins are continuously inserted, the judgment signal CNT becomes "0" as shown in the section h in Figure 8, so the AND condition of AND circuit AD ₅ no longer holds true. . Therefore, since the FF ₄ continues in the reset state, the control signal for the distribution member 2 sent through the terminal G remains at "0" as shown in the section of FIG. 8j. Therefore, the sorting member 2 protrudes above the sorting machine main body 1, and the coins falling through the rolling path 12 are prevented from falling by the sorting member 2 and are returned in the return direction B.
be led to. In addition, FF ₁ and FF ₂ shown in Figure 4
If both are set within the screening period,
When the detection signal SP ₂ is generated, the judgment signal SJ is as shown in Fig. 8 f.
As shown in the classification, it is "0", so the AND condition of AND circuit AD ₅ is not satisfied in this case as well, and the input coins are returned in the return direction B by the sorting member 2.
be led to. Then, in the same way as when the inserted coin does not reach the position of the coin detector SW ₂ due to the operation of the return lever, the timer TM ₁ shown in Fig. 4 operates for a limited time and outputs as shown in the section g of Fig. 8. The up-down counter UD shown in FIG. 5 is reset and the system returns to the standby state.

Next, an explanation will be given of the operation when subsequent coins are inserted at intervals that are not determined to be continuous insertion in the above-described continuous insertion determination, and the rolling speed of the subsequent coins is high.

In FIG. 6, AND circuit AD ₆ receives the output terminal Q of FF ₄ and the output (SP ₂ ) of coin detector SW ₂ as input, and the output of AND circuit AD ₆ is connected to FF ₄ via OR circuit OR ₃ . Connected to reset input terminal R. Therefore, first, when the preceding coin (specified coin) passes through the coin detector SW ₂ and the detection signal SP ₂ is generated,
Since the subsequent coin has not reached the position where it is detected by the coin detector SW ₁ , the AND condition of the AND circuit AD ₅ is satisfied, and when the detection signal SP ₂ falls, FF ₄ is set, and the sorting member 2 detects the inserted coins. are sorted in the storage direction A. At this time, since one of the inputs of the AND circuit _AD6 is set to "0", the output "1" is not generated from the AND circuit _AD6 . After that, the subsequent coin rolls at a faster speed (an output signal is generated from Timer TM ₂ ).
If the coin passes through the coin detector SW ₂ (before FF ₄ is reset), the AND condition of the AND circuit AD ₆ is satisfied, the output resets FF ₄ , and the sorting member 2 sends the input coins in the return direction B. It is said to be in a state of distribution. Therefore, if the interval between the coin detectors SW ₁ and SW ₂ is set to a sufficient interval (shorter than the interval required for sorting by denomination) for sorting the input coins by the sorting member 2, the preceding coins will Subsequent coins that are accepted and no longer have the necessary interval for denomination distribution with respect to the preceding coins are returned.

In the above embodiment, the coin detector SW ₂ only detects the passing of a coin;
It goes without saying that the coin properties may also be detected using the SW ₁ or the sorting coil 3. Here, the plurality of coin detectors of the present invention include a coin detector
SW ₁ , sorting coil 3 and coin detector SW ₂ , the acceptance judgment circuit is as shown in Figs. 2 and 3.
The flip-flop is composed of the flip-flop _FF4 of FIG. 6, the timer is composed of the timer _TM2 of FIG. ₆ , The reset means is constituted by an AND circuit _AD6 shown in FIG.

〔Effect of the invention〕

According to the present invention as described above, when a detection signal is generated from the final stage coin detector while the input coin sorting member is in the state of sorting the input coins in the storage direction, the sorting member is inserted. Since the subsequent coins are returned after the coins are sorted in the return direction, the rolling speed of the subsequent coins is If the succeeding coins quickly catch up with the preceding coins during the sorting operation and there is no longer the interval necessary for sorting the denominations, the preceding coins are accepted but the succeeding coins are returned. Therefore, it is possible to prevent incorrect sorting of subsequent coins and coin jams, and to ensure reliable sorting of inserted coins.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the arrangement of a coin detector and sorting member, etc. of the present invention, and FIGS. 2 to 5 are circuit diagrams showing an embodiment of the acceptance determination circuit of the present invention. FIG. 6 is a circuit diagram showing an embodiment of the flip-flop and reset means of the present invention, and FIGS. 7 and 8 are waveform diagrams showing the operation of this embodiment. 1... sorting machine main body, 2... sorting member, 3,
SW ₁ , SW ₂ ...Selection coil and coin detector as a coin detector, 11...Coin slot, 12...Rolling path, A...Accepting path, B...Returning path, FF ₄ ...Flip-flop, TM ₂ ...Timer, AD ₆ ...AND circuit as a reset means.

Claims (1)

[Claims] 1. A rolling path on which coins inserted from a coin insertion slot roll, a plurality of coin detectors that are sequentially provided along the rolling path and detect the properties or passage of the inserted coins, and the plurality of coins. an acceptability determining circuit that integrates the outputs of the detector and determines acceptability based on the continuous input of the input coins and authenticity; a flip-flop that is set based on the acceptability determination of the circuit; and the flip-flop is set. a timer for resetting the flip-flop after a predetermined time; a distributing member that distributes the input coins by being set in a first state by a reset output of the flip-flop and in a second state by a set output; a return path through which the input coins are guided; a reception path through which the input coins are guided depending on the second state of the sorting member; a set output of the flip-flop; and an output of the final stage of the plurality of coin detectors. and a reset means for resetting the flip-flop by the AND output of the coin sorting device.