JPH0223052B2 - - Google Patents

Description

[Detailed Description of the Invention] This invention mainly relates to two
The present invention relates to an automobile radio receiver having two receiving systems, and particularly relates to the configuration of an identity determiner that determines whether audio signals from the two receiving systems are the same.

In this type of car radio receiver, under the control of a microcomputer, one receiving system receives the broadcast, while the other receiving system searches for a station with better reception, and an identity determiner determines whether the broadcast content is the same. By determining whether the broadcast content is the same or not, and selecting and receiving stations with the same broadcast content and better reception condition, the listener's It is possible to automatically continue receiving the same broadcast program in good reception condition without any trouble.

FIG. 1 shows an example of this type of radio receiver. In the figure, 1 is an antenna, 2 is a distributor, 3 is a channel selection device, 4 is an intermediate frequency amplifier, 5 is a detector, and 6 is a first
(hereinafter referred to as receiving system A), 7 is a tuning device 8 is an intermediate frequency amplifier, 9 is a detector, 10 is a second receiving system (hereinafter referred to as receiving system B), 11 is an audio signal 12 is a low frequency amplifier, 13 is a speaker, 14 is a first electric field detector, 15 is a second electric field detector, 16 is an identity determination device, 17 is a control device 1
8 is a frequency display, and 19 is an operation key. In the radio receiver configured as above, antenna 1
The broadcast wave signal induced by the splitter 2 is divided into two parts and given to the receiving system A6 and the receiving system B10. The tuning devices 3 and 7 are, for example, PLL synthesizer electronic tuners, which receive frequency data from the control device 17, convert only broadcast waves of that frequency into intermediate frequency signals, and output the signals. Intermediate frequency amplifiers 4 and 8 amplify this intermediate frequency signal and provide it to detectors 5 and 9. Detectors 5 and 9 detect intermediate frequency signals and output audio signals. In this way, one of the audio signals obtained from receiving system A6 and receiving system B10 is selected by audio signal switch 11, amplified by low frequency amplifier 12, and reproduced by speaker 13. The electric field detectors 14 and 15 detect the reception level of each broadcasting station being received by the reception system A6 and the reception system B10, respectively, and provide a corresponding signal to the control device 17. This is to determine whether or not audio signals from two receiving systems have the same content. Control device 17
is composed of, for example, a microcomputer, and in addition to controlling the received frequency and displaying it on the frequency display 18 in response to operations on the operation keys 19, it also performs an automatic tuning operation for the same broadcast content station. This automatic channel selection operation is performed as follows, for example. First, it is assumed that a certain station is received by the receiving system A6 by a listener's manual operation and is being reproduced through the audio signal switch 11. At this time, the control device 17
At step 10, the reception frequency is scanned over the entire broadcast frequency band, and a station whose reception level is higher than the station being received by the reception system A6 is searched from the signals of the electric field detectors 14 and 15. From this result, if there is a station with a high reception level, that is, a station with good reception conditions, it is determined using the identity determination device 16 whether or not the audio signals from the two reception systems have the same content. As a result, if it is determined that they are not the same, scanning by the receiving system B10 is continued, and if it is determined that they are the same, the audio signal switch 11 is set to the receiving system B10 side, and the receiving system B10
While reproducing the output audio signal, the frequency display 18 displays the receiving frequency of the receiving system B10.
Furthermore, the receiving system A6 continues scanning the receiving frequency, which has been performed by the receiving system B10. As a result of the above operation, all stations in the broadcasting frequency band with better reception than the station currently being received will be tested, even if there are several stations with the same broadcast content.
Among them, the station with the best reception status continues to be received.

Conventionally, there has been an identity determining device shown in FIG. 2 used in this type of radio receiver. In the figure, 30 and 31 are low-pass filters, 32 and 33 are zero cross detectors, 42 and 43 are shift registers,
44 is a clock generator; 34, 35, and 46;
is an exclusive OR circuit (hereinafter referred to as E-OR circuit),
35, 47, and 48 are integrators, 49, 50 are combiners, 36 is a first voltage comparator, 37 is a second voltage comparator, 38, 39 are detectors, and 40, 41 are voltage comparators. . In the identity determiner 16 configured as described above, the receiving system A6 and the receiving system B
The audio signals from 10 are each passed through a low-pass filter 3.
After high frequency components are removed by 0 and 31, the signal is applied to zero cross detectors 32 and 33. The zero cross detectors 32 and 33 output binary signals from "H" level to "L" level, depending on the sign of the AC component of the input signal.
That is, it outputs a zero-crossing wave. E-OR circuit 34, 45, 46 and integrator 35, 47, 4
8 converts the degree of coincidence between these two zero-crossing waves into a DC signal level and outputs it, and the shift registers 42 and 43 are connected to E-OR circuits 45 and 43, respectively.
46, one of the zero crossing waves is delayed. Next, the operations of the E-OR circuit 34 and the integrator 35 will be described first. The E-OR circuit 34 outputs an "L" level when two inputs, that is, two zero-crossing waves given from the zero-crossing detectors 42 and 43, are both "H" or both "L"; When the other is “L”, it outputs “H” level, and the integrator 35 outputs this E
-It integrates the output of the OR circuit 34 for a predetermined period. Therefore, when the two audio signals given to the identity determiner 16 are exactly the same: the outputs of the zero cross detectors 32 and 33 simultaneously become "H" level or "L" level, and the output of the E-OR circuit 34 becomes:
The level becomes "L" almost continuously, and the output of the integrator 35 also becomes almost equal to the "L" level. Furthermore, when the two audio signals have the same content and are in opposite phases, the outputs of the zero cross detectors 32 and 33 are always at the "H" level while the other is at the "L" level, and the output of the E-OR circuit 34 is “H” almost continuously
level, and the output of the integrator 35 also becomes approximately equal to the "H" level. Next, if the contents of the two audio signals are different, the above relationship does not exist between the two outputs of the zero cross detectors 32 and 33, and if enough time is taken, they will become "H" or "L" level at the same time. The period and the period in which one is at "H" level and the other is at "L" level become almost equal. For this reason E-
Considering an appropriate period, the output of the OR circuit 34 will be "H" for approximately 1/2 of the period and "L" for the remaining period.
becomes. Therefore, the output of the integrator 35 becomes approximately an intermediate value between the "H" level and the "L" level.

From this, if a sufficient integration period is provided, whether or not the contents of the two audio signals are the same will clearly appear as the output of the integrator 35.

Next, a case will be described in which two audio signals from receiving system A6 and receiving system B10 have the same content but have a time difference τ. Here, let us consider the case where T>2τ, where the above two audio signals are a repeating wave with a frequency f and a period T (T=1/f).

First, if the two audio signals are in phase, during the period T
Since the outputs of the zero cross detectors 32 and 33 do not match for a period of 2τ, the output eo of the integrator 35 becomes approximately eo = 2τ/TV _H = 2fτV _H ...(1), and when the two audio signals are in opposite phase, During a period T, a period zero cross detector 32 of 2T,
Since the outputs of the integrator 33 match, the integrator 35 output eo is approximately eo = (1-2τ/T)V _H = (1-2fτ)V _H ...(2), and both are ideal without time difference. The accuracy of the judgment will be lowered as the result deviates from the normal case. E
-OR circuits 45, 46 and integrators 47, 48 are provided to prevent a decrease in judgment accuracy due to this time difference τ, and E-OR circuits 45 and 4
One of the zero-crossing waves applied to the waveform 6 is delayed by a time t in advance by shift registers 42 and 43, and output for judgment is obtained from the integrators 47 and 48 as described above. Here, the delay time t in the shift register is determined by the number of stages of the shift register being n, and the clock frequency from the clock generator 44.
If fc _LK , then t=n/fc _LK . In addition, by appropriately selecting the number of shift register stages, the clock frequency fc _LK can be adjusted to the low frequency filter 3.
It is considered that by setting the cutoff frequency sufficiently higher than the cutoff frequency of 0 and 31, the two zero crossings in the shift registers 42 and 43 are hardly modified and only a delay is given.

As a result, the output e ₁ of the integrator 47 and the output e ₂ of the integrator 48 are determined by the time difference between the two audio signals (receiving system A6
The best judgment result is given when the delay time of the audio signal from the receiving system B10 is t and -t, respectively, based on the audio signal from the receiving system B10. Figure 3 shows t=
This is a graph showing this situation with the frequency f being 250 [Hz] and 500 [Hz], and the outputs of the integrators e ₀ , e ₁ , e ₂ relative to the time difference τ. Furthermore, for two audio signals with different contents, no correlation is caused by giving a delay time t, so if a sufficient integration time is given, the outputs e ₁ and e ₂ of the integrators 47 and 48 will be approximately 1/2V _H becomes. Therefore, in the case shown in FIG.
If the high-frequency components above 500 [Hz] are sufficiently attenuated at 0.31, the time difference τ = ±1.2 [ms].
It can be seen that identity determination can be performed with high accuracy using any of the outputs of the integrators 35, 47, and 48 within the range of .

Next, the synthesizer 49 is configured to receive the outputs of the integrators 35, 47, and 48 and always output the maximum value of them, and the voltage comparator 36 is configured such that the synthesizer output is at the first judgment level eth ₁ ( Here, eth ₁ is an appropriately determined value in the range of approximately 1/2 V _H < eth ₁ < V _H. The synthesizer 50 is configured to receive the outputs of the integrators 35, 47, and 48 and always output the minimum value thereof, and the voltage comparator 37 is configured so that the synthesizer output is at the second judgment level eth ₂ (Here eth ₂ is 0<eth ₂ <
It is an appropriately determined value within the range of 1/ _2VH . ), the contents are the same, and in other cases, the contents are inconsistent.

The control device 17 receives the outputs of the voltage comparators 36 and 37 and operates by determining that the contents are the same when either one gives the same signal.

Next, the detectors 38, 39 and the voltage comparator 40,
41 is a signal that detects the audio signal level output from the low-pass filters 30 and 31 and provides a signal indicating whether or not there is a sufficient audio signal level for determination, that is, an audio level determination signal to the control device 17; When performing the identity determination, the control device 17 selects and performs the identity determination during a period in which the audio level is sufficient, thereby making it possible to perform the identity determination with relatively high accuracy in time.

As described above, the conventional identity determination was mainly performed by the hardware of the identity determination unit 16. For this reason, it had a relatively complex configuration including a shift register, an E-OR circuit, an integrator, etc., and was expensive. Furthermore, as a conventional example, we have shown a configuration with three sets of E-OR circuits and integrators, but the time difference between two audio signals that can be handled by this is at most around 1 [ms], and in order to handle even larger time differences, required the addition of many shift registers and E-OR circuits and integrator pairs.

This invention was made in order to eliminate the drawbacks of the conventional identity determiner, and the configuration of the identity determiner is simplified by directly determining the zero-crossing wave obtained from the zero-cross detector using a control device. At the same time, the aim is to be able to deal with even larger time differences.

FIG. 4 is a block diagram showing an embodiment of the present invention, in which 6 to 41 are completely the same as the conventional example;
0 is a first data memory area, ie, data memory A, 61 is a second data memory area, ie, data memory B, and 62 is a counter. Further, 60 to 62 are all areas provided on the data memory or register that constitutes the control device 17, and are temporarily set only during the identity determination operation described below. good.

The identity determination operation by the control device 17 is performed, for example, as follows.

First, the control device 17 checks the outputs of the voltage comparators 40 and 41 and waits until a signal indicating that the audio level is sufficiently present (hereinafter referred to as "valid") is output.
The acquisition of the two zero-crossing waves output from the zero-crossing detectors 32 and 33 is started. This data acquisition is carried out from the zero cross detector 32 to the data memory A6.
The data is sequentially stored in the data memory B61 from the zero cross detector 33 at 0, and the data acquisition interval is approximately a constant time ts, and the sampling frequency fs = 1/ts is set by the low-pass filter 30,
The cutoff frequency shall be selected sufficiently higher than the cutoff frequency of 31. It is also assumed that this data acquisition operation is performed a sufficient number of times for identity determination, that is, N+x times, and it is confirmed that the outputs of the voltage comparators 40 and 41 are both "valid" for each data acquisition. If either of the outputs of the voltage comparators 40 and 41 is not "valid", it waits until both outputs become "valid" and starts new data acquisition N+x times. As a result, N+x [bits] are continuously captured on the data memory A60 and the data memory B61 during a period when the audio signal level is sufficient.
Zero-crossing wave data will be stored. For convenience of explanation, the data memory A60 and the data memory B61 are shown in FIG.
A memory of N+2 (bits) with a number assigned to each bit. Zero-crossing wave data is stored sequentially starting from address 1, and data captured at the same time is stored at the same address of the two data memories. shall be.

When the above data acquisition operation is completed, the control device 17 first clears the counter 62 to an initial value of 0, and as shown by the arrow in FIG.
The data bits at the same location in the data memory B61 are sequentially compared, and one logical value is "1".
The contents of the counter 62 are set to 1 only when the other is “0”.
Add. This comparison operation is repeated N times, that is, from address 1 to N
It shall be repeated up to the address. As a result, if the two audio signals are exactly the same and in phase, the contents of the counter 62 will be approximately 0, and if the two audio signals are exactly the same, with only the phase inverted (opposite), it will be approximately N.
It is clear that if the contents of the two audio signals are different, if N is sufficiently large and N×ts, that is, the period of the audio signals to be compared is long enough, it will be approximately N/2, and an appropriate judgment can be made. The numbers Nth ₁ and Nth ₂ (where N/2<Nth ₁ <N, 0<Nth ₂ <N/2).
) so that after the comparison operation is completed, the contents of the counter 62 are
It is clear that it is possible to make the contents the same in the case where Nth is greater than ₁ and the case where it is less than Nth ₂ , and the contents are inconsistent in the other cases. Next, if we consider the case where there is a time difference τ between two audio signals, exactly the same argument applies if we consider the period T of the audio signal as T/ts, the time difference τ as τ/ts, and _VH as N in the conventional example. That is, the audio signal has a frequency f and a period T (T=1/
f) repetitive wave, when T > 2τ, if the two audio signals are in phase, approximately 2τ/ts out of T/ts data will be matched except for mismatches, so in this case The value N ₀ of the counter 62 is finally approximately N ₀ =・2τ/TN=2fτN (3), and when the two audio signals have opposite phases, N ₀ =・(1−2τ/T)N=( 1−2fτ)N……(4). Here, equations (3) and (4) are equivalent to (1) and (2) in the conventional example.
It has exactly the same form as the equation, and if ts is set sufficiently small and N is set sufficiently large, eo in FIG. 3 can be considered as the value of N ₀ normalized by N. Therefore, similarly to the conventional example, when two audio signals have the same content and there is a time difference τ, the determination accuracy can be improved by giving a relative delay time t to one of the audio signals in advance. . As shown in FIG. 5B and C, this operation is performed at time t at the time of data acquisition.
This can be done by comparing data captured at different times and repeating the above operations. If the data acquisition interval ts is 0.4 [ms], Figure 5B
means to sequentially compare the contents of addresses 1 to N of data memory A60 with the contents of addresses 3 to N+2 of data memory B61, and as a result, the output of zero cross detector 32 is delayed by 0.8 [ms] and compared. It will be the same as doing. Therefore, the content _N1 of the counter 62 obtained as a result is _VH as explained above.
If we replace N with N, we get the same result as the graph in Figure 3 _e1 . Also, Fig. 5c shows data memory A60.
Addresses 3 to N+2 and data memory B61 1 to
This is the same as comparing the output of the zero cross detector 33 with a delay of 0.8 [ms], and the content _N2 of the counter 62 obtained as a result is the same as the one obtained by replacing _VH with N. It will be the same as the graph in Figure 3 e ₂ .

This shows that in this embodiment, by performing the comparison and determination operation three times by the control device 17, it is possible to perform a determination completely equivalent to that of the conventional example.

It has been explained above that this embodiment can perform judgments equivalent to the conventional example, but the decisive difference from the conventional example is that it can judge two signals with a larger time difference without increasing the hardware. This can be done with high accuracy; for example, even when making a judgment to allow a time difference of ±4 [ms], data memory A60 and data memory B61 are N+10.
Comparison judgment is made once between the same locations as bits, and comparison judgment is made five times by varying i from 1 to 5 between the data of addresses I = 1 to N of data memory A 60 and address J = I + 2i of data memory B 61. , conversely, addresses J=1 to N of data memory B61
It is only necessary to compare and judge the data between the address and the address I=J+2i of the data memory A60 five times by changing i from 1 to 5, for a total of 11 times. Furthermore, this determination can be made a total of 21 times, with the number of mutually shifted addresses being 1, to further improve the determination accuracy. Furthermore, it is clear that a time difference larger than this can be easily dealt with by increasing the data memory and increasing the number of determinations.

As described above, according to the present invention, the number of hardware parts used for identity determination can be reduced, and identity determination can be performed with high accuracy even when there is a large time difference between two audio signals.

In addition, in the above explanation, data memories A and B are assumed to have a memory area corresponding to approximately the time to be judged + the allowable time difference, but if the time difference to be allowed for judgment is relatively small, the data memories A and B are set to the memory area corresponding to the allowable time difference. For only the corresponding number of times, a counter may be provided for the number of comparisons and determinations described above, and the contents of the data memory may be sequentially updated as data is taken in, and the comparison and counter counting may be performed at the same time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of this type of radio receiver, FIG. 2 is a block diagram showing a conventional identity determination device, FIG. 3 is an explanatory diagram of identity determination operation, and FIG. 4 is an embodiment of the present invention. FIG. 5 is a block diagram showing the operation of the present invention. In the figure, 1 is an antenna, 2 is a distributor, 6 is a first receiving system, 10 is a second receiving system, 11 is an audio signal switch, 12 is a low frequency amplifier, 13 is a speaker, and 14 and 15 are electric fields. Detector, 16 is an identity determiner, 17 is a control device, 30, 31 are low pass filters, 32, 33 are zero cross detectors, 38, 3
9 is a wave detector, 40 and 41 are voltage comparators, 60 is a first data memory, 61 is a second data memory, and 62 is a counter. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A first and second receiving system configured to be able to perform automatic tuning independently of each other, which detect the receiving state of the receiving station selected by these two receiving systems, and A means for discriminating pass/fail, an identity determiner that provides a signal necessary to distinguish between the output signals of the two receiving systems, and an identity determiner that determines whether the output signals of the two receiving systems are different or different based on the output of the identity determiner. If it is determined that the content of two receiving stations by two receiving systems is the same, the receiving station with better reception status is fixed to one receiving system, its output audio is fixed to the audio output circuit, and the other receiving station is fixed to the audio output circuit. The identity determination device includes a control device for shifting the reception system to an automatic tuning state, and the identity determination device has two low-pass filters each inputting an output signal of the reception system, and an output signal of each of the low-pass filters. two zero-cross detectors that output binary signals to the control device; and a signal that is connected to the two low-pass filters and detects the audio signal level of the low-pass filter output, and is activated when this is higher than a predetermined determination level. and means for providing a signal to the control device that disables the control device when it is not necessary. 2. Two memory areas where the control device imports and temporarily stores the two zero-cross detector outputs into the identity determiner when both audio level signals of the identity determiner are valid, and a It is determined whether or not each memory data matches multiple times, either as a combination with the same data acquisition time or as a combination with a predetermined time difference, and the number of data that matches or does not match is counted for each judgment. If the counter value as a result of each judgment exceeds the first judgment number or falls below the second judgment number even once, the audio signals from the two receiving systems are treated as having the same content. 2. The radio receiver according to claim 1, wherein the radio receiver operates as if the contents are different when the content is different.