JPH0224027B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a substrate bias generating device used in a semiconductor device.

Traditionally, circuits formed on semiconductor substrates
2. Description of the Related Art A charge pumping device as shown in FIG. 1 is known as a power source for generating a voltage of opposite polarity to an externally supplied power source voltage and supplying it to a substrate. In the figure, reference numeral 1 denotes an alternating current voltage generating circuit with one end grounded, and this alternating current voltage generating circuit 1 generates an alternating current that oscillates between a reference voltage V _SS (here, the GND voltage) and a power supply voltage V _DD . The other end of this generating circuit 1 is connected to the source of an N-channel MOS transistor 3 via a capacitor 2. The gate and drain of this transistor 3 are both connected to a terminal (substrate) 4. N ₁ indicates a node between voltage generating circuit 1 and capacitor 2 , and N ₂ indicates a node between capacitor 2 and the source of transistor 3 .
The gate and drain of an N-channel MOS transistor 5 whose source side is grounded are connected to the node _N2 . The transistors 3 and 5 have a rectifying effect, and current flows from the terminal 4 to the node N ₂ and from the node N ₂ to GND.

In this charge pumping device, an AC voltage generating circuit 1 connects a node N 2 through a capacitor ₂ .
The electric charge induced in is supplied from the terminal (substrate) 4 and discharged to GND through the transistor 5.
That is, due to the charge pumping action, a current flows from the terminal (substrate) 4 to GND, thereby biasing the terminal (substrate) 4 to a negative potential.

FIG. 2 is a diagram showing a specific element structure when the charge pumping device is formed on a semiconductor substrate. That is, on the surface of a P-type silicon substrate (corresponding to the terminal 4 in FIG. 1) 6, N-type high concentration impurity regions 7 and 8, P-type high concentration impurity region 9, and N-type high concentration impurity region 10 are formed. are formed respectively. Gate electrodes 13 and 14 are formed on the N-type high concentration impurity region 10 and on the silicon substrate 6 between the high concentration impurity regions 7 and 8 via gate insulating films 11 and 12, respectively. Here, the gate electrode 13, the gate insulating film 11, and the N-type high concentration impurity region 10 constitute a capacitor 2, and the N-type high concentration impurity region 7, the gate electrode 14, and the N-type high concentration impurity region 8 constitute the source of the transistor 3.・Constitutes the gate and drain. P-type high concentration impurity region 9 is a diffusion region for facilitating ohmic contact with silicon substrate 6. Note that the transistor 5 of FIG. 1 is not shown in FIG.

Conventionally, the charge pumping device as described above has had the following drawbacks. That is, the N-type high concentration impurity region 7 (corresponding to node N ₂ in FIG. 1) has a lower voltage than the silicon substrate 6 (corresponding to terminal 4 in FIG. 1), and the voltage between the silicon substrate 6 and the high concentration impurity region 7 The PN junction (corresponding to the diode 15 indicated by the broken line in FIG. 1) formed by the two is in a forward bias state. Therefore, many electrons are injected into the silicon substrate 6. These electrons diffuse within the substrate 6 over a wide range until they recombine. This causes problems in the functionality of integrated circuits. In particular, floating nodes are often used in integrated circuits that perform dynamic circuit operations, and even in static circuits, the above-mentioned nodes are indispensable for reducing the power consumption of integrated circuits in a method that fixes the potential with high impedance. . If the electrons, which are the minority carriers mentioned above, are diffused and taken into these nodes, malfunctions of circuit elements are likely to occur.
This has been a big problem in the past.

This invention was made in view of the above circumstances.
The purpose is to provide a substrate bias generation device that can prevent injection of minority carriers into the substrate, prevent malfunction of circuit elements, and further improve charge pumping efficiency.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. 3, an alternating current voltage generating circuit 21 with one end grounded generates an alternating current that oscillates between a reference voltage V _SS (here, GND potential) and a power supply voltage V _DD . The other end of this generating circuit 21 is connected to a capacitor 22 and P
It is connected to a terminal (substrate) 24 via a channel MOS transistor 23. N ₁₁ indicates a node between the AC voltage generating circuit 21 and the capacitor 22, and N ₁₂ indicates a node between the capacitor 22 and the drain of the transistor 23. This node _N12 is grounded via a P-channel MOS transistor 25. Both of the transistors 23 and 25 have rectifying characteristics. As in the conventional example, the current flows from the terminal 24 to the node N ₁₂ due to the charge pumping action.
Flows from node N ₁₂ to GND, terminal 2
4 is biased to a negative potential.

FIG. 4 is a diagram showing a specific element structure when the charge pumping device is formed on a semiconductor substrate. In other words, an N-type silicon substrate (Fig. 3)
A P-type well region 27 (corresponding to the terminal 24 in FIG. 3) is formed in the display 26 (corresponding to the V _DD connection location),
An N-channel MOS transistor is formed in this well region 27 to constitute a main circuit.
Therefore, this well region 27 is an N channel.
Acts as a substrate for a group of MOS transistors. Further, P-type high concentration impurity regions 28, 29, and 30 are formed on the N-type silicon substrate 26, and the P-type high concentration impurity region 28 and the P-type high concentration impurity region 2 are formed on the N-type silicon substrate 26.
On the silicon substrate 26 between 9 and 30, gate electrodes 33 and 30 are formed via gate insulating films 31 and 32, respectively.
34 is formed. Here, gate electrode 3
3. The gate insulating film 31 and the P-type high concentration impurity region 28 constitute the capacitor 22 shown in FIG. channel
It constitutes the drain, gate, and source of the MOS transistor 23. The P type high concentration impurity region 35 is P
This is a diffusion region for facilitating ohmic contact with the shaped well region 27. Note that the transistor 25 of FIG. 3 is not shown in FIG.

In the charge pumping device having the above structure, unlike the conventional example, the PN junction formed by the P-type high concentration impurity region 29 corresponding to node _N12 in FIG. 3 and the N-type silicon substrate 26 is always reverse biased. state. Therefore, injection of minority carriers into the silicon substrate 26 does not occur, and disadvantages such as the malfunction of circuit elements described in the conventional example do not occur. Furthermore, this charge pumping device has the following advantages: That is, since the above-mentioned PN junction is reverse biased, the junction capacitance is extremely small, and the ratio of stray capacitance to capacitance 22 is extremely small. Therefore, the amplitude of the node _N12 can be increased, and the charge pumping efficiency is dramatically improved.

FIG. 5 shows another embodiment, in which the P-type high concentration impurity region 30 in the embodiment of FIG. 4 overlaps with the P-type well region 27 to improve the degree of integration.

FIG. 6 shows yet another embodiment.
In this embodiment _{, the} P-type high concentration impurity region ₂₉ shown in _FIG . Further, an N-type high concentration impurity region 37 is provided in this well region 36.
A PN junction formed by the P-type well region 36 and the N-type high concentration impurity region 37 is used to form a rectifying element corresponding to the P-channel MOS transistor 25 shown in FIG. In this embodiment, when the P-type well region 36 reaches a high potential, the above-mentioned PN junction is forward biased, and some of the electrons injected into the P-type well region 36 enter the silicon substrate 26. However, these only become substrate currents and have no effect on the circuit elements formed within the P-type well region 27.

In the above embodiment, the substrate is of N type, but the present invention is not limited to this. It is also possible to use a P type substrate, reverse the conductivity type of each element, and reverse the sign of the applied voltage. A similar effect can be obtained.

As described above, according to the present invention, in a substrate bias generation device including a capacitive element for charge pumping and a rectifying element, the substrate bias generating device includes a substrate and a region that becomes one electrode of each of the capacitive element and the rectifying element. Since the PN junction is always reverse-biased, injection of minority carriers into the substrate can be prevented, preventing malfunction of circuit elements and improving charge pumping efficiency.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional charge pumping device, and FIG. 2 is a sectional view showing the element structure of the device.
FIG. 3 is a circuit diagram of a charge pumping device according to one embodiment of the present invention, FIG. 4 is a cross-sectional view showing the element structure of the device, and FIGS. 5 and 6 are respectively other embodiments of the present invention. FIG. 21...AC voltage generation circuit, 22...Capacity, 2
3...P channel MOS transistor, 24...
...Terminal (substrate), 25...P channel MOS transistor, 26...N type silicon substrate, 27...
P-type well region, 28, 29, 30... P-type high concentration impurity region, 33, 34... gate electrode.

Claims (1)

[Scope of Claims] 1. A substrate bias generating device including a capacitive element for charge pumping and a rectifying element, including a semiconductor substrate of a first conductivity type, and a semiconductor substrate formed on this substrate and serving as one electrode of the capacitive element. a first region of a second conductivity type; a second region of a second conductivity type formed on the substrate and serving as one electrode of the rectifying element; and a substrate of a main circuit group connected to the second region and connected to the substrate. A substrate comprising: a well region of a second conductivity type formed as a region; and voltage applying means for operating the first region and the second region in an operation region that is reverse biased with respect to the substrate. Bias generator. 2. The rectifying element has the first region and the second region of the second conductivity type as a source/drain.
2. The substrate bias generating device according to claim 1, wherein the substrate bias generating device is constituted by a MOS type field effect transistor. 3. The substrate bias generating device according to claim 2, wherein the source region of the MOS type field effect transistor is common to the well region of the second conductivity type.