JPH0224474B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a combinational network integrated with a tri-state drive circuit and controlling said tri-state drive circuit to a high output impedance state.

Tri-state drive circuits are circuits that are capable of three states at their output. Two of them, called active states, correspond to the binary values 0 and 1.
In one state, the tristate drive circuit is in a low output impedance state, but DON′T
In another state, referred to as the CARE state, the tri-state drive circuit is characterized by a high output impedance state.

Such drive circuits are needed for various reasons,
This is the case, for example, when several electrically interconnected semiconductor chips of a data processing device are individually functionally tested after being soldered onto a substrate.
In that case, the chip to be tested must not receive any signals from other semiconductor chips that would affect the applied test signals. Therefore, the tristate drive circuits of the other chips are placed in a high output impedance state. The test chip's response to the applied test signal pattern is obtained at the output of its tristate driver circuit.

However, the tristate drive circuit is required not only for the above-mentioned test but also when bidirectional data transfer is to be performed via the transfer path in normal operation of the data processing device. In that kind of operation, two
Only one of the two tri-state drive circuits must be active at a time while the other is in a high output impedance state; if both drive circuits are in the opposite active state, they will be overloaded. Can be destroyed by electric current.

Another field of application for tristate drive circuits is when several tristate drive circuits provided on different semiconductor chips of a storage device are connected to a common output line. In operation of the device, only one tristate drive circuit should be active at a time. This is accomplished, as in the bidirectional transfer case above, by a combinational network connected to the control input of the tri-state drive circuit, which immediately places the drive circuit in a high output impedance state.

However, if the combinational network for putting the tri-state drive circuit into a high output impedance state is built into the same semiconductor chip as the drive circuit, its output can only be seen through the tri-state drive circuit. , making it impossible to fully test the combinational network. Generally, when testing a combinational network, various test signal patterns are applied to its inputs and its output value (1 or 0) is compared to a predetermined value. If all comparisons result in a match, the test passes. However, as mentioned above, when a combinational network is integrated into a semiconductor chip with a tri-state drive circuit, its output obtains an active state or a high output impedance state, thus making it impossible to accurately compare it with a predetermined value. become unable to do so. For example, if the data input of a tri-state drive circuit is held at a low potential during testing, a high potential is available at its output in the active or low output impedance state. If the output of the combinational network changes in this state and the tristate drive circuit enters a high output impedance state, the output will remain at a high potential for a while, resulting in a mismatch when compared with the expected value. Put it away. The same applies when the active state is at a low potential. It is therefore an object of the present invention to achieve the following by accurately reflecting changes in the output of a combinational network connected to the control input of a tri-state drive circuit in the output of the tri-state drive circuit.
The objective is to be able to completely test such a combinational network.

To achieve the above objectives, the present invention prevents a tri-state drive circuit from entering a high output impedance state during testing, regardless of the output of the combinational network, and provides feed into the data input of
This allows changes in the output of the combinational network to appear as changes in the output of the tri-state drive circuit, allowing the combinational network to be tested. Note that when the outputs of a plurality of tristate drive circuits are connected in common, it is necessary to maintain the tristate drive circuits connected to the combinational network that is not tested in a high output impedance state. This is made possible by a signal on the control line, which will be discussed later. A tristate drive circuit connected to the combinational network being tested receives at its control input a signal that cancels the effects of the signal on this control line and the output of the combinational network and keeps the drive circuit active.

Next, the method of the present invention will be explained in more detail with reference to the drawings. The circuit device shown in Fig. 1 is
It consists of a conventional drive circuit consisting of NPN transistors T1 to T4 and resistors R1 to R4, a combination network 4 connected to the control input 2, and a control line 5 also connected to the control input 2. The control electrode of the input transistor T1 of the tri-state drive circuit is connected to its data input 1. Transistors T3 and T4 connected in series
is the output transistor of the tri-state drive circuit, the output of which is obtained at the connection point of the two transistors T3 and T4. The two control electrodes of these output transistors are respectively connected to the collector and emitter of the input transistor T1.

This conventional circuit arrangement operates as follows. When a data signal is applied to the data input 1 of the tri-state drive circuit that causes the input transistor T1 to conduct, the output transistor T3 no longer receives any control current and the output transistor T4 becomes conductive, causing the tri-state drive circuit to conduct. Connect the output to ground potential. Therefore, a high potential at data input 1 is inverted to a low potential at output 3. On the contrary, a low potential at data input 1 switches off transistor T1 so that output transistor T4 no longer receives any control current and becomes non-conducting, while output transistor T3 receives the base current through resistor R2. Receive.
Therefore, transistor T3 becomes conductive and supplies a high potential to the output of the tristate drive circuit.

The high output impedance state of the tri-state drive circuit, in which both output transistors T3 and T4 are non-conducting, is achieved in normal operation of the data processing device by the control signal of the combinational network 4 which switches on the control transistor T2. achieved. The output transistor T3 therefore no longer receives any control current and is switched off. Since the conducting control transistor T2 prevents current from flowing through the input transistor T1, the output transistor T4 also no longer receives any control current. In testing, the high output impedance state of the tri-state drive circuit is achieved by a control signal applied via control line 5 to the control input 2 of the tri-state drive circuit.

FIG. 2 shows a circuit arrangement for implementing the method of the invention. Compared to the circuit of FIG. 1, an OR gate 6 is placed before the control input 2 of the tri-state drive circuit, an OR gate 7 is placed before the data input 1 of the tri-state drive circuit,
A control line 8 is further provided which is connected to the control input 2 and the control input 2 . Furthermore, the output of combinational network 4 is connected to one input of each of OR gates 6 and 7. A data signal is applied to the second input 9 of the OR gate 7. A control line 5 is connected to the second input of the OR gate 6, and a signal is applied to said control line 5 in order to obtain a high output impedance state of the tri-state drive circuit during testing.

The circuit of FIG. 2 operates as follows. At the beginning of the test, control line 5 receives a signal that places the tristate drive circuit in a high output impedance state if no defects are present. At its output 3 it is determined whether the drive circuit has reached that state. If it is determined that that state has been reached and therefore the drive circuit does not have any defects with respect to the high output impedance state, its control input 2 is routed via the control line 8 to the OR gate 6.
receives a potential that keeps control transistor T2 non-conducting independent of the signal provided by T2. Thereafter, testing of the combinational network 4 is started. Since the response of the combinational network to the test signal pattern applied to it is obtained only at the output 3 of the tri-state drive circuit, the drive circuit must not reach a high output impedance state. This is achieved by a potential applied to the control input 2 of the tristate drive circuit via the control line 8 throughout the test operation of the combinational network 4. Therefore, the output signal of the combinational network 4 can no longer cause a high output impedance state of the tri-state drive circuit, and said output signal is fed via the OR gate 7 to the data input 1 of the tri-state drive circuit, thus At its output 3 it is obtained in inverted form.

As explained above, according to the method of the present invention, the output signal of the combinational network 4 which causes the high output impedance state of the tri-state drive circuit is maintained at the high output impedance state of the drive circuit during testing of the combination network. All responses of the combinational network to the test signal pattern are available at the output 3 of the tri-state drive circuit.

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram showing a conventional circuit arrangement with a tri-state drive circuit, and FIG. 2 is a schematic circuit diagram showing a circuit arrangement with a tri-state drive circuit for implementing the method of the invention. . T1...Input transistor of the tri-state drive circuit, T2...Control transistor, T3, T4
...Output transistor, 1...Data input, 2...
...Control input, 3...Output, 4...Combination network,
5, 8...control line, 6,7...OR gate, 9...
...Second input of OR gate 7.

Claims (1)

Claims: 1. A method for testing a combinational network integrated with a tristate drive circuit having a data input and a control input, the control input providing a signal that places the tristate drive circuit in a high output impedance state. providing a signal to the control input that prevents the tri-state drive circuit from entering a high output impedance state, regardless of the output of the combinational network, and connecting the output of the combination network to the data input; A method for testing a combinational network, characterized by supplying