JPH0225295B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a successive approximation type A/D conversion method.

Successive approximation type analog/digital (A/D)
The converter has a configuration as shown in FIG.
This example is a block diagram of a DAC with 4-bit resolution, where COMP is the analog input voltage V _A and the reference voltage.
Comparator to compare with Vref, SAR is 4 bits B ₃ ~
B ₀ successive approximation register (B ₃ is MSB, B ₀ is
LSB), DAC is the digital output of register SAR D ₃
A local D/A converter that converts ~D ₀ back to an analog value. The reference voltage Vref is obtained by dividing the voltage V _REF (generally the power supply voltage), which specifies the maximum allowable value of the analog input voltage V _A , by resistance according to the outputs _{D 3} to _{D 0} of the resistor SAR. The maximum value is 1111, and the minimum value is 0000.

In the normal successive approximation method, B ₃ of register SAR ~
Set _B0 to 1000 and start comparison operation. B ₃
When ~B ₀ is 1000, Vref=1/2V _REF , and the input voltage V _A is first compared with 1/2V _REF . And V _A >
If it is Vref, set B ₃ to _{B 0} of register SAR to 1100, then compare Vref=3/4V _REF and V _A. vice versa
Vref=1/2V If V _A < Vref at _REF , register
Set B ₃ to _{B 0} of SAR to 0100 and set Vref = 1/4V _REF and V _A
Compare. In this way, starting from the most significant bit _B3, each bit is compared one by one, and finally all bits are compared.
Determine B ₃ to B ₀ and complete A/D conversion for input V _A. The feature of this successive approximation method is that the register SAR is initially set to 1000 and the input V _A is set to 1/2V _REF.
The point is that the operation of increasing or decreasing the reference voltage by half (1/4V _REF , 1/8V _REF, etc.) according to the comparison result is repeated. When COMP is constructed of MOS transistors, the following problems occur.

In other words, the comparator COMP shown in Figure 2a is a MOS
It is configured using transistors T ₁ to _{T 3} , capacitor C ₀ and MOS inverter G ₁ and operates as follows.
First, when the clock BAL is set to H (high) to make the transistors T ₁ and T ₃ conductive, the capacitor C ₀ is charged by the difference between the input voltage V _A and the voltage at the point N ₂ . Point N ₂
The voltage of is inverted by transistor T ₃
Since the input and output ends of _G1 are short-circuited, their intermediate potential is _Vx . After this, when the clock BAL is set to L, transistors T ₁ and T ₃ are turned off, so
A charge corresponding to (V _A −V _X ) is stored in the capacitor C ₀ . In other words, the input V _A is sampled. Figure 2b shows the voltage _VX at point _N2 when transistor _T3 is on, which voltage
It becomes the intermediate potential between _G1 's input _VIN and output Vout. capacity
The charge Q accumulated on C ₀ is Q=C ₀ (V _A −V _X ). When the comparison operation starts, the clock CP is set to H and the transistor _T2 is turned on, and the first time is Vref=1/2.
Apply V _REF to _N1 point. At this time, if Vref>V _A , the _N2 point is pushed up and becomes higher than _VX , and the output of the inverter _G1 becomes L. Conversely, if Vref<V _A , point _N2 becomes less than _VX , and the output of inverter _G1 becomes H. The L and H of this output OUT are the comparison results, but the problem is when Vref<V _A.

For example, assuming V _REF = 3.5V and V _A = 3.5V,
V _X value is usually 1.25V for n-channel E/D type.
Therefore, a potential difference of V _A −V _X =3.5V−1.25V=2.25V is generated across the capacitor C ₀ by sampling. If we enter the first stage comparison operation in this state, the _N1 point will drop to Vref = 1/2V _REF = 1.75V, so the _N2 point will be 2.25V lower than that.
It becomes 0.5V. In this case, if the transistor _T3 is an n-channel transistor, the substrate Sub is p-type and normally grounded (OV) as shown in Figure 2c, so if the _N2 point becomes negative potential, the substrate-source connection is in the forward direction, and the high charge in the capacitor C ₀ escapes until N ₂ = OV. In this case, since the charge at the time of sampling is not stored in the capacitor C ₀ , the accuracy of A/D conversion decreases. Although the comparator shown in FIG. 2a has the advantage of a simple configuration, it has the problem of charge leakage due to the relationship between Vref and V _A.

In order to improve this point, the present invention changes the reference voltage initially applied when starting the comparison operation to a high voltage that forward biases the PN junction included in the comparison response and prevents charge leakage from the comparison capacitor. In other words, instead of standardizing the comparison from the MSB, it is intended to start by removing it and comparing the bits after the MSB (MSB = 1). The successive approximation A/D conversion method of the present invention samples the analog input voltage.
A successive approximation reference voltage accumulated in a capacitor of a comparator circuit consisting of a MOS element and D/A converted from the data in a successive approximation register is applied to the input side electrode of the capacitor, and the voltage is applied according to the potential of the output side electrode of the capacitor. In the successive approximation type A/D conversion method that produces high and low outputs,
A plurality of bits from the top of the register are set to "1" and preliminary comparisons are performed sequentially starting from the lowest bits.Based on the data obtained as a result, data is added to the MOS element connected to the output side electrode of the capacitor. The present invention is characterized in that the successive approximation reference voltage is set at a cutoff time so that the voltage does not forward bias the PN junction of the MOS element, and the main comparison is performed sequentially from the most significant bit to the least significant bit. This will be explained in detail with reference to.

FIG. 3 is an explanatory diagram showing one embodiment of the present invention, and shows changes in the contents of the register SAR. The A/D conversion method of the present invention can be divided into "preliminary comparison" and "main comparison" for ease of explanation. This comparison is a process in which B ₃ , B ₂ , . . . are sequentially compared starting from the most significant bit based on the reference voltage as in the conventional case. On the other hand, preliminary comparison is a process in which comparison is performed from the lower bit side. The example in Figure 3 is a register
Set 1100 to B ₃ to _{B 0} of SAR and set the second bit B ₂
The following is a case in which a preliminary comparison is made. B ₃ ~ _{B 0} is 1100
Therefore, under the conditions shown in Figure 2, Vref = 3/4V _REF = 2.625V. This becomes the potential at the _N1 point, so when the voltage of the capacitor _C0 is 2.25V, _N2 = _N1-2.25V =+0.4V, and the charge in the capacitor _C0 is not discharged.
Comparison is performed in this state, and if V _A > Vref, the initial reference voltage for this comparison is 3/4V _REF , and SAR is 1100.
Set. This preliminary comparison can be said to be a determination as to whether or not to set the second bit _B2 to 1, and the most significant bit _B3 is determined to be set to 1 from the beginning as described above. If V _A <Vref in preliminary comparison
Set B ₂ = 0 and set SAR to 1000. Therefore, this comparison starts with an initial value of 1100 or 1000. Each process of this comparison is the same as the conventional one. For example, if the initial value is 1000 and the most significant bit B ₃ is compared,
If V _A is large, set it to 1100, and if V _A is small, set it to 0100.
Rewrite inside SAR. Then, the same operation is repeated up to the lowest bit _B0 .

On the other hand, in this comparison, which started with an initial value of 1100, in the preliminary comparison, V _A > Vref for 1100
Since this condition is satisfied, we may start by comparing the first bit _B1 . However, if you do this, the circuit configuration will become complicated, and there is a risk that the charge on the capacitor C ₀ may vary slightly due to the influence of noise, etc., so please be sure to check the most significant bit.
Start with B ₃ . As is clear from the preliminary comparison results, this comparison should yield the same comparison results of 1100 for B ₃ and B ₂ . In this comparison, when the first bit _B1 is reached, the judgment result is divided into _VA large and small for the first time, the bit is set to "1" or "0", and the process proceeds to the lowest bit _B0 . Note that in this case of V _A > Vref, charge leakage may occur, so if V _A has a large value, the capacitance
Let's compare from a higher Vref than sampling to C ₀ .

FIG. 4 shows another embodiment of the invention, in which the preliminary comparison starts from the first bit _B1 . Therefore, depending on the comparison result of the second bit _B2 , there are three initial values (1000, 1100, 1110) for this comparison. In this case as well, this comparison is performed in the same way.
If this idea is further advanced, preliminary comparisons can be made by setting B ₃ to B ₀ as 1111 and sequentially starting from the 0th bit B ₀ to B ₁ and B ₂ . In this case, since the comparison is started from the highest reference voltage, there is no problem of charge leakage, but the time required is long.

When actually configuring a successive approximation type A/D converter, the number of stages of preliminary comparison to be included is determined by taking into account the maximum allowable value of the analog voltage. for example
If V _REF = 3.5V, _{V A = 3.5V ,} and _V
Vref = 3/4V _REF = 2.625V is appropriate when B ₃ ~ _{B 0} is 1100, but making B ₃ ~ _{B 0} higher than this, i.e.
There is no need to make a preliminary comparison using 1110 or 1111. However, V _REF = 10V, V _A = 10V, V _X =
When _{the voltage is} 1.25V, Vref>V _{A -V} In this case
Set B ₃ to B ₀ to 1110 or 1111.

Therefore, in order to meet all the conditions, B ₃ to B ₀ are set to 1111 as described above, and a preliminary comparison is made with B ₀ , B ₁ ,
B ₂ in order, and the resulting code string B ₃ ~
Based on B ₀ , this comparison may be performed in the order of B ₃ , B ₂ , B ₁ , and B ₀ . In this case, the A/D conversion time is more than twice the normal time, and there is no negative potential at the _N2 point. However, the initial value for preliminary comparison may be 1100 in advance. If this is known, it is a good idea to shorten the conversion time in this way.

As described above, according to the present invention, the charge (analog voltage sample value) in the storage capacitor in the comparator constituted by a MOS transistor does not change, so there is an advantage that conversion accuracy does not deteriorate.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a successive approximation type A/D converter, FIG. 2 is an explanatory diagram of a comparator composed of MOS transistors, and FIGS. 3 and 4 are explanatory diagrams showing embodiments of the present invention. . In the figure, COMP is a comparator, SAR is a successive approximation register, DAC is a D/A converter, C ₀ is a capacitor, and T ₁
~ _T3 is a MOS transistor, _G1 is a MOS inverter.

Claims (1)

[Claims] 1 Sampling the analog input voltage and converting it to MOS
A successive approximation reference voltage accumulated in a capacitor of a comparator circuit consisting of an element and D/A converted from the data in a successive approximation register is applied to the input side electrode of the capacitor, and the voltage is adjusted according to the potential of the output side electrode of the capacitor. In the successive approximation type A/D conversion method that produces high and low outputs, multiple bits from the top of the register are set to "1" and preliminary comparisons are performed sequentially starting from the lower bits, and the resulting data is used as the basis. The successive approximation reference voltage is initially set so that the voltage applied to the MOS element connected to the output side electrode of the capacitor does not forward bias the PN junction of the MOS element, and the main comparison is performed sequentially from the most significant bit to the least significant bit. A successive approximation type A/D conversion method.