JPH0225538B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an addition/subtraction circuit used for waveform synthesis using an arithmetic logic circuit. Conventionally, waveform synthesis has been performed using software. In other words, when combining two types of waveform data, A and B, the sign of A is in the AS register,
The absolute value is stored in the AL register, the sign of B is stored in the BS register, and the absolute value of B is stored in the BL register.
Assuming that the register that stores the sign of the composite waveform is the CS register, and the register that stores the absolute value is the CL register, first, as shown in Figure 1, the contents of the AS register and the BS register are both “positive” or “negative”. In this case, the contents of the AL register and the contents of the B register are added, the addition result is stored in the CL register, and the contents of the AS register are stored as they are in the CS register.
Next, if the contents of the AS register are “positive” and the contents of the BS register are “negative”, or the contents of the AS register are “negative”.
If the contents of the BS register are "positive", the CL register stores the result of subtracting the BL register from the AL register. Here, when subtracting, Boro-B. When this occurs, the contents of the AS register are inverted and stored in the CS register, and if no borrow occurs, the contents of the AS register are stored as they are in the CS register. Here, we will examine the timing of such operations in detail. From the flowchart in FIG. 1, it can be seen that it takes a minimum of 6 steps and a maximum of 9 steps to obtain the composite waveform data. for example
In a microprocessor operating with a 1MHz timing clock, the time it takes to execute one step is
Since the time is 1 μs, it takes 6 to 9 μs to obtain the composite waveform data. However, processing such as voice synthesis and pattern display requires addition and subtraction to be performed in real time. In this case, the conventional software method has the drawback that the calculation time is too long and high-speed processing cannot be performed in real time. SUMMARY OF THE INVENTION An object of the present invention is to provide an extremely high-speed addition/subtraction processing circuit that solves the above-mentioned drawbacks. The present invention provides a first EXOR that receives input from the sign register of the augend, the absolute value register of the augend, the sign register of the addendum and subtractive number, the absolute value register of the addendum and subtractive number, and the sign registers of the augend and the addendum and subtractable number. The gate receives the output of this first EXOR gate, and when the signs of the augend and the number to be added and subtracted match, an addition operation is performed, and when they do not match, a subtraction operation is performed.The adder/subtracter performs a boro-output from the adder/subtractor. a complement circuit that takes the complement of the absolute value output of the adder/subtractor when the adder/subtractor is generated, and a second EXOR gate that receives the boro output of the adder/subtractor and the contents of the sign register of the augend. , the output of the second EXOR gate is used as code information of the calculation result. Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a functional block diagram showing one embodiment of the addition/subtraction circuit of the present invention, showing a data bus 1 for transferring 8-bit addition/subtraction numbers and augends, and the absolute value of the augends for setting the absolute value of the augends. value register 2
, an addition/subtraction number absolute value register 3 in which the absolute value of the addition/subtraction number is set, an adder/subtractor 4, and an addition/subtraction number sign register 6 in which the sign of the addition/subtraction number is set.
EXOR gate 7, EXOR gate 8, an operation result sign register 9 that stores the sign output data from the exclusive OR (hereinafter referred to as EXOR) gate 8, and a complement circuit 12 that takes the complement of the operation output data from the adder/subtractor 4. , an accumulator 10 for storing the output of the complement circuit 12, and a borrow flip-flop for storing the borrow output of the adder/subtractor 4. In this embodiment, the absolute value data for addition and subtraction and the absolute value data for addition and subtraction augends are each 7 bits, and the code data for addition and subtraction and the code data for addition and subtraction augends are each 1 bit. On the other hand, the EXOR gate 7 sends an addition command to the adder/subtractor 4 when the data read from the register 5 and the data read from the register 6 match, and sends a subtraction command when they do not match. Further, when the data read from the register 5 is "positive", the EXOR gate 8 outputs BORO-B in the adder/subtractor 4. If the data read from the register 5 is "negative" and no borrow occurs in the adder/subtractor 4, it outputs "positive" and if a borrow occurs, it outputs "negative". If a ``borrow'' occurs, a ``positive'' signal is output. Also, the boro flip-flop is the boro output B of the adder/subtractor 4. It is something to remember. The first one shows this situation.
Shown in the table. Here, the BORO indicates "1" when a BORO occurs, and "0" when no BORO occurs.

[Table] The operation of this embodiment will be explained below. First, the absolute value of the 7-bit augend is set from the data bus 1 into the absolute value register 2 of the augend, and similarly the absolute value of the number of addition and subtraction is set from the data bus 1 into the absolute value register 3 of the number of addition and subtraction. When an addition/subtraction instruction is issued here, the sign of the augend set in the sign register 5 of the augend is "positive" (0), and the sign of the number of addition/subtraction set in the sign register 6 of the number of addition/subtraction is "positive" (0). 0), the EXOR circuit 7 issues an "addition command" (0) to the adder 4. Since the data in the absolute value register of the augend and the data in the absolute value register 3 of the number to be added and subtracted are applied to the adder/subtractor 4, the absolute value of the augend and the absolute value of the number to be added/subtracted are obtained from the output S of the adder 4. are added and input to the accumulator 10. Here, the adder/subtractor 4 performs addition and no boro is generated, so the boro output is B. outputs “0” to the EXOR circuit 8 borrow flip-flop 11, and the sign of the augend is “positive” (0).
Therefore, the EXOR circuit 8 outputs "0" (positive) to the sign register 9 of the operation result. Next, if the sign of the augend is “negative” (1) and the sign of the augend is “positive” (0), the EXOR circuit 7 instructs the adder/subtractor 4 to “subtract command” (1), and the sign of the augend is “positive” (0). Absolute value of number and addition/subtractionThe absolute value of number is subtracted.
Here, if the absolute value of the augend is smaller than the absolute value of the augend, the boro output of the adder/subtractor outputs "1", and the sign of the augend is "negative" (1).
Therefore, the EXOR circuit 8 outputs "0" (positive) to the sign register 9 of the operation result, and outputs "1" to the borrow flip-flop 11. Further, the complement of the absolute value output of the adder/subtractor is generated based on the boro output by the complement circuit 12, and the complement of the absolute value output of the adder/subtracter is generated by the
is stored in In the above configuration, the adder/subtractor 4 may be an ALU. Also, the boro-output B of the adder/subtractor 4. Karatara-
The inversion command output to the flip-flop 11 may be an EXOR output of the contents of the sign register 5 of the addition/subtraction number and the contents of the sign register 9 of the operation result. Addition is performed as described above. According to the present invention, the 16 steps required in conventional software are reduced to 4 steps as shown in FIG. 3, simplifying the complicated software. In addition, to produce one calculation result, software now takes 3 steps instead of 6 to 9 steps, which is now 2 to 3 times faster than waveform synthesis calculations using conventional software. can. Therefore, if the addition/subtraction circuit of this embodiment is applied to a general microcomputer, the burden on the software will be reduced compared to the conventional one, and addition/subtraction will be completed in approximately 1/2 to 1/3 of the time, making it extremely suitable for real-time processing. suitable.

[Brief explanation of drawings]

FIG. 1 is a flowchart of conventional addition and subtraction, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a flowchart of the present invention. 1...Data bus, 2...Absolute value register for the augend, 3...Absolute value register for the number to be added and subtracted, 4
... Addition and subtraction unit (ALU), 5 ... Sign register for addition and subtraction numbers, 6 ... Sign register for addition and subtraction numbers, 7,
8...EXOR circuit, 9...Sign register for operation result, 10...Accumulator (absolute value register for operation result), 11...Borrow flip-flop,
12... Complement circuit.

Claims (1)

[Claims] 1 The first register that receives input from the sign register of the augend, the absolute value register of the augend, the sign register of the addendum and subtractive number, the absolute value register of the addendum and subtractive number, and the sign registers of the augend and subtractable number.
EXOR gate, receives the output of the first EXOR gate, performs an addition operation when the signs of the augend and the number to be added/subtracted match, and performs a subtraction operation when they do not match; - a complement circuit that takes the complement of the absolute value output of the adder/subtractor when the output is received; and a second complement circuit that receives the borrow output of the adder/subtractor and the contents of the sign register of the augend;
An addition/subtraction circuit comprising an EXOR gate and using the output of the second EXOR gate as sign information of an operation result.