JPH0225582B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to an inter-processor data transmission system, and more particularly to a data transmission system in which a plurality of processors communicate data with each other via a communication control device and a common bus. It is.

(b) Background of the Technology Figure 1 shows a block diagram of a multiprocessor system used, for example, in switching equipment. In the figure, 1 is a management processor, 2a...2n are call processing processors, 3a...3n are exchanges, and 4, 7a are
...7n is a communication control device, 5, 8a...8n is a memory, 6, 9a...9n is a control unit using a microcomputer, etc., 10 is a bus control unit,
11 indicates a common bus.

In a system using a common bus as shown in FIG. 1, when the management processor 1 controls, for example, the call processing processor 2a, the management processor 1 first controls the polling of the bus control unit 10 for the call processing processor 2a. When access is accepted, data transfer begins. That is, the data stored in the memory 5 is immediately stored in a buffer memory (described later) of the communication control device 4 by memory access DMA, and then transferred to the memory 8a stored in the buffer memory (described later) of the communication control device 7a.
When the memory 8a becomes full, the control units 6 and 9
An interrupt end notification is sent to a.

The present invention relates to data transfer between the management program 1 and the call processing processor 2a after polling in the system shown in FIG.

(c) Prior art and problems In the system shown in Figure 1, the processor 1 and call processing processor 2a after polling completion management
Figure 2 shows data transfer between the two.

In FIG. 2, blocks that are the same as those in FIG. 1 are indicated by the same symbols as in FIG. 26, 32 are transfer byte counters, 27, 3
3 shows matching circuits, respectively.

In the circuit shown in FIG. 2, data input to the data receiving circuit 22 is sequentially written into the buffer memory 23 starting from address 0, and the address to which it is written is counted up by an address counter. On the one hand, the transferred data is counted by a transfer byte counter 26. buffer memory 23
When the data reception is completed, the buffer memory 23
The contents of are transmitted to the communication control device 7a via the data transmitting circuit 24, but prior to this, a reset signal is issued from the data transmitting circuit 24 to the address counter 25 to initialize the counter. After that, the data transmission circuit 24 transfers the data to the buffer memory 23.
The address counter 25 counts up each time the contents of the address are read out and transmitted to the receiving side communication control device 7a. This data transmission operation is executed until the match circuit 27 detects a match between the value of the address counter 25 and the value of the byte counter 26.

The data transmitted from the data transmission circuit 24 is received by the data transmission circuit 28 of the communication control device 7a, and the received data is processed in exactly the same way as in the communication control device 4.

Such a conventional data transfer system requires a transfer byte counter and a matching circuit in each processor, which increases the number of components and makes the transfer system complicated.

(d) Object of the Invention In view of the drawbacks of the prior art, it is an object of the present invention to provide an inter-processor data transmission system that can transfer data using a simple circuit.

(e) Structure of the Invention According to the present invention, in a data transmission system in which a plurality of processors communicate data with each other via a communication control device and a common bus, the present invention provides a data transmission system in which a plurality of processors communicate data with each other via a communication control device and a common bus. The writing order and the order of sending data to the receiving side communication control device after data writing are reversed, and the data writing order to the data buffer memory in the receiving side communication control device and the processor side after data reception are reversed. This is achieved by providing an inter-processor data transmission system characterized by reversing the order in which data is read.

(f) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of the system according to the present invention, in which 41 and 45 are data receiving circuits, 42 and 46 are buffer memories, 43 and 47 are data transmitting circuits, and 44 and 48 are address counters. The blocks shown with the same symbols as in FIG. 1 indicate the same corresponding blocks as in FIG.

In FIG. 3, the data received by the data receiving circuit 41 is n+1 data starting from address 0 as shown by _D0 , and this data is transferred to the buffer memory 42 by a count-up instruction from the data receiving circuit 41 to the address counter 44. to 0
Written from address. When n+1 pieces of data have been written, the operation moves to data transmission from the buffer memory 42 to the communication control device 7a via the data transmission circuit 13.

At this time, when reading data from the buffer memory 42, the data is read out from address n of the buffer memory 42 in reverse by a countdown instruction from the data transmitting circuit 43 to the address counter 44. Then, the output data from the data transmitting circuit 43 becomes data starting from address n, as shown by _D1 , and is sent to the communication control device 7a.

The operation in the communication control device 7a is similar to the operation in the device 4, and the input data D ₁ starting from address n is converted to data D ₂ starting from address 0, and the same data as the original data D ₀ is output. do.

(g) Effects of the Invention As explained in detail above, according to the present invention, the transfer byte counter and matching circuit that were conventionally required in a communication control device can be omitted, saving hardware, thereby simplifying the system. Since the cost is low, the present invention can be applied to multiprocessor systems of private branch exchanges, etc., and its effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system in an exchange to which the method according to the present invention is applied, FIG. 2 is a block diagram of an example of a conventional data transmission method between processors, and FIG. 1 of the data transmission method according to the invention
FIG. 2 is a block diagram of an embodiment. In the drawing, 41 and 45 are data receiving circuits;
2 and 46 are buffer memories, 43 and 47 are data transmission circuits, and 44 and 48 are address counters, respectively.

Claims (1)

[Claims] 1. In a data transmission system in which multiple processors communicate data with each other via a communication control device and a common bus, the order in which data is written to the data buffer memory in the communication control device on the sending side and the communication on the receiving side after data is written. The feature is that the order of sending data to the control device is reversed, the order of writing data to the data buffer memory in the communication control device on the receiving side, and the order of reading data to the processor side after data reception are reversed. An inter-processor data transmission method.