JPH0226318B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor memory circuits, and more particularly to static type semiconductor memory circuits.

In general, static type semiconductor memory circuits are
A pair of bit lines BL extending along the Y direction,
BL, a large number of memory cells connected to be sandwiched between the pair of bit lines, a pair of load transistors each inserted into the pair of bit lines BL, and each of the large number of memory cells. Therefore, the basic component is a word line extending in the X direction. In a semiconductor memory circuit having such a configuration, two problems have hitherto been a drawback in this type of semiconductor memory circuit. The first drawback is that power consumption becomes unnecessarily large. This is because, in the semiconductor memory circuit described above, a steady current is always passed through one of the pair of load transistors to one of the pair of bit lines. The second drawback is that it is difficult to increase the access time. There are two causes for this second drawback. The first cause is
When reading information from an accessed memory cell to a bit line, the steady current is drawn through the transistor in the memory cell and the information is transferred onto the bit line at the same time, so naturally there is a brake on the read speed. The problem is that it is multiplied by The second cause is
g _n (transconductance), mainly g _n of the load transistor. Generally, it is known that the larger g _n is better in order to improve access time. However, it is also well known that in order to increase g _n , the size of the transistor itself must be increased. In this case, in order to increase the degree of integration, it is common to end up designing in the direction of decreasing g _n , which results in a sacrifice in access time.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to propose a semiconductor memory circuit in which the two drawbacks mentioned above can be eliminated.

In accordance with the above object, the present invention is characterized in that the g _n of the load transistor is apparently variable depending on information at the time of access, and the conventional steady current is controlled in accordance with the information. .

The present invention will be explained below with reference to the drawings.

FIG. 1 is a circuit diagram showing a general static semiconductor memory circuit. In this figure, BL and BL are a pair of bit lines, and a large number of memory cells MC are arranged connected to the pair of bit lines BL. The pair of bit lines BL,
A pair of load transistors Q ₁ and Q ₂ are also inserted into BL. On the other hand, a word line WL is connected to the memory cell MC, and a desired memory cell MC is captured by the bit line and the word line. Note that, although there are actually many memory cells, many pairs of bit lines, and many word lines, they are not shown. or,
Each bit line pair is provided with a write buffer for writing information and a sense amplifier for reading information, but these are not shown.

Now suppose that the BL side of the memory cell MC has logic L (therefore,
Assume that a logic H) is stored on the BL side, and that the memory cell MC is now accessed by the word line WL. In this case, the state of each transistor is first determined by the fact that logic L and H are stored as shown in the figure.
_Q5 is on, transistor _Q6 is off. Then, since there is an access from the word line WL, both transistor Q ₃ and transistor Q ₄ (transfer gate) are turned on.

Then, both transistors Q ₃ and Q ₅ turn on, so the connection between the power supply Vcc and the ground GND is
Transistor Q ₁ along the dotted line route towards
A current i flows through it. This is the memory cell in question
It flows steadily as long as the MC continues to be accessed, and this is the steady current described above. This appears as a waste of power consumption (the first drawback mentioned above). On the other hand, during read access, since the read operation is performed while drawing this steady current i through transistors _Q3 and _Q5 , memory cell MC
From this point of view, the read operation must be carried out with not only the capacitive load of the bit line BL but also this steady current load, making it impossible to speed up the access time (the second disadvantage mentioned above).

Therefore, in order to eliminate the above-mentioned drawbacks, the present invention focuses on g _n of the load transistors Q ₁ and Q ₂ . In other words,
G _n is varied as appropriate to improve power consumption and access time. in particular,
As mentioned above, regarding improving access time,
g _n is increased, and regarding power consumption, g _n is decreased after the rise of the current i. However, generally this g _n is fixed and relatively small. The reason for the small size is to increase the packaging density. Therefore, in the present invention, a "level converter" is introduced to make this g _n variable as appropriate. There is a pair of level converters, each of which functions to invert the level of the logic signal appearing on the corresponding pair of bit lines BL, and apply it to each control electrode of the corresponding pair of load transistors.

FIG. 2 is a circuit diagram showing the principle structure of a semiconductor memory circuit according to the present invention. In this figure, the same components as in FIG. 1 are indicated with the same reference symbols. Therefore, LC ₁ and LC ₂ in this figure are a pair of level converters introduced based on the principles of the present invention. Level converters LC ₁ and LC ₂ receive and level convert logic signals on bit lines BL and LC 2, respectively, and transfer these to respective control electrodes of load transistors Q ₁ and Q ₂ (FETs in the figure), respectively.
gate).

The operation of the circuit having the principle configuration shown in FIG. 2 is as follows. Using the explanation of Figure 1 again,
Transistor _Q5 side is L, transistor _Q6 side is H
The corresponding memory cell is connected by the word line WL in the state of
When MC is accessed, first the current i mentioned above rises. Before this current i rises, the bit line
The logic level of BL is not sufficiently pulled to L, but is rather at H level. This bit line
The level H of BL is sufficiently converted by the level converter LC ₁ , and the level is converted to the load transistor Q ₁ .
A sufficiently high H level is applied to the gate of. Then, the load transistor _Q1 is sufficiently maintained in the on state (g _{n is} large). In this on state, if the memory cell MC is accessed as before, the current i will rise rapidly. Then, this current i is drawn to the earth GND through transistors Q ₃ and Q ₅ , and the logic of the bit line BL falls toward L. Then, since the level converter _LC1 sufficiently converts the logic level that falls to L, a sufficiently low L level is applied to the gate of the load transistor _Q1 . For this reason, the load transistor Q ₁
turns off rapidly and then remains in this off state (g _n small).

Thus, it is extremely beneficial that the load transistor _Q1 is turned off quickly after accessing the memory cell MC. This is because as the memory cell MC is accessed, the current i rapidly decreases. From the perspective of the memory cell MC, during the information read operation, only the original capacitive load of the bit line is present, and the current load (current i) is no longer present. The load due to the withdrawal of i) no longer exists. This leads to improved access time and eliminates the second drawback mentioned above. At the same time, the fact that the current i rapidly decreases and remains almost zero leads to an improvement in power consumption and eliminates the first drawback mentioned above.

According to the principle configuration shown in FIG. 2 described above, a logic signal for changing the above g _n is obtained from the own side.
It is a so-called self-returning type. However, the principles of the invention are not to be realized only by such a self-returning method. That is, g _n
Obtain a logical signal from the other side to change the
The above principle can also be realized by using a so-called mutual feedback type. This is the memory cell MC
This paper focuses on the logical complementarity of bit lines versus BL in . Its configuration is clarified in FIG.

FIG. 3 is a circuit diagram showing an embodiment of a semiconductor memory circuit according to the present invention. In this figure, the same components as in FIG. 1 are indicated with the same reference symbols. Here LC and are level converters based on the present invention, and these level converters
LC, is a level inversion function (H→L, L→H)
, which replaces the level converters LC ₁ and LC ₂ described above. This level inversion is based on the logical complementarity of the bit line pairs, i.e. (BL=H,=L) or (BL=L,=L).
This is necessary in order to adapt the relationship H) to the above mutual feedback type. However, the basic operating principle and effects are the same as explained using FIG.

Finally, I will give a specific example of a level converter. The level converter LC can most simply be an inverter. Inverters are extremely common and consist of two FETs connected in series.
Its form is E
(Enhancement)/D (Depletion) type circuits may also be used. In a CMOS circuit, the steady current to the gate of the load transistor is almost zero,
This is preferable in terms of power consumption. However, even if an E/D type circuit is used, the gate capacitance of the load transistor is extremely small compared to the bit line capacitance, so power consumption is hardly a problem.

As described above, according to the present invention, a semiconductor memory circuit that is improved in terms of access time and power consumption compared to the conventional semiconductor memory circuit is realized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a general static semiconductor memory circuit, FIG. 2 is a circuit diagram showing the principle configuration of a semiconductor memory circuit according to the present invention, and FIG. 3 is an embodiment of a semiconductor memory circuit according to the present invention. FIG. MC...Memory cell, BL,...Bit line pair, _Q1 , _Q2 ...Load transistor pair, LC,...
Level converter, WL...word line.

Claims (1)

[Scope of Claims] 1: a pair of bit lines consisting of a first bit line and a second bit line; a static type memory cell connected between the first and second bit lines via a transfer gate; A semiconductor memory circuit comprising: a first load transistor directly connected between the bit line and the power supply; and a second load transistor directly connected between the second bit line and the power supply. A signal responsive to the potential of the first bit line is constantly transmitted to the control electrode of the second load transistor, and as the potential of the first bit line increases, the conductance of the second load transistor is reduced and turned off. a first feedback means for constantly transmitting a signal responsive to the potential of the second bit line to a control electrode of the first load transistor, and increasing the potential of the first load transistor as the potential of the second bit line increases; A semiconductor memory circuit comprising: second feedback means for reducing the conductance of a transistor and turning it off.