JPH0226812B2 - - Google Patents

Description

Detailed Description of the Invention The present invention provides a transistor circuit that improves the surge absorption capability of a transistor that absorbs surges from an inductive load or wiring while shortening the switching time of a transistor that controls on/off an inductive load. It is related to.

Conventionally, in order to shorten the switching time, especially the time to transition from a conductive state to a cutoff state, and absorb surges, a capacitor and a resistor were connected in series between the collector and emitter of a transistor (generally called a CR absorber). ) were commonly connected in parallel. When there is no external surge absorber such as a CR absorber and the transistor is controlled to shorten its switching time (by reverse biasing the base and emitter, or by making the transistor conductive in the active region, etc.), ,
Because the transistor's surge absorption capacity was small, it was often destroyed. That is, the surge absorption capability of the transistor becomes smaller as the switching time of the transistor becomes shorter. On the other hand, the shorter the switching time of the transistor, the better the response, and there was a contradiction between these.

An object of the present invention is to provide a transistor circuit in which the switching time of the transistor is shortened and the surge absorption capacity thereof is increased without requiring an external absorber such as a CR absorber. For this purpose, the transistor circuit according to the present invention increases the surge absorption capability by setting the base bias of the transistor to a reverse bias state the moment the transistor is cut off, and setting the transistor to an open state after a predetermined period of time has elapsed. That is,
The surge absorption capacity EV _CE(SUS) of a transistor against inductive loads, etc. has the following relationship: EV _CEO(SUS) > EV _CER(SUS) > EV _CES(SUS) > EV _CEX(SUS) (1). Here, equation (1) is as follows, starting from the left side:
Open the base, insert a resistor between the base and emitter,
The surge absorption capacity under the conditions of base-emitter short circuit and base-emitter reverse bias is shown, and a subscript with an alphabetic character is shown for each.
Therefore, when the switching time is shortened by reverse biasing between the base and emitter, the surge absorption capacity is the smallest, as is clear from equation (1). By the way, the switching time of a transistor, especially the time to transition from a conductive state to a cut-off state, is determined by the accumulation time tstg during which the collector-emitter current decreases to a predetermined value (usually 90%) and a value from which it can be assumed that almost no current is flowing. (10%). Therefore, if these times are reduced by means of base-emitter reverse bias, the switching time will be reduced accordingly. However, especially when the second time is shortened, the surge absorption capacity becomes smaller accordingly. Therefore, the present invention allows the base reverse current to flow when the transistor is turned off to shorten the accumulation time.
tstg is shortened and the base-emitter reverse bias is eliminated to reduce the decrease in the second time. As a result, the surge absorption capacity is
EV _{CEO (SUS)} is approached, and the sum of the accumulation time tstg and the second time becomes smaller overall, so that the switching time can be shortened. Here, the point at which the base-emitter reverse bias is eliminated is detected by the collector-emitter voltage of the transistor. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.
2 is a transistor that performs surge absorption, and 2 is a collector terminal 12 and an emitter terminal 11 of transistor 1.
Detection terminals 10 and 11 are respectively connected to the detection terminals 10 and 11, and the detection circuit detects the voltage between them. 3 is a signal source for controlling on/off of the transistor 1; 4 is a signal output terminal of the detection circuit 2, which is connected to an input signal terminal 5 of the signal source 3; One end 6 and the other end 7 of the bias output of the signal source 3 are connected to the base end 8 and emitter end 9 of the transistor 1, respectively. The configuration of the detection circuit 2 is that resistors 13 and 14 are connected in series. The signal source 3 has a configuration in which a DC power supply 15, a resistor 16, a forward bias transistor 17, and a reverse bias transistor 18 are connected in series, 19 is a control signal, 20 is a diode, 21 is an inverter for signal inversion, and 22 is a capacitor for reverse bias power supply, and 23 is a resistor for forward bias current limiting and charging of capacitor 22.

This operation is performed by controlling the forward bias transistor 17 and the reverse bias transistor 1 by the control signal 19.
8 are turned on and off alternately, and the base end 8 and emitter end 9 of the transistor 1 are forward biased and reverse biased to make the transistor 1 conductive and cut off. Now, when transistor 18 becomes conductive and transistor 1 begins to turn off, the charge on capacitor 22 is transferred to the emitters of transistor 8 and transistor 1.
A reverse base current flows through the transistor 1 by being discharged through the base. This results in transistor 1
The accumulation time becomes very short. Also at this time,
The collector-emitter current of the transistor 1 decreases and its breakdown voltage recovers, that is, the collector terminal 12.
When the voltage between the emitter terminals 9 increases, the detection circuit 2
As a result, the voltages at the input signal terminal 5 and the bias output terminal 7 rise. When this voltage reaches the gate threshold of the inverter 21, the output of the inverter 21 becomes low level, and as a result, the transistor 18 is cut off, and the base end 8 and emitter end 9 are in an open state and no bias is present. Therefore, the storage time tstg of the transistor 1 becomes short, and if the voltage of the detection circuit 2 that causes the transistor 18 to be in the cut-off state is adjusted so as not to shorten the second time too much, the transistor As the surge absorption state of No. 1 becomes closer to EV _{CEO (SUS)} , the switching time also becomes shorter.

FIG. 2 shows another embodiment of the present invention, in which the present invention is applied to a conventional circuit. Components that are the same as those in FIG. 1 are designated by the same numbers and their explanations will be omitted.
In FIG. 1, 50 is an equivalent circuit of a Darlington transistor for high-speed switching, which is composed of two Darlington-connected transistors, two resistors, and a diode. 24 is an input control signal, and 25 is a transistor for conducting reverse bias current. When the potential of the signal output terminal 4 of the detection circuit 2 rises, it is cut off, and the base terminal 8 and emitter terminal 9 of the Darlington transistor 50 are in an open state. Become. 26 is an overvoltage protection diode, and 27 is a forward bias current conducting diode. In this operation, the Darlington transistor 50 conducts during the positive cycle of the input control signal 24, and a reverse bias current flows to the Darlington transistor 50 through the transistor 25 during the negative cycle. Then, as the collector-emitter voltage of the transistor 50 rises, the transistor 25 is turned off and the base-emitter becomes open. Therefore, the same effect as in FIG. 1 is obtained.

To show specific experimental results, the bias signal 24
are ±0.5A and ±5V, resistor 13 is 100kΩ, and resistor 14 is 5kΩ, the surge absorption capacity of Darlington transistor 50 is 1.5J (EV _CEO(SUS)
≒3J), EV _CEX(SUS) of this transistor 50 ≒0.1J
The tolerance was improved by more than 10 times compared to the previous version. Also, the accumulation time tstg is about 11μs under the EV _{CEO (SUS)} condition, and the second
Under the EV _{CEX (SUS)} conditions shown in the figure, the time was about 8 μs.

As described above, according to the circuit of the present invention, the switching time can be shortened and the surge absorption capacity can be increased, so that an external surge absorber such as a CR absorber is not required. In the above embodiment, the voltage between the collector and emitter of the transistor is detected by the detection circuit 2, but the voltage between the collector and base may also be detected.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing another embodiment of the present invention, in which the present invention is applied to a conventional circuit. 1...Transistor, 2...Detection circuit, 3...
Signal source, 4...signal output end, 5...input signal end,
6, 7...Bias output end, 8...Base end, 9
...Emitter end, 10, 11...Detection end, 12...
... Collector end, 13, 14 ... Resistor, 15 ... DC power supply, 16 ... Resistor, 17, 18 ... Transistor, 19 ... Control signal, 20 ... Diode,
21... Inverter, 22... Capacitor, 23
...Resistor, 24...Bias signal, 25...Transistor, 26, 27...Diode.

Claims (1)

[Claims] 1. A detection circuit that detects the voltage between the collector and emitter or base of a transistor that performs surge absorption, a supply means that supplies a signal to the transistor to control conduction and cutoff of the transistor, and a supply means that cuts off the transistor. means for supplying a reverse base current to the base of the transistor by supplying a signal to the collector of the transistor by supplying the reverse base current;
A transistor circuit comprising: means for stopping the operation of the reverse bias means using an output from the detection circuit to open the base and emitter of the transistor when the emitter voltage exceeds a predetermined potential.