JPH0227885B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital protective relay device, and particularly to a digital protective relay device that inputs a large amount of electricity from its own power station for the purpose of main protection as well as back-up protection. It is. [Technical background of the invention] A protective relay using a microcomputer,
That is, digital protective relay devices using digital relays are beginning to be put into practical use by taking advantage of the excellent features of digital relays. One of the features of digital relays is that they can accommodate a large number of relay elements. FIG. 1 shows a conventional configuration of a digital protective relay device that takes advantage of this feature and can also provide backup protection. Note that in the following explanation, a single phase will be explained for simplicity. Figure 1 shows, for example, "Showa 57
This figure shows a configuration with a protection device that inputs a large amount of electric power, as disclosed in 2011 National Conference of the Institute of Electrical Engineers of Japan, Proceedings No. 979, "Practical Application of Digital Type Fault Continuation Detection Device". The digital protective relay device shown in FIG. 1 is composed of a first device 1 for main protection and a second device 19 for backup protection, and the second device 19 is for n-line protection. Current from power transmission lines 2 ₁ , 2 _{2 .} . . 2n is inputted through a current transformer 3 and a cable 4, and voltage is inputted from a voltage transformer 6 connected to a bus bar 5 and a cable 7. In the second device 19 the cables 4 and 7 are each laid up to the cable terminal 8, after which the inboard cable 9 is connected to the auxiliary transformer 10.
It will be laid down until the end. The auxiliary transformer 10 converts the current and voltage input from the internal cable 9 into appropriate signal levels and outputs outputs S1 ₁ , S1 ₂ , ...S1n to an analog/digital conversion circuit (hereinafter referred to as A/D) 11. do. This A/D 11 inputs the sampling signal S9 and the switching signal S10 output from the control circuit 12, samples all the inputs simultaneously when the sampling signal S9 is input, and then inputs the switching signal S10. All inputs are sequentially converted into digital signals,
The data signal S11 is processed by the arithmetic processing unit 15 (hereinafter referred to as CPU).
). CPU15 is switching signal S1
0 and the data signal S11 as input, and the switching signal S
10 determines the type of input of the data signal S11, and inputs the data signal S11 to a predetermined location in the CPU 15.
Remember. Then, this memorized power transmission line 2 ₁ ,
A protection calculation for the power transmission lines 2 ₁ , 2 ₂ ...2n is performed using the current values of 2 ₂ ...2n and the voltage values of the bus 5. As protection methods in this protection calculation, for example, a distance relay method is used for short circuit protection, and a ground fault direction relay method is used for ground fault protection.
When the CPU 15 detects a failure in the power transmission lines 2 ₁ , 2 ₂ , . . . 2n, it issues trip commands S2 ₁ ,
Output S2 ₂ ,...S2n. On the other hand, the first devices 1 ₁ , 1 ₂ , ...1n are the main protection devices for the power transmission lines 2 ₁ and 2 ₂ , 2 ₃ and 2 ₄ , ...2n _-1 and 2n, respectively, and the configuration of the device is It has the same configuration as the second device 19 except for the input amount. As a protection method, for example, a line selective relay method is used, and protection is performed in units of two lines. [Problems with the background art] In the above configuration, the CPU 15 of the second device 19
Since one device can protect n lines, the circuit for determining failure can be significantly downsized, but there are the following problems. First, since it is necessary to input the current for n lines of the power transmission line, at least n current cables must be routed to take in the current. Despite the reduction in space due to miniaturization of panels, this large amount of cable routing still poses a problem in terms of space for cable pits and the like. Second, there is the problem of the complexity of wiring within the panel. In other words, because a large number of cables rise up from the cable pit into the panel and are connected to cable terminals, and the cables inside the panel are connected to these terminals, the amount of wiring on the back of the panel becomes extremely large, which causes a big problem in wiring work. Become. Thirdly, there is the problem of the number of input circuits. That is, the filter circuit and sample hold circuit (not shown) in the auxiliary transformer 10 and A/D 11 are as follows:
Regarding current input, it is equal to the number of lines x number of phases,
Therefore, it is necessary to provide this number of circuits. Therefore, the number of these circuits increases in proportion to the number of inputs, which is a major hindrance to downsizing the device when performing multi-line processing using digital relays. [Object of the Invention] The present invention was made with the aim of solving the above-mentioned problems, and it reduces the space for laying cables in an electric station, and reduces the input of a protection device that inputs a large amount of electricity from the electric station itself. The purpose of this invention is to provide a digital protective relay device with a miniaturized circuit. [Summary of the invention] In the present invention, a large number of electrical quantities taken in from each power transmission line to a first device are converted from analog to digital, and the converted digital data is transmitted to a second device by digital transmission. This is intended to reduce the size of the input circuit and eliminate wiring. [Embodiments of the Invention] Examples will be described below with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the digital protection relay device according to the present invention, and the system configuration is four lines. In FIG. 2, 20 is a second device corresponding to 19 in FIG. 1, and provides back-up protection for power transmission lines 2 ₁ to 2 ₄ . 21 ₁ and 21 ₂ are first devices _{corresponding} to 1 in FIG _.
The main protection calculations ₃ and ₂₄ are performed by the CPU 15B. Note that the protection methods for the first devices 21 ₁ , 21 ₂ and the second device 20 are the same as in FIG. 1. In the configuration of the first device 21 ₁ , the first device in FIG.
The difference from the devices 1 ₁ to 1n is that the first parallel/
Serial conversion circuit (hereinafter referred to as P/S circuit) 22
Only A and a second P/S circuit 22B are added. The first P/S circuit 22A receives a write signal S12 output from the control circuit 100 and a clock signal S1.
3 ₁ and switching signal S10 as input, write signal S
12, the switching signal S10 which is a parallel signal is converted into a serial signal in synchronization with the clock signal _S131 ,
The output _S14A1 is output to the device 20 of.
The second P/S circuit 22B receives the write signal S12, the clock signal _S131 , and the data signal S11, and receives the data signal S1 when the write signal S12 is input.
1, converts the data signal _S11 which is a parallel signal into a serial signal in synchronization with the clock signal S131, and outputs it to the second device 20 .
Output B ₁ . The configuration of the first device 21 ₂ is exactly the same as that of the first device 21 ₁ , and includes the first P/S circuit 22A and the second P/S circuit 22A.
P/S circuit 22B, and outputs S14A ₂ and S to the second device 20 with the same response.
14B ₂ are output respectively. Therefore, from the first devices 21 ₁ and 21 ₂ to the second device 20 ,
clock signal _S131 , output _S14A1 and output _S14B1 , and clock signal _S132 and output S1, respectively.
4A ₂ and output S14B ₂ . Furthermore, the configuration of the second device 20 is different from the second device 19 shown in FIG. 1 in that the auxiliary transformer 10, A/D 11, and control circuit 12 are not provided, and the following circuit is added. It is. That is, the first serial/parallel conversion circuit (hereinafter referred to as S/P circuit) _23A1 outputs an output S1 obtained by inverting the clock signal _S131 by the inverting circuit ₂₄₁ .
5 ₁ and the output S14A ₁ as inputs, and outputs an output S16A ₁ obtained by converting the output S14A ₁ into a parallel signal in synchronization with the clock signal S15 ₁ . Similarly,
The second S/P circuit 23B ₁ receives the output S15 ₁ and the output S14B ₁ and outputs an output S16B ₁ . Further, the counter 25 ₁ receives the output S15 ₁ and counts the number of pulses thereof, and when this reaches a predetermined value, outputs a write signal S17 ₁ to the CPU 15C. The CPU 15C simultaneously samples the voltage and current data of the power transmission lines 2 ₁ and 2 ₂ and the bus bar 5 and inputs them as an output S16B ₁ , and determines the type of electricity to be serially input as the output S16B ₁ from the output S16A ₁ . Identify and capture.
Furthermore, by inputting the write signal S17 ₁ , it is determined whether the output S16B ₁ and the output S16A ₁ can be input as parallel signals. The third S/P circuit 23A ₂ and the fourth S/P circuit 23B ₂ have an output S14A ₂ and an output S14, respectively.
_B2 and the output _S152 obtained by inverting the clock signal S132 by the inverting circuit ₂₄₂ , and output _{S16A2 .}
and output _S16B2 . Further, the counter circuit ₂₅₂ inputs the output _S152 and outputs the write signal S1.
7 Outputs ₂ . Then, the CPU 15C outputs outputs S16A 2 and ₂ for the simultaneously sampled voltage and current data of the power transmission lines 2 ₃ and 2 ₄ and the bus 5.
It can be obtained by inputting the output S16B ₂ and the output S17 ₂ . FIG. 3 is a time chart for explaining the operation. Note that FIG. 3 shows the response regarding data transferred from the first device 21 ₁ to the second device 20. In FIG. In FIG. 3, a sampling signal S9 generated at a constant period T ₀ is output at time t ₀ , and at the same time a switching signal S10 for selecting the first quantity of electricity is output. Then, analog/digital conversion is performed on the first electrical quantity from time _t0 , and data signal S11 is established at time _t1 after a conversion delay time _T1 in A/D 11. Here, the write signal S12 is the analog/
Anticipating a delay time T ₁ due to digital conversion, the signal is output as a signal with a pulse width T ₂ from time t ₂ delayed from time t ₁ . Then, this write signal S12 causes the first P/S circuit 22A and the second P/S circuit 22B to output the switching signal S10 and the data signal S, respectively.
Hold 11. Furthermore, the control circuit 100 at time t ₃
The output of the clock signal _S131 starts from this point. This clock signal _S131 is output with a period _T4 ,
The number of pulses is at least equal to or greater than the data signal S11 or the switching signal S10, whichever has the greater number of bits. The first P/S circuit 22A and the second P/S circuit 22B are clocked by the clock signal S13.
₁ , this clock signal S1
₃₁ , all bits of the data signal S11 and switching signal S10 are converted from parallel signals to serial signals. Therefore, from time t ₃ to _{t 4}
Between the output S14A ₁ and the output S14B ₁ ,
the first of the switching signal S10 and the data signal S11, respectively.
The th bit (generally the least significant bit) is output as data. Then, between the next time _t4 and _t5 , the second bit (the second bit from the lowest order) is output in the same way. Note that the switching signal S1
0 and the data signal S11, the output S1 for the clock signal _S13 greater than or equal to the data bit length
4A ₁ and output S14B ₁ are meaningless, but this processing will be described later. Note that the parallel/serial conversion in the first and second P/S circuits 22A and 22B is performed at time _t9 when the write signal S for the next electrical quantity is
The process is completed by the time 12 is output. On the other hand, the converted serial data output S14
_A1 and the output _S14B1 are latched at the rising edge of the output _S151 which is an inversion of the clock signal _S131 , and each bit is sequentially transferred to the output _S151 at the rising edge of the output S151.
16A ₁ and output S16B ₁ . Then, with the rise of the output S15 ₁ at time t ₈ , an output S16A ₁ equal to the switching signal S10 and an output S16B ₁ equal to the data signal S11 are obtained. The output _S151 is then input to the counter circuit ₂₅₁ and counted up to a predetermined number of pulses, and at time _t7 when it reaches the predetermined number, the CPU 15C outputs "0".
By inputting the output S17 ₁ , it is known that the output S16A ₁ and the output S16B ₁ have been established. CPU15C
Since it is possible to know in advance the number of bits required as information among each input of the output S16A ₁ and the output S16B ₁ , unnecessary bits are ignored in the processing. Further, the output S17 ₁ becomes "0" at time t ₇ and continues in this state until the first rise of the output S15 ₁ for the next quantity of electricity (time t ₁₀ '). Then, the same operation as described above is performed for the next quantity of electricity. That is, at time t ₆ after time T ₅ has elapsed from time t ₀ , the switching signal S10
switches to select the next amount of electricity. Next, at time _t7 , the data signal S11, which is the output of the A/D 11, is established, and at the subsequent time _t9 , the write signal S11 is established.
12 is output. Hereinafter, the P/S conversion and S/P conversion are the same as in the case of the first quantity of electricity.
In this way, one sampling data for all relay inputs is transferred to the second device 20 , and the time
At t ₁₁ , the next sampling signal S ₉ is output,
Repeat these steps thereafter. Note that the time width (transmission speed) of 1 bit of output S14A ₁ and output S14B ₁ , which are serial data, is a sampling period of 1.66 ms (600 Hz sampling in a 50 Hz system), the number of electrical quantities is 10, and the data bit length is 12. If it is a bit, then the time occupied by one amount of analog/digital conversion (switching signal S1
The zero retention time T ₅ ) can be 100 μs or more. Since serial transmission of 12 bits is performed within this time _T5 , the time _T4 for one bit can be set to 5 μs or more, which is a sufficiently practical transmission speed.
In addition, in the first device 21 ₁ , the CPU 15B inputs data at time t ₁ , whereas in the second device 20 , the CPU 15C inputs data at time t ₇ , but this delay is at most an hour
T ₅ (100 μs in the above example), which poses no practical problem. FIG. 4 is a flowchart explaining the arithmetic processing of the CPU 15C. Note that FIG. 4 shows data processing for one sampling. First, in step 41, the first device 21 ₁
In order to determine whether the outputs S16A ₁ and S16B ₁ can be read, the presence or absence of the output S17 ₁ is determined. If the result of this judgment is “Yes”, step
Proceed to step 42, and if it is "no", proceed to step 43.
In step 42, the type of the output _S16B1 , which is voltage or current data, is determined from the contents of the switching signal _S16A1 and stored in a predetermined location. step
43 and 44 are processes for inputting data from the first device ₂₁₂ , and steps 41 and 42 described above are
The process is exactly the same as that of . That is, in step 43, the presence or absence of the output _S172 is determined, and when it is "present", the process moves to step 44, and when it is "absent", the process moves to step 45.
Move to. Note that step 44 stores the output S16B ₂ as output S16A ₂ , and step 45 determines whether or not the data on the total amount of electricity has been acquired from the first devices 21 ₁ and 21 ₂ . If the process has not finished, the process returns to step 41, and if it has finished, the process moves to the next step 46. As this determination method, for example, since the output S16A ₁ and the output S16A ₂ undergo a known change, a method of determining whether or not each value has reached the final value can be used. Step 46 is a protection calculation process using the current sampled data, and when this step is completed, 1
Data processing for the sampling is completed. FIG. 5 shows another embodiment of the digital protective relay device according to the present invention, and shows only the first device ₂₁₁ in the configuration shown in FIG. Note that the first device 21 ₂ is not shown because it has exactly the same configuration. Further, the second device 20 has exactly the same configuration as in FIG. 2. In this embodiment, the input circuit shared by the first device and the second device is duplicated to prevent the main protection and backup protection from failing together due to a data signal failure. In FIG. 5, in the first device 26 , the auxiliary transformer 10 and the A/D circuit 11 are duplicated, and the data signals S11A,
S11B is input to the CPU 15A and also to a selection circuit (hereinafter referred to as MUX) 27. Then, the CPU 15A receives each data signal S11A and S1.
1B, and it is determined whether these are output correctly, that is, whether the auxiliary transformer 10 and the A/D 11 are normal. Several methods are known for making this determination, but for example, the zero-sequence electricity quantity is calculated from the electricity quantity of each of the three phases, and since this value is usually small, it is necessary to calculate the zero-sequence electricity quantity above a certain value (when an accident occurs). )
A method of monitoring that the value is within a predetermined time, a method of comparing this value with the zero-sequence electricity quantity of the grid and monitoring that they are the same, and a method of monitoring that the predetermined voltage value is analog/
There are methods of monitoring the A/D converter by digitally converting and checking this value, and methods of monitoring the magnitude of outputs S11A and S11B with respect to known inputs during automatic inspection. As a result of this determination, when it is determined that the constantly used data signal S11A is defective, the CPU 15A outputs a switching command S18 to the MUX 27, and at the same time, the CPU 15A performs a protection calculation using another data signal S11B. That is, the MUX 27 inputs the data signals S11A and S11B and the switching command S18, and outputs the output S11A as the output S19 unless the switching command S18 is input, and outputs the other output S11B when the switching command S18 is input. . and,
The output S19 is input to the second P/S circuit 22B. The other configurations are the same as the first device 21 ₁ in FIG. 2. In the above embodiment, after the data signal is switched by the MUX 27, it is input to the P/S circuit 22B, but two sets of P/S circuits are always provided, and each P/S circuit has a data output S11A, S11
Directly input B and MUX the output of the P/S circuit.
It may be configured such that the switching signal is switched by inputting the signal to the switching signal. With this configuration, even the P/S circuit is duplicated, making it possible to further improve reliability. Furthermore, the control circuit 100 is also duplicated and the A/D 11
If these are controlled independently, a more reliable configuration can be achieved. FIG. 6 shows another embodiment of the digital protective relay device according to the present invention. In this embodiment, the data signals from the duplicated input circuits are transmitted to the second device for backup protection through individual transmission means, and the data signals are transmitted by the arithmetic means in the second device. By determining the quality of the received data signal, the first device for main protection and the second device for backup protection are prevented from collapsing together. In FIG. 6, the first device ₂₈₁ has the auxiliary transformer 10 and the A/D 11 both duplicated, and the A/D
Data signals S11A and S11B which are the outputs of 11
are input to the CPU 15D, and are also input to the second P/S circuit 22B and third P/S circuit 22C, respectively. In addition, the CPU15D is as shown in Fig. 5 above.
Similar to the CPU 15A, the quality of the data signals S11A and S11B is determined and used for the main protection calculation. Further, the third P/S circuit 22C converts the input data signal into serial data and outputs it S1.
4C ₁ , and this conversion method is exactly the same as that of the second P/S circuit 22B. Other configurations regarding the first device 28 ₁ are shown in FIG .
1 ₁ and the first device 28 ₂ is exactly the same as the first device 28 ₁ . Then, the outputs S14B ₂ and S14C 2 are duplicated to transfer data signals, and the outputs S14C ₂ are duplicated to transfer data signals.
14A ₂ and clock signal S13 ₂ are both
It is configured to output to the device 29 of. In the second device 29 , the fifth S/P circuit 2
3C ₁ and the sixth S/P circuit 23C ₂ input the output S14C ₁ and the output S14C ₂ and the output S15 1 and the output S15 ₂ , respectively, perform serial/parallel conversion, and output the output S16C ₁ and _{the output S16C 2 to} the CPU 15.
Output to E. This conversion is exactly the same for the first to fourth S/P circuits 23A ₁ , 23B ₁ , 23A ₂ , 23B ₂ . The CPU 15E is the first device 28 ₁
Regarding the transfer data from output S16A ₁ ,
When S16B ₁ , S16C ₁ and S17 ₁ are input and there is output S17 ₁ , output S16B ₁ and output S16
C ₁ and the output S16 determines the type of the amount of electricity from the contents of C ₁ and stores it. And 15E always uses this stored one output S16B ₁ ,
When it is determined that data is defective due to E, backup protection calculation is performed using the other output _S16C1 .
Further, the processing regarding the transfer data from the first device ₂₈₂ is exactly the same, and one output S1 is always used.
When using 6B ₂ and it is determined that the data is defective,
Backup protection calculation is performed using the other output _S16C2 . According to the embodiment described above, the number of signal transmissions increases compared to the embodiment shown in FIG. 2, so the number of circuit configurations and transmission cables increases, but the data signal input circuit and transmission system are duplicated. Therefore, it is possible to prevent the first and second devices from collapsing together due to data signal failure. Furthermore, since the first and second devices individually check the quality of the duplicated data signal, the above-mentioned risk of simultaneous failure can be eliminated. FIG. 7 shows still another embodiment of the digital protective relay device according to the present invention. In this embodiment, a relay system is used in which the first device for main protection responds only to the current input to the grid, and the second device for backup protection responds based on each input of voltage and current. It will be done. In other words, methods that respond only to the system current, such as current differential relaying and phase comparison relaying, are used for the main protection of ultra-high voltage systems, and this is an attempt to deal with these protection methods. . In FIG. 7, the data signal from the first devices 30 ₁ , 30 ₂ to the second device 31 is only current information, and the second device 31 independently converts analog/digital voltage information and inputs it. Show the configuration. The first device 30 ₁ receives only current input from the power transmission lines 2 ₁ and 2 ₂ , and performs main protection calculation in response to only the current input in the CPU 15F,
The sampling signal S9 ₁ is output to the second device 31 . The other configuration is the first device 21 in FIG.
₁ , and the effect of the sampling signal S9 ₁ is also the same as that of the sampling signal S9. The same applies to the first device ₃₀₂ , and the power transmission lines ₂₃ and 2
₄ , and outputs the sampling signal S9 ₂ to the second device 31 . In the second device 31 , each auxiliary transformer 10
A and 10B each input the voltage output from the voltage transformer 6, convert it to an appropriate signal level, and output it to A/10B.
Output to D11A and 11B. Synchronous circuit 32A
inputs the sampling signal S9 ₁ , and when the sampling signal S9 ₁ is input, in synchronization with this, outputs a switching signal S10A for sequentially A/D converting the multiphase voltage input to the A/D 11A and the CPU 15G. In exactly the same way, the synchronous circuit 32B inputs the sampling signal S9 ₂ and outputs the switching signal S10B to the A/D 11B and the CPU 15G. A/
D11A inputs the output of the auxiliary transformer 10A, the sampling signal S9 ₁ and the switching signal S10A, and outputs the data signal S11 ₁ to the CPU 15G in the same response as the A/D 11 of the first device 30 ₁ . Similarly, the A/D 11B is the output of the auxiliary transformer 10B,
It inputs the sampling signal S9 ₂ and the switching signal S10B and outputs the data signal S11 ₂ to the CPU 15G. The other configurations are the same as in FIG. 2. In short, the CPU 15G inputs the system current information of the power transmission lines 2 ₁ and 2 ₂ from the output S16B ₁ and the output S16A ₁ , and inputs the system voltage information from the switching signal S10A and the data signal S11 ₁ . Since each of the voltage and current information is sampled synchronously, it can also be applied to protection calculations such as distance relays where the phase of voltage and current is an issue. Similarly, regarding the grid current information of transmission lines 2 ₃ and 2 ₄ , output S16B ₂ and output S16A ₂
Voltage information synchronized with the voltage input from the switching signal S10B and the data signal S112 is inputted from the switching signal S10B and the data signal _S112 . Note that in this embodiment, the first device 30 ₁ ,
30 ₂ and the second device 31 use the same clock signals S9 ₁ and S9 ₂ to simultaneously perform sampling in both devices.
If the transmission delay of S9 ₁ and S9 ₂ becomes a problem, the A/D in the first device 30 ₁ and 30 ₂
The configuration may be such that the sampling time of No. 11 is compensated for by the transmission delay. In each of the above embodiments, a method has been described in which a total of three signals, a data signal, a switching signal, and a clock signal, are transmitted in data transmission from the first device to the second device, but the present invention is not limited to this. Instead, it is also possible to adopt the cyclic digital information transmission system disclosed in, for example, Japanese Patent Publication No. 56-35039. Regarding the application of the cyclic digital information transmission method to digital protective relay devices, please refer to
For example, this technology has already been disclosed in ``1972 Institute of Electrical Engineers of Japan Tokyo Conference, Tokyo Branch Conference Proceedings No. 95. Automatic Synchronization PCM Relay Device,'' but this disclosed technology transmits current information at both ends of a power transmission line. The above-mentioned transmission method is adopted depending on the conditions specified by the transmission means (PCM transmission) to meet the requirements. FIG. 8 shows still another embodiment of the digital protection relay device according to the present invention, in which a cyclic digital information transmission method is applied. In FIG. 8, data is transferred from the first device 33 ₁ to the second device 34 using a parallel/serial control circuit (hereinafter referred to as PSC) 35 . PSC35 receives data signal S1 from A/D11
1 and the sampling signal S9 from the control circuit 100
is input, and serial data output _S201 is output at each sampling in a transmission format having a frame structure, an example of which is shown in FIG. This output _S201 consists of n-bit synchronization bits indicating the beginning of the frame, m-bit information bits indicating P electrical quantities, and q-bit verification code bits.The arrangement of the system electrical quantities in the information bits is For example, a CRC test code is used as the test code bit. This frame is output for each sampling, so the transmission speed is determined taking this into account, but the overall bit length of the frame is almost the same as the serial bit length explained in Figure 3, so it is not practical. It is possible to achieve a high speed.
The other configuration of the first device 33 ₁ is the same as the first device 21 ₁ shown in FIG. 2, and the first device 33 ₂
is the same as 33 ₁ and outputs an output S20 ₂ . In the second device 34, the first serial/parallel control circuit (hereinafter referred to as SPC) ₃₆₁ inputs the output _S201 , detects the synchronization bit, detects the beginning of the frame, and outputs the detection code bit and the information bit. The quality of the transmitted signal is determined from When this judgment result is good, the output S16B ₁ which is bit parallel grid electricity quantity data, the output S16A ₁ indicating the type of electricity quantity of the output S16B ₁ , and the write signal S1
7 Outputs ₁ to the CPU 15H. Also, if the judgment result is bad, the alarm signal _S211 is sent to the CPU15.
Output to H. The second SPC 36 ₂ inputs the output S20 ₂ in exactly the same way, and outputs 16A ₂ , 16B ₂ ,
Write signal S17 ₂ and alarm signal S21 ₂ to CPU
Output to 15H. And in CPU15H,
The processing when the alarm signals S21 ₁ and S21 ₂ are not input, that is, when the transmitted data is normal, is the same as the processing performed by the CPU 15C of the second device 20 in FIG. Alarm signal S21 ₁ , S2
When 1 ₂ is input, the arithmetic processing is stopped and an alarm signal S22 is output. In this way, PSC and
Although the use of SPC requires somewhat complicated control, the number of transmission cables can be reduced to one. In each of the above-described embodiments, the first device is the main protection device and the second device is the back-up protection device, but the invention is not limited to this.
For example, a local back-up protection device (local backup device) installed for the purpose of preventing a circuit breaker from malfunctioning, etc.
is the second device, and the main protection back-up protection device is the first protection device.
It is clear that the first device may be a device as long as it inputs at least the system current. Moreover, although the system configuration has been described in which two protected power transmission lines are collectively protected, it goes without saying that the protection system configuration may be configured on a line-by-line basis. [Effects of the Invention] As explained above, according to the present invention, since a large amount of electricity in the own electrical station is inputted as serial data in digital code, the input circuit of the digital protective relay device can be downsized, and , it is possible to provide a digital protective relay device that can reduce the space for laying cables in an electric station.

[Brief explanation of drawings]

Figure 1 is a configuration diagram of a conventional digital protection device.
Fig. 2 is a configuration diagram of one embodiment of the digital protective relay device according to the present invention, Fig. 3 is a time chart for explaining the operation, Fig. 4 is a flow chart for explaining the operation, and Fig. 5 is a diagram of the first embodiment. 6 is a block diagram of another embodiment of the digital protective relay device according to the present invention, FIG. 7 is a block diagram of still another embodiment, and FIG. 8 is a block diagram of still another embodiment. The configuration diagram, FIG. 9, is an example of the transmission data format in the configuration of FIG. 8. 1 , 21 ₁ , 21 ₂ , 26 , 28 ₁ , 28 ₂ , 30
₁ , ₃₀₂ , ₃₃₁ , ₃₃₂ ...First device for main protection, 19 , 20 , 29 , 31 , 34 ...Second device for backup protection, ₂₁ to 2n...Power transmission line, 3... ...Current transformer, 4, 7...Cable, 5...Bus bar, 6...
Transformer, 8... Cable terminal, 9... In-panel cable, 10, 10A, 10B... Auxiliary transformer, 11
...Analog/digital conversion circuit, 12,10
0...Control circuit, 15, 15A, 15B, 15
C, 15D, 15E, 15F, 15G, 15H...
...Arithmetic processing unit, 22A, 22B, 22C...
P/S conversion circuit, 23A ₁ , 23B ₁ , 23C ₁ , 2
3A ₂ , 23B ₂ , 23C ₂ ... S/P conversion circuit, 2
4 ₁ , 24 ₂ ... Inverting circuit, 25 ₁ , 25 ₂ ... Counter, 27 ... Selection circuit, 32A, 32B ... Synchronous circuit, 35 ... Parallel/serial control circuit,
36 ₁ , 36 ₂ ... Serial/parallel control circuit.

Claims (1)

[Claims] 1. A first system that introduces a plurality of electric quantities from a plurality of power systems and performs main protection calculation for each power system.
In the digital protective relay device, the first device includes a converting means for converting a plurality of input electric quantities into digital codes, and a converting means for converting the converted digital data into digital codes. a first calculation means for inputting the data and performing a main protection calculation for the power system; a plurality of transmission means for transmitting the converted digital data for back-up protection calculation; and control for providing a control signal to each of the means. The second device includes a plurality of receiving means for receiving the transmitted digital data, and receives the received digital data by receiving a control signal from the control circuit and counting the number of pulses. A counter that determines the quality of data,
A digital protection relay device comprising: second calculation means for inputting the received digital data and performing a backup protection calculation for a power system. 2 The first step introduces multiple amounts of electricity from multiple power systems and performs main protection calculations for each power system.
In the digital protective relay device, the first device includes a duplex converting means for converting a plurality of input electric quantities into digital codes; a first calculation means inputting each of the converted digital data to perform a main protection calculation for the power system and at the same time determining the quality of the digital data and outputting a switching signal when the digital data is defective; A selection means for outputting one of the digital data in response to an input switching signal, a plurality of transmission means for transmitting the selected output for backup protection calculation, and a control circuit for supplying a control signal to each means. In addition, the second device includes a plurality of receiving means for receiving the transmitted digital data, and receives the received digital data by receiving a control signal from the control circuit and counting the number of pulses. 1. A digital protection relay device comprising: a counter for determining whether or not the received digital data is acceptable; and second calculation means for inputting the received digital data and performing back-up protection calculations for the power system. 3. The first step, which introduces multiple amounts of electricity from multiple power systems and performs main protection calculations for each power system.
In the digital protective relay device, the first device includes a duplex converting means for converting a plurality of input electric quantities into digital codes; a first calculation means that inputs each of the converted digital data and performs a main protection calculation for the power system; a plurality of transmission means that transmits the converted digital data for backup protection calculation; and each of the means The second device also includes a plurality of receiving means for receiving the transmitted digital data, and a second device that receives the control signal from the control circuit and calculates the number of pulses. A counter that determines the acceptability of received digital data by counting, and a second calculation means that switches and inputs the received digital data based on the determination result and performs backup protection calculation for the power system. Features a digital protective relay device. 4. The first step, which introduces multiple amounts of electricity from multiple power systems and performs main protection calculations for each power system.
In the digital protective relay device, the first device includes a converting means for converting only a plurality of input currents into digital codes, and a converting means for converting only the plurality of input currents into digital codes, and a second device for performing backup protection calculation. a first calculation means for inputting and performing a main protection calculation for the power system; a means for transmitting the converted digital data for backup protection calculation;
The second device includes a control circuit that provides control signals to each device, and a second device that receives the transmitted digital data and receives the control signal from the control circuit and calculates the number of pulses. A counter that determines the quality of received digital data by counting; a synchronization circuit that receives a sampling signal from the control circuit; A digital protection relay device comprising a conversion means for converting into a digital code, and a second calculation means for inputting each of the digital data and performing backup protection calculation for an electric power system. 5 The first step is to introduce multiple amounts of electricity from multiple power systems and perform main protection calculations for each power system.
In the digital protective relay device, the first device includes a converting means for converting a plurality of input electric quantities into digital codes, and a converting means for converting the converted digital data into digital codes. a first calculation means for inputting and performing a main protection calculation for the power system; a transmission means for transmitting the converted digital data for backup protection calculation using a cyclic digital information transmission method;
The second device includes a control circuit that provides control signals to each device, and a receiving device that receives transmitted data having a frame structure and determines the quality of the received data, and 1. A digital protection relay device comprising: second calculation means for inputting data and performing back-up protection calculations for an electric power system, and for stopping calculation processing and sending out an alarm signal when transmitted data is defective.