JPH0227893B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an overvoltage suppression circuit that is provided in a semiconductor integrated circuit and is capable of suppressing the generation of a voltage exceeding a given set value.

Semiconductor circuits are normally used in a voltage range below the withstand voltage to prevent element destruction.
When special circuit technology is applied or due to abnormalities in other circuits, a high voltage exceeding the withstand voltage may be applied.

Specifically, for example, as shown in Figure 4, we applied a circuit technology that stores charge in a capacitor during non-operation and uses this charge during operation to generate a voltage higher than the power supply voltage through the bootstrap effect. In this case, if the voltage at E is set relatively high, there is a possibility that the voltage at the terminal D will exceed the voltage at E and reach a high voltage higher than the withstand voltage of the electronic element _Q4 . F indicates an output terminal.

In particular, since destruction of one element in an integrated circuit leads to failure of each chip, countermeasures are of great significance.

In order to solve these problems, the present invention provides an overvoltage suppression circuit that is installed in a semiconductor integrated circuit and is capable of suppressing the generation of a high voltage that exceeds the breakdown voltage of an element. Explain in detail.

FIG. 1 shows an embodiment of the overvoltage suppression circuit of the present invention, where _Q1 is a field effect transistor, SC is a constant voltage generation circuit, and the output terminal C of the constant voltage generation circuit SC is
The potential of is set to V ₀ . T is an input terminal of the overvoltage suppression circuit, and is connected to a node of another circuit in which it is desired to suppress a voltage increase exceeding a set value. That is, in the example in which the circuit using the bootstrap effect shown in FIG. 4 is the circuit to be protected, it is connected to the terminal D. The source of the field effect transistor _Q1 is connected to the output terminal C of the constant voltage generating circuit SC, the drain is connected to the terminal T, and the control terminal is connected to the terminal T. If the threshold voltage of the field effect transistor Q ₁ is defined as V _TH , the field effect transistor Q ₁ is non-conductive when the potential V _T of the input terminal T is less than or equal to V ₀ +V _TH . However, the potential V _T of the input terminal T is V ₀ +
When the potential becomes equal to or higher than V _TH , the field effect transistor Q ₁ becomes conductive, so that the potential of the input terminal T is fixed to V ₀ +V _TH by the constant voltage generating circuit SC through the field effect transistor Q ₁ . Therefore, it is possible to prevent the potential V _T of the input terminal T from exceeding V ₀ +V _TH .

Specifically, in an example in which the circuit using the bootstrap effect shown in Fig. 4 is the circuit to be protected, the voltage at terminal E in Fig. 4 is 15V, the capacitance _C2 is 0.7pF, and the voltage at terminal E in Fig. 2 is 0.7pF.
When V _P is 15V, the voltage at terminal D increases to 20V when no overvoltage suppression circuit is added, but is suppressed to 16V or less when an overvoltage suppression circuit is added.

Note that terminal T is connected by field effect transistor _Q1 .
The operating speed for lowering the potential of the node connected to _Q1 depends on the current that can flow through the field effect transistor Q1, but in field effect transistors, increasing the current that can flow can be achieved by expanding the channel width or shortening the channel length. Therefore, by shortening the latter channel length, there is an advantage that the operation speed can be increased and the integration can be improved at the same time.

Additionally, most semiconductor integrated circuits are MOS
However, when the overvoltage suppression circuit of the present invention is incorporated into a semiconductor integrated circuit, it can be created at the same time using the MOS technology used to create other circuit parts, which has the advantage of not complicating the manufacturing process. be.

FIG. 2 shows another embodiment of the present invention, in which Q ₁ , Q ₂ ,
Q ₃ is a field effect transistor, C ₁ is a capacitor, _T is an input terminal of the control circuit, and V _P is _a voltage terminal connected to the power supply. It constitutes the generation circuit SC.
That is, the field effect transistors Q ₂ and Q ₃ are connected in series, the power supply voltage V _P is applied to the drain of the field effect transistor Q ₂ , and the source of the field effect transistor Q ₃ is grounded. The control terminals of field effect transistors Q ₂ and Q ₃ are connected to their own drains, the connection point of field effect transistors Q ₂ and Q ₃ is set to node N ₁ , and this node N ₁ is connected to the source of field effect transistor Q ₁ . The drain is connected to the terminal T, the control element is connected to the terminal T, and the source is grounded through the capacitor _C1 . A node connecting the source of field effect transistor Q ₂ and the drain of field effect transistor Q ₃ by appropriately selecting the gm ratio of field effect transistors Q ₂ and Q ₃
The potential of _N1 can be set arbitrarily. In addition,
Capacitor C ₁ is added to stabilize the potential of node N ₁ . The operating principle is the same as shown in FIG.

FIG. 3 shows another embodiment of the present invention, in which Q ₁ , Q ₂ ,
Q ₃ is a field effect transistor, C ₁ is a capacitor, T is an input terminal of the overvoltage suppression circuit of the present invention, and V _P is a voltage terminal. The difference from FIG. 2 is that the control terminal of the field effect transistor Q ₃ is connected to the voltage terminal V _P .

As explained above, the overvoltage suppression circuit of the present invention can suppress the generation of voltage exceeding an arbitrary set value by setting the output level of the constant voltage generation circuit. It has the advantage of being suitable for integration because it can be manufactured at the same time through the manufacturing process, and measures for improving performance are the same as those for the protected circuit, such as shortening the channel length is effective for improving performance. .

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the overvoltage suppression circuit of the present invention, FIGS. 2 and 3 are configuration diagrams showing other embodiments of the present invention, and FIG. 4 is a diagram showing the overvoltage suppression circuit of the present invention. This is an example of an applicable protected circuit. Q ₁ to _{Q 4} ... field effect transistor, C ₁ , C ₂ ...
... Capacity, V _P ... Voltage terminal, T ... Input terminal of overvoltage suppression circuit, SC ... Constant voltage generation circuit, C ...
Output terminal of the constant voltage generation circuit, D...Terminal to which the overvoltage suppression circuit of the protected circuit should be connected, E...Voltage terminal, F...Output terminal of the protected circuit.

Claims (1)

[Claims] 1. In an overvoltage suppression circuit that is provided in a semiconductor integrated circuit and limits the upper limit of voltage rise at a predetermined node, the overvoltage suppression circuit is controlled to be conductive or nonconductive by a voltage applied to a control terminal. The output terminal of the constant voltage generating circuit is connected to one terminal other than the control terminal of the field effect transistor, and the other terminal of the field effect transistor and the control terminal are connected to each other. An overvoltage suppression circuit characterized in that terminals are connected to each other and the terminals are used as input terminals. 2. A constant voltage generation circuit is constructed of second and third field effect transistors and a capacitor, one terminal other than the control terminal of the second field effect transistor and the control terminal are connected to the power supply voltage, and the second field effect transistor is connected to the power supply voltage. The other terminal of the field effect transistor is connected to one terminal of the capacitor, one terminal other than the control terminal of the third field effect transistor, and the control terminal, and the other terminal of the third field effect transistor is connected to the other terminal of the capacitor. The overvoltage suppression circuit according to claim 1, wherein the overvoltage suppressing circuit is connected to the ground and the non-grounding terminal of the capacitor is used as the output terminal of the constant voltage generating circuit.