JPH0228271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to increasing the sensitivity of a solid-state imaging device.

[Background of the invention]

First, an overview of the prior art and its problems will be explained using FIGS. 1 and 2.

FIG. 1 shows an example of the configuration of a typical two-dimensional solid-state imaging device. A pixel array is constructed as a unit of a photodiode 1 and a MOS type transistor (MOST) 2. For example, a horizontal scanning circuit 9 and a vertical scanning circuit 10 each consisting of a MOS shift register scan sequentially by sequentially conducting the MOS transistors 3 and 2, respectively, and convert the charge generated by the light accumulated in the photodiode 1 into a signal. The image (light) signal received by the pixel is taken out as an electrical signal by sequentially leading out from the output end 8 through the lines 6 and 7. The signal lines 6, 7 and the output end 8 may be divided into a plurality of parts depending on the purpose.

FIG. 2 schematically shows the cross-sectional structure of a typical pixel. For convenience of explanation below, electrons are used as signal charges n
Although a channel element will be described, the following explanation can be applied in exactly the same way to a p-channel element in which holes are used as signal charges, just by reversing the conductivity type and polarity.

Si substrate 11 made of p-type Si single crystal and n ⁺ diffusion layer 1
2 constitutes a photodiode, and at the same time n ⁺ diffusion layer 1
2 constitutes a MOS transistor together with a gate electrode 13 made of polycrystalline Si as a source, an SiO ₂ film 16 thinned below the gate electrode 13, and an n ⁺ diffusion layer 14 as a drain. n ⁺
The diffusion layer 14 is usually provided with an electrode 17 made of metal such as Al in order to reduce its electrical resistance.
It is used as the signal line 6 in FIG. The n ⁺ diffusion layer 12 is positively charged via the signal line 6 to which a positive voltage is applied, and electrons 20 of the electron-hole pairs generated by the light 15 flow into the n ⁺ diffusion layer 12 and are discharged. . This discharge continues until the next scanning pulse is applied to the gate electrode 13, and when the n ⁺ diffusion layer 12 is recharged by this scanning pulse, the amount of electrons corresponding to the amount of light is read out at the same time.

Solid-state imaging devices with such a basic configuration have many problems.

First, the amount of signal charge generated by light is small, and the charge capacity of the n ⁺ diffusion layer 12, that is, the junction capacitance 18, is also small. In particular, to improve resolution, it is necessary to make pixels smaller.
Inevitably, the area of the n ⁺ diffusion layer 12 becomes smaller, and the amount of signal charge per pixel becomes smaller and smaller. Furthermore, ^the number of n ⁺ diffusion layers 14 connected to the signal line 6 in FIG. This results in a large capacity. Therefore, the electrical signal appearing at the output terminal 8 is extremely small and buried in electrical noise, making detection difficult. As shown in the patent application No. 51-144800,
Although the signal-to-noise ratio could be improved by increasing only the junction capacitance of the n ⁺ diffusion layer 12, the weak photosensitivity could not be improved.

The second major problem is related to the case where strong light is incident on a part of the element. Electrons that should flow into the n ⁺ diffusion layer 12 and be stored flow into the n ⁺ diffusion layer 14, and as a result, the signal line When other pixels that share the same pixel are being read, the signal is mixed into the signal, causing bright vertical lines to appear on the playback screen, which is called a blooming phenomenon. There are two causes. One is that the junction capacitance 18 is saturated and the photovoltaic force further makes the n ⁺ diffusion layer 12 a negative potential, resulting in electron injection from the n ⁺ diffusion layer 12 to the p-type Si substrate 11. occurs, and even when no positive scanning pulse is applied to the gate electrode, it efficiently flows out to the n ⁺ diffusion layer 14 along the surface where the potential is particularly low due to the operating conditions (as shown by the electron 22). It's called blooming. In order to suppress this, it is necessary to apply a negative bias to the gate electrode to particularly increase the potential under the gate electrode 13, but this requires both positive and negative voltages to drive the element, which is very difficult. . The other is due to photoelectrons 21 generated deep inside the Si substrate 11 due to red or infrared light with ^a small absorption coefficient.
Instead, it constantly flows into the n ⁺ diffusion layer 14, resulting in the creation of a pseudo signal that is unrelated to the timing of readout. (blooming).

Although there are many other problems, the above-mentioned insufficient sensitivity and blooming phenomenon are major problems that can be said to be fatal to solid-state imaging devices with a basic configuration.

[Purpose of the invention]

The present invention provides a means for obtaining a practical solid-state imaging device that has high sensitivity and suppresses the blooming phenomenon by eliminating the above-mentioned drawbacks of the prior art.

[Summary of the invention]

Conventional solid-state imaging devices employ a method in which the photoelectrically converted signal is amplified by a preamplifier provided on the output side of the device, so that noise generated inside the device is also amplified at the same time. Therefore, in the present invention, a phototransistor having an amplification function and a switching means are provided for each pixel section.

[Embodiments of the invention]

FIG. 3 shows an embodiment of the present invention. This figure shows the cross-sectional structure of a pixel. n-type Si substrate 3
1. The p-type impurity diffusion layer 32 and the n-type impurity diffusion layer 33 constitute a phototransistor, and each
Becomes collector, base, and emitter. The n-type impurity diffusion layer 33 is connected to the n-type impurity diffusion layer 35 formed in the p-type impurity diffusion layer 34 through an aluminum (or polysilicon) layer 36 in ohmic contact. n-type impurity diffusion layer 35, 3
7 and polysilicon 38 are each MOS
These are the drain, source, and gate of the transistor, and the aluminum 39 is a signal output line in ohmic contact with the n-type impurity diffusion layer 37. The n-type impurity diffusion layer 40 forms a diode with the p-type impurity diffusion layer 34, and is brought into ohmic contact with the p-type impurity diffusion layer 32 through aluminum 41. The electrode 42 creates a capacitance with the impurity diffusion layer 32,
It may be integrated with polysilicon 38. The n-type impurity diffusion layers 43, 44, 45 are the p-type impurity diffusion layer 3.
Ensure electrical isolation between 2 and 34. 46 is
It is _SiO2 .

FIG. 4 is an equivalent circuit for the embodiment shown in FIG. 3, and FIG. 5 shows its timing chart.
In FIG. 5, the signal accumulation period is T _S and the signal readout period is _TR . The bipolar transistor _T1 is turned ON only during the signal readout period by the coupling capacitor _C1 (v _B > v _E + V _Bi : V _Bi is the base
(the tie voltage between the emitters) can be turned OFF (v _B < v _E ) during the signal accumulation period. The clamping diode _D1 also controls the reset potential of the base potential _vB of the transistor _T1 . The reason for this provision is as follows. Generally, the current amplification factor β (collector current/base current) of a bipolar transistor changes depending on the base current,
Especially in the region where the base current is small, a sufficient value cannot be obtained. In addition, the base current I _B depends on the base-emitter voltage V _BE , and the following relationship holds: I _B ∝exp(qV _BE /kT) (q: elementary charge, k: Boltzmann constant, T: absolute temperature) Therefore, in order to obtain a predetermined base current, the base-emitter voltage must also be set to a certain value or higher.

In this way, the operating point of the bipolar transistor can be set in a region where the current amplification factor is large, making it possible to increase the sensitivity of the imaging device.

Next, suppression of the blooming phenomenon will be explained. When light enters the base 32, the base 32,
Therefore, the potential of the source 33 changes in the positive direction. That is, contrary to the prior art, a reverse bias is applied between the source 35 and the well 34 by light.
As a result, no matter how strong the light is incident, the source 35
Since no electrons are injected from the surface, no blooming occurs. Further, the photoelectrons generated inside the Si substrate 31 are majority carriers here, and cannot enter the reverse biased well 34, so that no blooming occurs at all. Therefore, a solid-state imaging device with high photosensitivity and no blooming phenomenon can be obtained using ordinary n-channel MOS integrated circuit technology.

FIG. 6 shows another embodiment of the invention. This is the MOS transistor section in the previous embodiment formed on the field oxide film, and the purpose is to further improve the integration density. n-type Si substrate 6
1, p-type impurity diffusion layer 62, n-type impurity diffusion layer 6
3 constitutes a phototransistor, each serving as a collector, base, and emitter. The n-type impurity diffusion layer 63 is formed on the upper surface of the n-type impurity diffusion layer 63.
The n-type impurity diffusion layers 64 and 65, the polysilicon 67, and the p-type impurity diffusion layer 66 serve as the drain, source, gate, and substrate of the MOS transistor, respectively. Aluminum 68 is a signal output line in ohmic contact with n-type impurity diffusion layer 65. The n-type impurity diffusion layer 69 forms a diode with the p-type impurity diffusion layer 70 and is brought into ohmic contact with the p-type impurity diffusion layer 62 through aluminum 71. Note that the Si layers 64, 6
6, 65, 70, and 69 can be formed by forming polysilicon by epitaxial growth or CVD, and then crystallizing it by laser annealing. The electrode 72 is the p-type impurity diffusion layer 6
A capacitance may be created between the two and the polysilicon 67 may be integrated. The n-type impurity diffusion layers 73 and 74 are p
Electrical isolation between type impurity diffusion layers 75, 62, and 76 is ensured. 77 is _SiO2 . The structure in which the MOS transistor section is placed on top of Si makes it possible to minimize the separation layer area between pixels and improve integration density.
In addition, the capacity of the signal output line 68 can be reduced to 1/2 or less compared to the conventional method, reducing random noise.
It is possible to improve reading speed. Note that the gist of the present invention, which is to increase sensitivity and suppress the blooming phenomenon, is the same as in the previous embodiment.

In the embodiment of the present invention, T ₁ ,
Although T ₂ is a bipolar transistor or a MOS transistor, T ₂ may be replaced with a junction FET.

〔Effect of the invention〕

According to the present invention, since it is possible to amplify only the signal of each pixel portion, it is possible to relatively reduce the noise generated inside the element, and it is possible to increase the sensitivity of the entire solid-state imaging device. .

[Brief explanation of drawings]

FIG. 1 is a schematic circuit diagram showing the configuration of a conventional solid-state imaging device, FIG. 2 is a sectional view showing the pixel configuration of the conventional solid-state imaging device, and FIG. 3 is a schematic circuit diagram showing the pixel configuration of the solid-state imaging device of the present invention. A sectional view showing the embodiment, FIG. 4 is the third
FIG. 5 is a schematic circuit diagram showing an equivalent circuit of the picture element shown in the figure, FIG. 5 is a timing chart showing potential changes at each node in FIG. 4, and FIG. 6 is a sectional view showing another embodiment of the present invention. 31...n-type Si substrate, 32, 34...p-type impurity diffusion layer, 33, 35, 37, 40...n ⁺ -type impurity diffusion layer, 38...gate electrode, 39, 41,
42, 36... Electrode wiring, I _L ... Photocurrent source, V _V
...Video voltage power supply.

Claims (1)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first impurity region of a second conductivity type provided on the semiconductor substrate, and a first impurity region of a first conductivity type provided on the first impurity region. Second
a phototransistor comprising an impurity region; and fourth and fifth impurity regions of a first conductivity type provided in a third impurity region of a second conductivity type provided on the semiconductor substrate separately from the first impurity region. a pixel consisting of an impurity region and a MOS transistor formed of a gate electrode provided between the impurity regions; and a sixth impurity region of the first conductivity type provided within the third impurity region; The second impurity region and the fourth impurity region are ohmicly connected, the first impurity region and the gate electrode are connected via a capacitance, and the first impurity region and the fourth impurity region are connected through a capacitor.
A solid-state imaging device characterized in that the impurity region and the sixth impurity region are ohmicly connected.