JPH0229256B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a circuit failure monitoring circuit, and more particularly, to a circuit failure monitoring circuit that converts a frame synchronization signal of an input primary group PCM signal into a circuit failure monitoring signal including a frame conversion circuit between a transmission path side and a frame synchronization signal. Regarding the diverted circuit failure monitoring circuit.

Description of the Prior Art In PCM wireless communication equipment that connects PCM carrier ends and transmits PCM primary group signals, logic circuit failures are detected and
It often has the function of issuing alarm information (warning).

There are various conventional circuit fault monitoring methods, but
The following three examples can be cited as representative methods.

(1) A method of dividing the signal passage route into several sections and checking the parity in each section. (2) A method of running a test signal (mainly known pattern signals are used) in parallel with the main signal, and checking the parity of the test signal. Method of monitoring (3) Method of adding redundant bits to the main signal string and monitoring the redundant bits All of the above methods have the same purpose of detecting circuit failures, but they actually configure the circuit. When doing so, the circuit scale and signal frame structure must be considered, which has many disadvantages.

Specific methods corresponding to the above (1) to (3) and their disadvantages are listed using (a) to (c).

(b) To check parity, count the parity of the signal at the input point and temporarily store it. The parity of the next output signal is counted and stored. The stored parity count results of the input point and the output point are compared to determine pass/fail. From the above, to realize this method, parity count circuits on the input side and output side,
It is easy to imagine that the circuit scale will increase because a memory circuit and a comparison circuit are required, and they are also required for each divided section.

(b) A circuit configuration similar to that for the main signal must be provided for the test signal, and the circuit size will be doubled.

(c) In general, the frame structure of PCM primary group signals is internationally standardized according to the recommendations of CCITT, and it is often impossible to provide redundant bits.

OBJECT OF THE INVENTION The present invention has been made by paying attention to the above-mentioned conventional circumstances.Therefore, an object of the present invention is to achieve the same design with a minimum circuit configuration and without restrictions in any PCM primary group signal frame configuration. The object of the present invention is to provide a circuit failure monitoring circuit that can be configured based on ideas.

Structure of the Invention In order to achieve the above object, a circuit failure monitoring circuit according to the present invention is connected to a PCM carrier end and a primary group PCM
In a wireless communication device that bidirectionally transmits primary group PCM signals and is composed of a wireless logical signal processing unit and a transmitting/receiving unit that mainly perform conversion between signal frames and radio frames, primary group PCM multiplexed in a wireless transmission frame is used. The frame synchronization signal of the signal is transferred only in the time domain of the reception frame at the entrance of the reception logic signal processing section with the output of the transmission logic signal processing section,
After frame conversion, the frame synchronization signal in the signal is monitored at the primary group PCM signal interface point to the carrier end, and the wireless logical signal processing unit is monitored for failure. do.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION Hereinafter, one preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a PCM wireless communication device according to the present invention.

In FIG. 1, reference number 11 indicates a PCM carrier end, and the PCM carrier end 11 is connected to a wireless communication device. The part within the broken line 10 in the figure is the logical signal processing unit of the wireless device, which mainly converts frames of PCM primary group signals into wireless frames and sends them to the transmitter. It plays the role of converting it into a frame. The input primary group PCM signal 101 is subjected to frame synchronization by the primary group frame matching circuit 12, and then frame matching is performed to make the temporal relative relationship with the radio frame constant. By the way, frame synchronization is performed by discovering a known pattern that is internationally standardized according to the CCITT recommendations, which is incorporated into the PCM primary group signal. Therefore, it should be emphasized that there is always a known, internationally unified pattern for synchronization in PCM primary group signals.

The frame-aligned primary group PCM signals are multiplexed into specific time slots within the radio frame by the frame conversion circuit 13. 1 for wireless frame
In addition to the next group PCM signal, maintenance telephone signals, service signals, and patterns for radio frame synchronization are multiplexed. The primary group PCM signal multiplexed into the radio frame is sent to the radio transmitter 18, branched, and input to the delay circuit 14. The output of the delay circuit 14 becomes an input to each of the selection circuits 15 together with the reception logic signal (having the same frame structure as the transmitted radio frame) demodulated by the radio reception section 19. Here, the role of the delay circuit 14 will be described. The delay circuit 14 delays the branched transmitting side wireless frame and adjusts the time of both frames at the input point of the selection circuit 15 when the relative temporal relationship between the transmitting side wireless frame and the receiving side wireless frame is different. This is to ensure that the target positions match, and it is not necessary if the system is designed in advance so that both frames match at the input point of the selection circuit 15, so it may be omitted.

Now, the selection circuit 15 determines that the time position is in the first order group.
When the frame synchronization signal of the PCM signal occurs, the branched transmitting side signal is selected, and at other times, the receiving side signal is selected. Therefore, at this point, the frame synchronization signal of the primary group PCM signal multiplexed in the transmitting side radio frame is one in the receiving side radio frame.
It is superimposed on the time slot of the next group PCM signal. Thereafter, the frame conversion circuit 16 converts the radio frame into the frame structure of the primary group PCM signal. The output 102 of the frame conversion circuit 16 is sent to the PCM carrier end 11, and
The signal is branched and input to the failure detection circuit 17. The fault detection circuit 17 can easily check the quality of the frame synchronization signal in the output 102 since it has a known pattern as described above. If the detected frame synchronization signal has an error of more than a certain value,
Outputs a warning.

Next, it will be explained that the monitoring circuit of the present invention can be easily constructed. To this end, it is sufficient to explain that the selection circuit 15 that selects the signal of the radio frame structure on the transmitting side and the receiving side shown in FIG. 1 and the failure detection circuit 17 shown at the end of the same figure can be easily configured. Will.

One embodiment will be described using FIGS. 2 and 3. First, the selection circuit 15 will be explained with reference to FIGS. 2A and 2B. A in FIG. 2 is a specific example of a selection circuit, which is a commonly used 2-to-1 data selector. A and B are inputs, S is a control signal input that controls which of inputs A and B is selected, and Y is an output. Now, it is assumed that a radio frame from the transmitting side is input to the A side, and a radio frame from the receiving side is input to the B side. Figure 2 (b) is a time chart of each input/output point A, B, S, Y in (a). a, b, and c in the A signal sequence are the primary group on the transmitting side
It is assumed that the signal is a frame synchronization signal of a PCM signal, and a', b', and c' in the B signal sequence are time slots for frame synchronization signals of a primary group PCM signal on the receiving side, that is, on the other party's side. In S, only the frame synchronization signal position becomes "L" level, and the A side is selected. Therefore, the output Y becomes as shown in the figure.

Next, according to FIG. 3 A and B, the fault detection circuit 17 is
Explain. FIG. 3A shows a specific example of the configuration of the fault detection circuit 17. is the first-order group PCM signal train branched at the interface point with the carrier end, and a,
It is assumed that b and c are frame synchronization signals. is a comparison signal that is generated for comparison of frame synchronization signals and has a pattern equivalent to the frame synchronization signal at the same time position. Note that this comparison signal is a signal prepared for frame synchronization at the primary group frame input point, and is simply used here. Now, each of the above becomes an input to the exclusive OR circuit 17, and if they match, "L" level is output, and if they do not match, "H" level is output. The NAND gate ¹⁷² connected to the output of the exclusive OR circuit ₁₇₁ controls the alarm output when only the frame synchronization signal position time becomes "H" level. The time chart of the circuit shown in FIG. 3A is shown in FIG.

Finally, a specific time slot of a frame synchronization signal may contain signals other than those for frame synchronization, such as a device alarm, but these are not covered by the present invention and are therefore excluded. It goes without saying that when there is an abnormality in the input of the primary group signal, backup countermeasures are applied as necessary to prevent false triggering of a circuit failure, such as by masking the failure monitoring circuit output with abnormality detection information.

Effects of the Invention The present invention is constructed and operates as described above, and the present invention produces the following effects.

(1) The circuit fault monitoring circuit according to the present invention has a first-order group
In order to utilize the frame synchronization signal of the PCM signal as a monitoring signal, there is no need to add redundant bits for monitoring, and furthermore, the signal configuration from the PCM carrier end to the frame conversion circuit described in Figure 1 is CCITT.
The recommendations are standardized, and even circuit parts to which it is impossible to add redundant bits can be monitored without any restrictions.

(2) The circuit failure detection circuit according to the present invention can be configured extremely easily.

(3) Since the present invention utilizes the frame synchronization signal for monitoring, the same design concept can be applied to other n-order group PCM signals.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a wireless communication device to which the present invention is applied, and FIGS. 2A and 2B are a specific configuration diagram of a signal selection circuit and its time chart.
Figures 3A and 3B show a specific configuration diagram of the fault detection circuit and its time chart. 10...Wireless logic signal processing unit, 11...PCM
Carrying end, 12... Primary group frame matching circuit, 13...
...Frame conversion circuit, 14...Delay circuit, 15...
...Selection circuit, 16...Frame conversion circuit, 17...
...fault detection circuit, 18...wireless transmitter, 19...
Wireless receiving section.

Claims (1)

[Claims] 1 A transmitting side logic signal processing unit that interfaces with an information source including a frame synchronization pattern and converts the information source side frame into a transmission line side frame, and a receiving unit that converts the transmission line side frame into the information source side frame. In a PCM signal transmission device constituted by a logical signal processing section on the side, only the frame synchronization pattern is returned at the output point of the logical signal processing section on the transmitting side to the input point of the logical signal processing section on the receiving side,
A circuit fault monitoring circuit characterized in that a fault in the transmitting/receiving logical signal processing section is monitored by inspecting the frame synchronization pattern at an output point of the receiving side logical signal processing section.