JPH0229268B2 - HEIRETSUCHOKURETSUHENKANKAIRO - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parallel-to-serial conversion circuit, and more particularly to a circuit for converting variable length parallel data into serial data.

Generally, when digitally transmitting a facsimile signal, etc., the facsimile signal is encoded in a predetermined manner to obtain variable length parallel data, and then the parallel data is converted to serial data and transmission control is performed. become.

Conventionally, as a circuit for converting such variable length parallel data into serial data, a circuit constructed of a shift register that can load parallel data and a clock circuit that controls the operation timing of the shift register has been used. The clock output timing of the clock circuit is appropriately controlled to obtain serial data corresponding to the data length of the parallel data input to the shift register.

However, such conventional parallel-to-serial conversion circuits do not operate the above-mentioned clock when inserting specific data (for example, "O" data to ensure transparency of identification flags, etc.) into converted serial data. This has the disadvantage that output control becomes extremely complicated.

This invention has been made in view of the above circumstances, and provides a parallel-to-serial conversion circuit that can not only convert variable-length parallel data to serial data but also easily insert specific data into the converted serial data. The purpose is to provide.

That is, the present invention includes a selection information generating means that sequentially generates selection information using a counter or the like, and a data selector that receives parallel data and sequentially selects and outputs the input parallel data based on the selection information. It constitutes a parallel-to-serial conversion circuit, and by using the function of this data selector, for example, the data selector can be made inactive at a desired point (thereby, the data selector output is set to "0" unconditionally).
data is inserted), or by adding fixed data other than parallel data to other input addresses of the data selector in advance, and selecting this fixed data using the above selection information at a desired time. Perform data insertion.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A parallel-to-serial conversion circuit according to the present invention will be described in detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 shows an embodiment of a parallel-to-serial conversion circuit according to the present invention.

This embodiment circuit includes a data selector 1, a counter 2, a digital converter 3, and a control processing section 4, and is configured as shown in the figure. In other words, variable-length parallel data PD (in this example, data with a maximum length of 10 bits) that is desired to be serially converted,
and specific fixed data CD that is desired to be inserted (in this example, up to 6 types of data can be inserted) are applied to each input terminal at addresses 0 to 15 of data selector 1. The data is sent to the selection terminals A, B, of the data selector 1,
They are selectively outputted in accordance with the contents of the 4-bit count output of counter 2 added to C and D, respectively.
For example, if the count output of counter 2 is a binary signal and has the content "0, 0, 0, 0", then the data added to the input terminal at address 0 of data selector 1, that is, the example shown in FIG. In other words, the data of the first bit of the parallel data PD is the data SD.
Similarly, if the count output of counter 2 is "0, 0, 0, 1", the data added to the input terminal at address 1 of data selector 1, that is, among the parallel data PD Second
The bit-th data is selected and output as data SD, and the count output of counter 2 is "1, 0, 1, 0".
If the content is 10 of data selector 1
One of the data added to the input terminal of the address, that is, the fixed data CD, is selectively output as data SD. In this embodiment circuit, the digital comparator 3 receives the variable length parallel data.
It accepts and compares data length information PDL indicating the data length of PD and the count output of counter 2,
When these contents match, a match detection signal DT is generated.
It has a function of outputting to the control processing section 4.
In addition, the control processing unit 4 sets the data selector 1 to an active state or an inactive state by the signal EN, and
INC increments the count contents of the counter 2 at a timing synchronized with a predetermined clock signal CK, initializes the count contents of the counter 2 with the signal CL, and arbitrarily forms P1 and P2 in the control processing section 4 with the signal L. , P3, and P4 into the counter 2, and also has the function of transferring the data SD output from the data selector 1 at the timing of the clock signal CK (however, the transfer means is not shown). and the above coincidence detection signal from the digital comparator 3
By adding DT, it is recognized that the serial conversion of one piece of variable-length parallel data has been completed, and predetermined processing to be described later is performed.

FIG. 2 is a flowchart showing an example of the operation of the control processing section 4, and the specific operation of the embodiment circuit shown in FIG. 1 will be explained below with reference to this flowchart.

First, a normal parallel-to-serial conversion operation that does not require insertion of specific data will be described.

Now, for example, parallel data PD having a data length of 8 bits (this data length information PDL is "0, 1,
1, 1'') is applied to the input terminals from address 0 to address 7 of the data selector 1, the control processing unit 4 activates the data selector 1 by the signal EN as an initial operation (see Fig. 2). (Refer to step <10>), then the counter 2 is set by the signal CL.
Initialize the count contents (see second step <20>). As a result, the count output of counter 2 is “0,
0, 0, 0", and the above parallel data
Of the PDs, the bit data applied to the input terminal at address 0 of the data selector 1 is selected and output as data SD. This output data SD is transferred in synchronization with the timing of the clock signal CK output from the control processing 4 (step <
30＞Reference). Next, the control processing unit 4 increments the count contents of the counter 2 to "0, 0, 0, 1" by the signal INC, and increments the count contents of the counter 2 to "0, 0, 0, 1", and increments the bit applied to the input terminal at address 1 of the data selector 1 of the parallel PDs. data is selected as data SD and transferred in the same manner (see step <40> in Figure 2). Thereafter, the control processing unit 4 performs this count content increment operation and data transfer operation until the count content of the counter 2 reaches "0, 1, 1, 1", which is the content of the data length information PDL of the parallel data PD. It is executed repeatedly (see step <90> in Figure 2), and when the contents match "0, 1, 1, 1", the match detection signal DT output from the digital comparator 3 is accepted and the corresponding It is recognized that the serial conversion of the parallel data PD has been completed, and, for example, the data selector 1 is made inactive and the next parallel data is applied. Of course, data SD is the above parallel data
This means that it was transferred as serial data compatible with PD.

For reference, FIG. 3 shows the temporal relationship of each signal in such a parallel-to-serial conversion operation of the embodiment circuit.

Next, the operation when inserting "0" data as specific data into the serial data SD will be explained.

Step <40> and Step << shown in the flowchart of FIG. 2 for arbitrary parallel data PD
90>, when inserting "0" data for the purpose of ensuring the transparency of the identification flag (see step <50> in Figure 2), the parallel data
Step <40> for the relevant bit of PD (the bit before the bit for which "0" data is desired to be inserted)
The control processing section 4 is programmed to make the data selector 1 inactive at the time when the processing of . Thereafter, the control processing section 4 stops the signal INC to interrupt the counting content increment operation, and in this state operates to transfer the data SD for an arbitrary clock period (see step <70> in FIG. 2).
As a result, "0" data is transferred by the number of bits corresponding to the clock period mentioned above, and the serial data is transferred.
This "0" data will be inserted into the SD. When this “0” data insertion operation is completed, the control processing unit 4 again activates the data selector 1, and the count contents of the counter 2 are compared with the contents of the data length information PDL of the parallel data PD, which is compared by the digital comparator 3. The processes of step <40> and step <90> described above are repeated until they match. In such a parallel-to-serial conversion operation of the embodiment circuit, the temporal relationship of each of the above signals is shown in FIG. Shown for reference. When inserting "0" data again for one parallel data PD, once the process of step <40> for that bit is completed, steps <60> to <80> are executed in the same manner as described above.
> process. The subsequent operations are similar to normal parallel-to-serial conversion operations.

Furthermore, if you wish to insert specific fixed data CDs in addition to the above-mentioned insertion of "0" data (not shown in the flowchart of Fig. 2), the data you wish to insert among these fixed data CDs may be The count output of the counter 2 is set so that it is selectively output from the data selector 1. That is, the control processing section 4 forms preset data necessary to select the data desired to be inserted using the signals P1, P2, P3, and P4, and loads the formed preset data into the counter 2 using the signal L. . After that, if the selected fixed data is transferred at the timing of the clock signal CK, this fixed data will also be inserted serially into the data SD.

The format of the above fixed data CD is arbitrary.
They may be different types of serial data, multiple bits of parallel data (in this case, the maximum data length is 6 bits in the embodiment shown in Figure 1), or even It may be the “0” data mentioned above. Therefore, if the fixed data CD is serial data, the contents of counter 2 are held until the serial data is completely transferred, and if it is parallel data, the contents of counter 2 are held as in the parallel-to-serial conversion operation described above. It is sufficient to sequentially increment the contents of . Generally, such fixed data CD is inserted every time the aforementioned variable length parallel data PD is serialized. However, if this fixed data CD is the aforementioned "0" data and it is necessary to insert the "0" data during the parallel-to-serial conversion operation, the embodiment circuit shown in FIG. An appropriate memory is provided to temporarily hold the count contents of counter 2 when incrementing, and after the insertion of "0" data by loading the preset data into the counter is completed, the increment operation is restarted from the count contents held above. Or, when it is desired to insert "0" data, the incrementing operation of the counter 2 is temporarily stopped and the preset data necessary to select the "0" data is directly added to the data selector 1 without going through the counter 2. west,
The incrementing operation of the counter 2 may be restarted after the "0" data insertion based on the preset data is completed.

Further, in the embodiment shown in FIG. 1, the first bit of the variable length parallel data PD is applied to the input terminal at address 0 of the data selector 1, but the present invention is not particularly limited to this. That is, a function of loading the count contents corresponding to the address of the input terminal to which the first bit of the variable length parallel data PD is added into the counter 2 as preset data, and data length information of the variable length parallel data PD.
If we add a function to convert the contents of PDL, that is, to convert the number of bits corresponding to the address from address 0 to the address of the input terminal to which the first bit of this parallel data PD is added to the contents of this data length information PDL,
No matter where the variable length parallel data PD is applied to the input terminal of the data selector 1 at any address, it can be effectively serialized.

Note that the maximum data length that can be serially converted from the variable length parallel data PD is determined by the input capacity of the data selector 1, and is of course not limited to the data length described above.

As explained above, the parallel-to-serial conversion circuit according to the present invention has the advantage of effectively serializing any variable-length parallel data and easily inserting other specific data. be effective.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an embodiment of the parallel-serial conversion circuit according to the present invention, FIG. 2 is a flowchart showing an example of the operation of the control processing section in the embodiment circuit shown in FIG. 1, and FIG. FIG. 4 is a timing chart showing an example of the operation of the embodiment circuit shown in FIG. 1 as a whole. 1...Data selector, 2...Counter, 3...
...Digital comparator, 4...Control processing section.

Claims (1)

[Claims] 1. Parallel/serial processing that converts variable-length m-bit (m: natural number) parallel data into serial data based on data length information that is input along with the parallel data as information indicating the data length m. The conversion circuit includes a counter that sequentially counts based on a predetermined counting signal synchronized with the bit time of the serial data, and one of a plurality of input terminals corresponding to each address from 0 to n (n: a natural number, n≧m). The parallel data is input to one or all parts, and among the input parallel data, the data input corresponding to the address specified based on the counting contents of the counter are sequentially input according to the counting operation of the counter. a data selector that selectively outputs; a comparator that successively compares the contents of the data length information and the count contents of the counter and outputs a coincidence detection signal when these contents match; and based on the input of the parallel data, The data selector is activated, and the initial counting value of the counter is set corresponding to the input end address of the data selector to which the first data of the parallel data is input, and the data selector is activated based on the coincidence detection signal. A parallel-to-serial conversion circuit comprising: a control means that makes inactive; and a parallel-to-serial conversion circuit. 2. In a parallel-to-serial conversion circuit that converts variable-length m-bit (m: natural number) parallel data into serial data based on data length information that is input along with the parallel data as information indicating the data length m, A counter that sequentially counts based on a predetermined counting signal synchronized with the data bit time, and a parallel circuit connected to some or all of the plurality of input terminals corresponding to each address from 0 to n (n: natural number, n≧m). A data selector receives data, and sequentially selects and outputs the input data corresponding to the address specified based on the counting contents of the counter among the input parallel data according to the counting operation of the counter. , a comparator that successively compares the contents of the data length information and the count contents of the counter and outputs a coincidence detection signal when these contents match; and activating the data selector based on the input of the parallel data. At the same time, a count initial value of the counter is set corresponding to an input end address of the data selector into which the first data of the parallel data is input, and the data selector is made inactive based on the coincidence detection signal. 1, a control means for inactivating the data selector for a predetermined bit time of the serial data at a predetermined time after inputting the parallel data, and temporarily stopping application of a count signal to the counter during that time; A parallel-to-serial conversion circuit comprising: second control means for stopping and holding the count contents.