JPH0230058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data error detection and correction system for a vector processor.

[Conventional technology]

As shown in Figure 3, a data processing system including a vector processor consists of a memory MSU (main storage unit), a memory control unit MCU (memory control unit), a vector unit VU,
Channel device to which the scalar unit SU, magnetic disk device (not shown), etc. are connected
Consists of CHP etc. Vector unit VU is the fifth
As shown in the figure, vector register VR that can be seen (specified) from the program and addition (Add),
Multiplication (Mult), division (Div) operation pipeline,
It also includes a mask register (not shown).
These calculation pipelines can operate in parallel. Addition is, for example, a+b=c, read data a and b from memory MSU, and add result c.
is written to the memory MSU. Specifically, this is a scalar operation and is performed by the scalar unit SU. The vector operation is 〓+〓=〓, that is, a ₁ a ₂ 〓 a _o + b ₁ b ₂ 〓 b _o = c ₁ c ₂ 〓 c _o , and the vector elements a ₁ and b ₁ , a ₂ and b ₂ ,
. . . are added, and the results c ₁ , c ₂ , . . . are obtained. Therefore, the amount of data handled is much larger than that of scalar operations.
For this reason, the vector register VR has a large capacity of 64KB. The data is in the memory MSU, and a ₁ to an, b ₁ to bn are successively read from the memory by a fetch instruction and taken into the vector register VR,
The addition results c ₁ to cn are stored in the memory MSU via the vector register VR.

[Problem to be solved by the invention] Since the scalar unit SU handles less data, general-purpose registers are used as registers.
In the vector unit VU, static RAM is used because the register VR has a large capacity. However, in RAM (random access/memory), soft errors may occur due to alpha ray irradiation, although this is extremely rare. A similar problem occurs with buffer storage (cache memory), but since cache memory is originally a piece of hardware that is invisible to the program, the same data is in memory, so if an error occurs, it can be retrieved from memory. Vector registers are registers specified by the program, so such a method cannot be used.

An error checking and correction (ECC) circuit is effective for 1-bit errors. The memory MSU also has patrol and correction functions, and performs 1-bit error correction and 2-bit error detection (SECDEC). FIG. 5 shows an ECC circuit for load/store data provided in the memory control unit MCU, which includes a register REG, a check circuit ECC CHK that checks the data and generates a syndrome indicating the error location if there is an error; Correction circuit that inverts error bits due to the syndrome
Consists of ECC CORR. Furthermore, since it is necessary to add ECC bits to the store data, an ECC generator ECC GEN that generates the bits is provided.

However, such an ECC circuit cannot adequately cope with soft errors occurring in the vector register VR. Another disadvantage is that the access time becomes long. In other words, to perform ECC, as above
Two cycles are required because the ECC check is performed to generate a syndrome bit indicating the error position, and the bit is further decoded to invert (correct) the error bit.

The present invention aims to improve these points and provide an ECC method that is effective for correcting bit errors in vector registers.

[Means for solving problems]

The present invention provides an error detection and correction method for operation data of a vector processor that includes a vector register that loads data from a memory through a memory control device and stores data into the memory through the memory control device, and an operation pipeline.
An error detection and correction circuit is provided on the input side of the arithmetic pipeline, and an error detection and correction bit generation circuit is provided on the output side of the arithmetic pipeline. The present invention is characterized in that a detection circuit is provided, and even if the error detection circuit detects a data error, the data is loaded into a vector register or stored in the memory as is, and in the event of a data error at the time of storage, data correction means in the memory is activated. It is something.

[Effect]

If ECC is performed on the input side of the arithmetic pipeline, even if a soft error occurs in the vector register, it can be corrected sufficiently, and the memory controller
Since ECC is not performed and only error checking is performed, an increase in access time can be avoided. That is, since vector calculation is a pipeline process, the required data (E ₀ ~
En) ₁ , (E ₀ ~ En) ₂ , ... are all taken in sequentially (load L), these data are passed to a sequential operation such as an addition (Add) pipeline, and the addition results are sent to the memory MSU via a vector register etc. However, this store is performed only after the store timing has arrived, so the ECC is stored before the operation (addition).
Even if ECC bits are generated after addition, these bits are not sufficiently absorbed and do not lead to an increase in access time.

The memory control device only checks errors in load data and store data, but does not perform error correction. However, once an error is identified, memory data can be easily corrected using the memory's storage correction function. reliability can be maintained.

〔Example〕

FIG. 1 shows an embodiment of the present invention. As aforementioned
MSU is memory, MCU is memory control unit, VU is vector unit, and SU is scalar unit. For load/store data related to the vector unit, the memory control unit MCU does not have an ECC circuit, but an ECC circuit that simply checks for errors.
CHK will be established. Instead, an ECC circuit is provided on the input side of the arithmetic pipeline of the vector unit VU, and an ECC bit generation circuit EG is provided on the output side. Although FIG. 1 shows these circuits only for the addition (Add) pipeline, the same applies to the multiplication (Mult) and division (Div) pipelines.

When loading data from the memory MSU to the vector unit VU, the error detection circuit ECC CHK of the memory control unit MCU checks for errors and outputs a signal LOAD ECCERR if there is an error. Since no data correction is performed, even if there is an error, the error data is loaded into the vector register VR. There are two possible causes of this data error: the data in the memory MSU is erroneous, and the error occurred during data transfer from the MSU to the MCU. For the former, it is better to correct the memory data, but for the latter, it is not necessary.

When data is stored from the vector unit VU to the memory MSU, the error detection circuit ECC CHK of the memory control unit MCU checks for errors and outputs a signal ST_ECCERR if there is an error. However, since this circuit does not perform error correction, the error data is stored as is in the memory MSU. It is best to correct this as soon as possible, so the signal ST
ECCERR activates the memory collection function,
Causes memory data to be corrected.

Since the arithmetic pipeline has an ECC circuit on its input side, error detection and correction are performed using the arithmetic data from the vector register and the ECC bits attached to the data. Furthermore, the ECC bit generation circuit EG on the output side of the arithmetic pipeline generates ECC bits for the data of the arithmetic result.

As before, an ECC circuit is provided in the memory control unit MCU for load/store data regarding the scalar unit SU and the channel device. this
With the ECC circuit, when the check circuit ECC CHK detects that there is an error in the load/store data related to the vector unit VU, the memory MSU
The above data can be corrected. In other words, since the address of the data with the error is known, the data at that address is read from the memory MSU and sent to the scalar unit of the memory control unit MCU.
It is sufficient to correct this using the ECC circuit and write the corrected data to the corresponding address in the memory MSU. Second
The figure shows the hardware related to this address.

The vector unit VU generates an address on the memory MSU of the data group when performing a vector operation. ADDGEN is the address generation circuit. The address generated by the circuit is the register REG,
After entering the port PORT and determining the priority of memory access, the memory address register MSAR
and access the memory MSU. Further, the address is sequentially stored in the address pipeline APL. Memory MSU to vector unit VU
MCU check circuit ECC when loading data
Signal LOAD when CHK detects a data error
It outputs ECCERR, which causes the address output by APL to be taken into the correction address register CAR through OR gate G. This is done through the ports and registers on the scalar unit SU side.
It enters the MSU and causes the above-mentioned memory read, correction, and write operations to be performed. In addition, when the check circuit ECC CHK of the MCU generates a data error when storing data from the vector unit VU to the memory MSU, the circuit generates a signal ST ECCERR, which also passes through gate G and corrects the output address of APL to the address register CAR. to be taken into.

〔Effect of the invention〕

As explained above, according to the present invention, error detection and correction of vector operation data can be performed without increasing the memory access time of the vector unit, and reliability of the memory data can be ensured by correction using its correction function. It is possible and very effective. Furthermore, all errors in the memory MSU, vector register VR, and on the transfer path between them can be corrected by a single error detection and correction means. Furthermore, by shortening the processing time in the memory control unit MCU, access conflict control with CHP and SU is also simplified.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams showing an embodiment of the present invention, Figure 3 is a block diagram showing the configuration of a vector calculation system, Figure 4 is an explanatory diagram of vector calculation, and Figure 5 shows a conventional example. It is a block diagram. In the drawing, MSU is a memory, MCU is a memory control unit, ECC is an error detection and correction circuit, EG is an ECC bit generation circuit, and ECC CHK is an error detection circuit.

Claims (1)

[Scope of Claims] 1. Error detection and correction of operation data of a vector processor equipped with a vector register that loads data from a memory through a memory control device and stores data into the memory through the memory control device, and an operation pipeline. In this method, an error detection and correction circuit is provided on the input side of the arithmetic pipeline, and an error detection and correction bit generation circuit is provided on the output side of the arithmetic pipeline. An error detection circuit for data is provided, and even if the error detection circuit detects a data error, the data is directly loaded into a vector register or stored into the memory, and when a data error occurs during storage, a data correction means in the memory is activated. Features an error detection and correction method for vector processors.