JPH0230116B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a semiconductor memory device.

FIG. 1 shows an example of the layout of a conventional storage device. In Figure 1, the two data line pairs (D ₁ , ₁ ) and (D ₂ , ₂ ), which are the two inputs of the sense amplifier SA, are arranged in opposite directions with respect to the sense amplifier, and the sense amplifier is connected to the data lines. It is arranged only on the same end side. In this case, the layout pitch d of the sense amplifier, that is, the length between adjacent data lines, is determined by the pitch of the memory cells connected to the data lines.

In general, memory cell sizes tend to shrink as the capacity gradually increases from 64K to 256K to 1M bits. This naturally extends to the sense amplifiers connected to the memory cells, and it has become extremely difficult to fit the sense amplifiers SA ₁ and SA ₂ into the memory cell pitch, making it difficult to realize high-density storage devices. It had become one of the obstacles. Furthermore, as memory cells become smaller, sense amplifiers are required to have higher sensitivity, but it has been difficult due to circuit technology to realize highly sensitive sense amplifiers in a limited pitch.

An object of the present invention is to provide a semiconductor memory circuit device with high density and high sensitivity.

In the semiconductor memory device according to the present invention, two data lines connected to two inputs of a sense amplifier are arranged in opposite directions, and the sense amplifiers are arranged in the direction of the data lines with respect to a plurality of pitches of the data lines. It is characterized by its placement.

An embodiment of the storage device according to the present invention will be described with reference to FIGS. 2 and 3. In the example shown in FIG. 3, the memory cell MC is constructed of a well-known one-transistor type. The word lines W ₁ to _{W 6} driven by the row decoder 12 are data lines D ₁ , ₁
As shown in the figure, memory cells MC are arranged at the intersections with MC and MC to form a memory cell matrix. The characteristic feature here is the arrangement of the sense amplifiers SA (SA ₁ , SA ₂ ) and (SA ₃ , SA ₄ ), which form a set of two sense amplifiers stacked on top of each other at the same pitch. Line D ₁ , ₁ D ₂ , ₂ ...D ₄ ,
D ₄ is connected. With such an arrangement,
As shown in FIG. 2, each of the sense amplifiers SA ₁ and SA ₂ can be laid out with a width approximately twice that of the conventional layout. In other words, even if the memory cell pitch becomes smaller from d to d'(d'<d), it becomes possible to use a sense amplifier with higher sensitivity. Sense amplifiers SA ₃ and SA ₄ are arranged similarly. These sense amplifiers SA ₁ , SA ₂ , ...SA ₄
The amplified and detected data is selectively transmitted to the data bus DB via gate circuits 16 and 17 controlled by the output of the column decoder 11, and output via the output amplifier 13. data bus
Write gates 15 and 14 are coupled to DB,
It is configured such that true complement inputs 1N, 1 are transmitted in response to write signal W.

Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above embodiments and can be applied to any type of storage device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional storage device, and FIGS. 2 and 3 are block diagrams showing a storage device according to an embodiment of the present invention. MC...Memory cell, _{SA1 to SA4} ...Sense amplifier, _{D11 to D44} ...Data line, _W1 to _W6 ...
word line.

Claims (1)

[Claims] 1 A plurality of sense amplifiers are arranged adjacent to each other in the column direction, memory cells whose size is sufficiently smaller than the sense amplifiers are arranged in a matrix, and a plurality of memory cells connected to each sense amplifier and extending in the row direction are arranged. In a storage device where data lines are arranged, two adjacent
The two sense amplifiers are shifted from each other in the row direction, and the total length in the column direction of two adjacent sense amplifiers is reduced, and the connection to the two sense amplifiers is made using this reduced length. A semiconductor memory device characterized in that all data lines are arranged in the row direction.