JPH0230222B2 - - Google Patents

Description

[Detailed description of the invention]

(Technical Field) The present invention relates to a demodulator, and particularly to a demodulator for sampling and shaping a demodulated baseband signal for digital conversion in a digital carrier transmission system.
The present invention relates to a demodulator that improves timing signal generation means. (Prior Art) A demodulator used in a digital carrier wave transmission system generally requires a timing signal having a predetermined period and timing phase in order to convert a demodulated baseband signal into a digital signal. Generally, a timing synchronization circuit that reproduces a predetermined timing signal from a demodulated baseband signal is used as the generating means. FIG. 1 shows an example of a conventional demodulator, which includes a first phase detector 1 and a second phase detector 2.
, π/2 phase shifter 3, 2-bit A/D converters 4 and 5, carrier regeneration circuit 6, full-wave rectifier circuits 7 and 8, and phase adjustment circuits 9 and 1.
0, a first timing synchronization circuit 14 consisting of a phase comparator 11, a low-pass filter 12, and a voltage controlled oscillator 13, and a second timing synchronization circuit having the same configuration and function as the first timing synchronization circuit. It is equipped with a synchronous circuit. This conventional example shows the case of a demodulator for four-phase phase modulated waves, and the four-phase phase modulated signal S is
The signals are branched and input to first and second phase detectors 1 and 2, respectively. On the other hand, a carrier wave regeneration signal with a predetermined phase is outputted from the carrier wave regeneration circuit 6, which is branched into two, and passed through the π/2 phase shifter 3 as a reference signal having a mutual phase difference of π/2 radians. the first and second phase detectors. In the first and second phase detectors 1 and 2, a four-phase phase modulation signal S branched into two
are synchronously detected via the reference signal and sent as binary baseband signals to 2-bit A/D converters 4 and 5, respectively, and input to corresponding full-wave rectifier circuits 7 and 8. In full-wave rectifier circuits 7 and 8, each binary baseband signal is doubled and a timing signal is extracted. This extracted signal is input to the first and second timing synchronization circuits 14 and 15, respectively, but since it is sufficient to explain the operation of either one of these timing synchronization circuits, A timing synchronization circuit will be selected and explained. In the first timing synchronization circuit 14, the extraction timing signal output from the full-wave rectifier circuit 7 is input to the phase comparator 11, which includes the phase comparator 11, the low-pass filter 12, and the voltage-controlled oscillator 1.
3 forms a phase synchronization system, and the voltage controlled oscillator 13 outputs a reproduction timing signal which is phase synchronized with the extraction timing signal and whose jitter component is suppressed by an equivalent narrow band pass characteristic. This reproduction timing signal is input to the phase modulation circuit 9, the phase of which is adjusted, and the signal is input to the 2-bit A/D converter 4. Similarly, in the second timing synchronization circuit 15, a reproduction timing signal with suppressed jitter components is output in response to the extraction timing signal inputted from the full-wave rectification circuit 8, and the phase adjustment circuit 10 adjusts the phase. Been 2
The signal is input to the bit A/D converter 5. In the 2-bit A/D converters 4 and 5, as described above, the binary baseband signals inputted from the first and second phase detectors 1 and 2, respectively, are input to the phase adjustment circuits 9 and 10, respectively.
The signal is sampled, shaped, and digitally converted by the timing signal input via the input signal, and is output as data signals _X1 and _Y1 . The 2-bit A/D converters 4 and 5 output data signals X ₂ and Y ₂ as well as the data signals X ₁ and Y ₁ , respectively, and these data signals
X ₁ , X ₂ , Y ₁ and Y ₂ are input to a carrier wave reproducing circuit 6, and a predetermined carrier wave reproducing signal is generated. This carrier wave reproduction signal is divided into two parts, one of which is directly input to the first phase detector 1, and the other is input to the second phase detector 2 via the π/2 phase shifter 3. The operations of the first and second phase detectors 1 and 2 have already been described above. Also,
The operation of the carrier wave regeneration circuit 6 is described in detail in, for example, the carrier wave regeneration circuit (Japanese Unexamined Patent Publication No. 131151/1983), so the explanation thereof will be omitted. In this conventional demodulator, in the timing synchronization circuit used for timing signal regeneration, in order to ensure that the demodulated baseband signal is sampled at the optimal timing in the A/D converter, the phase There is an operational drawback in that phase adjustment must be performed using adjustment circuits 9 and 10. (Object of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks, and to form a phase control system for a timing signal by referring to a data signal output from an A/D converter, so that the phase control system can be constantly controlled without requiring phase adjustment. An object of the present invention is to provide a demodulator that can sample and shape a demodulated baseband signal at optimal timing. (Structure of the Invention) The demodulator of the present invention has N (N=2, 4, 8, 16,
…) Phase modulation method or L ² (L=2, 3, 4,
...) A predetermined band-limited digital carrier modulation signal based on the value orthogonal amplitude modulation method is input, and synchronous detection is performed via a carrier regeneration signal having a mutual phase difference of π/2 radians. first and second generating demodulated baseband signals;
The band-limited signals of the pair of demodulated baseband signals are inputted to a pair of phase phase detectors, and are digitally converted through a sampling shaping action using a predetermined timing signal, and each is converted into a digital signal by a predetermined value k (an integer of 1 or more). ) a pair of k-bit A/D converters output as data signals of the series; and at least two or more specific data signals of the pair of k-series data signals output from the pair of A/D converters. a carrier wave regeneration circuit that inputs a carrier wave signal and generates a carrier wave recovery signal corresponding to the carrier wave signal of the digital carrier wave modulation signal, and outputs it for synchronous detection to the pair of phase detectors; a π/2 phase shifter that provides a phase difference of π/2 radians to each other in order to supply the carrier-wave regenerated signal to the pair of phase detectors for synchronous detection; at least one variable phase generating means for automatically controlling and adjusting the phase of the output signal of the fixed frequency oscillator forming the oscillation source of the timing signal via at least one system of predetermined phase control signals; and the pair of A/Ds.
A data signal for specific polarity determination among a pair of k-series data signals output from the converter is input, and the differential coefficient of the band-limited baseband signal at the sampling point of the A/D converter is calculated. A polarity discrimination circuit for discriminating polarity and a phase control signal detection system of a timing synchronization system are formed together with the polarity discrimination circuit, and the pair of A/ A logic circuit that generates and outputs the phase control signal by performing a predetermined logical operation on a predetermined baseband signal position determination data signal among the k-series data signals output from the D converter. and a predetermined timing synchronization circuit formed by. (Embodiments of the Invention) Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 2 is a block diagram showing the main parts of the first embodiment of the present invention, and shows the case of a demodulation device using a four-phase phase modulation method. In the figure, in this embodiment, a first phase detector 16, a second phase detector 17,
π/2 phase shifter 18, 2-bit A/D converters 19 and 20, carrier regeneration circuit 21,
Polarity discrimination circuit 22, logic circuit 23, low-pass filter 2
4. Variable phase shifter 25 and fixed frequency oscillator 26
A timing synchronization circuit 27 is provided. In FIG. 2, a four-phase phase modulation signal S in an intermediate frequency band is branched into two, passed through first and second phase detectors 16 and 17, and 2-bit A/D converters 19 and 20. data signal X ₁ ,
The operation process of converting and outputting X ₂ , Y ₁ and Y ₂ is as already explained for the conventional example. Therefore, the description will focus on the operation of the timing synchronization circuit 27, which is the main focus of the present invention. Before explaining the first embodiment shown in FIG. 2, the principle of operation of the timing synchronization circuit will be explained with reference to the operation explanatory diagrams of the timing synchronization system shown in FIGS. 3a and 3b. In FIG. 3a, m ₁ to _{m 4} indicate waveforms of band-limited binary baseband signals, and this band-limited binary baseband signal is sampled in a predetermined 2-bit A/D converter. data signals X 1 and X ₂ , identified by the reference levels l ₁ , _{l 2} and l ₃ shown in FIG.
is converted to The relationship between this data band signal m and data signals X ₁ and X ₂ is as shown in Table 1 below.

[Table] T _-1 , T ₀ and T ₁ in Fig. 3b represent the optimum sampling points between the three time slits, and now the signals m ₁ to _{m 4} are the sampling points.
When sampled at T _-1 to _{T 1} , the baseband signal position (A _-1 , a _-1 , B ₀ , b ₀ , C ₁ , c ₁ )
The data signal X ₂ , which is used to determine _the It will look like a table.

[Table] From Table 2 above, for data signal X ₂ ,
In the case of the baseband signal waveform m ₁ to _{m 2} , that is, the baseband signal in which the polarity of the differential coefficient at time T ₀ is positive, when the sampling point reaches +Δt, it is always “1”, and on the contrary, −Δt When it reaches , it always becomes "0". On the other hand, in the case of waveforms m ₃ to _{m 4} , that is, baseband signals in which the polarity of the differential coefficient at time T ₀ is negative, a data signal X ₂ of the opposite polarity to the waveforms m ₁ to m ₂ is obtained. Therefore, by inverting the polarity of the data signal X ₂ , the same data signal as in the case of waveforms m ₃ to _{m 4} can be obtained. Therefore, if we determine the polarity of the differential coefficient of the baseband signal at time T ₀ as described above, and perform a predetermined logical operation on the data signal X ₂ with reference to the determination result, the output signal will be , it is clear that it can serve as an error signal for detecting the deviation of the sampling point. Next, the operation of the first embodiment of the present invention shown in FIG. 2 will be described. In the figure, the band-limited baseband signal output from the first phase detector 16 is input to a 2-bit A/D converter 19 and sampled by a timing signal sent via a variable phase shifter 25. It is shaped and output as data signals _X1 and _X2 . The operation of the 2-bit A/D converter 19 is as already explained with reference to FIGS. 3a and 3b and Table _{1 .}
and l ₃ , the baseband signal m is identified and converted into data signals X ₁ and X ₂ . The data signal X ₁ is output as a predetermined data signal and is simultaneously input to the polarity determination circuit 22 . The polarity determination circuit 22 has a function of determining the waveforms m ₁ to _{m 4} of the band-limited baseband signal, and the output signal G is “1” in the case of the waveforms m ₁ to _{m 2} . And the signal has the waveform m ₃ ~
In the case of m ₄ , it becomes "1". The logic circuit 23 has two
The polarity of the data signal X ₂ input from the bit A/D converter 19 is inverted when the signal is "1", and when both the signals G and are "0", the waveforms m ₁ to _{m 4 are} With any of the waveforms,
It is equipped with a circuit that holds the nearest past data _signal It will be done. By supplying this error signal to the variable phase shifter 25 via the low-pass filter 24 as a phase control signal of the timing signal synchronization circuit,
A timing synchronization system is formed in which the phase of a predetermined timing signal output from the fixed frequency oscillator 26 is automatically controlled and adjusted.
Timing signals are always supplied to D converters 19 and 20 at optimal timing. In addition, what is shown in FIG. 4 is the polarity discrimination circuit 2.
2 and logic circuit 23, the former is D
type flip-flops 28-30 and an amplitude comparator 31, the latter comprising D-type flip-flops 32, 33, 40, an OR/NOR gate 34, AND gates 35, 36, 39, an OR gate 37, It is equipped with 38. In the figure, in the polarity determination circuit 22, D type flip-flops 28, 29, and 30 operate as 3-bit memories in response to the input of the data signal _X1 and the timing signal T. The outputs y ₁ and y ₋₁ of 30 are input to an amplitude comparator 31 . The amplitude comparator 31 is
The 2-bit A/D converter 19 has a function of determining the polarity of the differential coefficient of the baseband signal at the sampling point _T0 , and the polarity of the differential coefficient is determined by comparing data at the sampling points T _-1 and _T1 . I am making a judgment. i.e. data output y _-1
and y ₁ , when changing from “0” to “1”, the polarity of the differential coefficient is positive, and the polarity changes from “1” to “0”.
When changing to , the polarity of the differential coefficient is negative. The amplitude comparator 31 outputs signals G and G for determining polarity, but the waveform of the baseband signal is
When m ₁ ~ m ₂ , G becomes "1", and when m ₃ ~
When m ₄ , becomes "1". On the _other hand, the data signal
It is input to AND gates 35 and 36. AND
The gate circuit formed by the gates 35 and 36 and the OR circuit 38 outputs the data signal X 2 as it is when the signal G is "1", and outputs the data signal X ₂ as it is when the signal G is " ₁ ". It operates to invert and output. Also, AND gate 39
operates to output the timing signal T when either signal G and is "1", and to output 0 when both signals G and are "0". Therefore, D type flip-flop 4
The waveform of the baseband signal is m ₁ ~
When the state is m ₄ , the output of the OR gate 38 is output as is, and when the waveform is not in the state m ₁ to m ₄ , the closest past m ₁ to m ₄ from the current time is output.
It operates to hold the data signal _X2 at any time of the waveform. Next, the operation of the second embodiment of the present invention will be explained. FIG. 5 is a block diagram showing the main part of the second embodiment, which is an example of application of the present invention to a demodulator using a four-phase phase modulation method. In the figure, this embodiment includes a first phase detector 41, a second phase detector 42, a π/2 phase shifter 43, and a 2-bit A/2 phase shifter 43.
D converters 44 and 45, carrier regeneration circuit 46, polarity discrimination circuits 47 and 48, logic circuits 49 and 50, countable circuit 51, and low-pass filter 5
2. Variable phase shifter 53 and fixed frequency oscillator 54
A timing synchronization circuit 55 is provided. In FIG. 5, first and second phase detectors 41 and 42, a π/2 phase shifter 43, and a 2-bit A/D correspond to the input of the four-phase phase modulation signal S.
Converters 44 and 45, carrier regeneration circuit 46
Since the operations are explained in the description of the conventional example, their explanation will be omitted. This means that
The same applies to the description of each embodiment below. The second embodiment has two systems for phase control signal detection, including a phase control signal detection system consisting of a polarity discrimination circuit 47 and a logic circuit 49, and a phase control signal detection system consisting of a polarity discrimination circuit 48 and a logic circuit 50. system is provided in the timing synchronization circuit 55, and
The original timing signal output from the fixed frequency oscillator 54 is automatically phase-adjusted via the variable phase shifter 53, and is shared as one timing signal for both the 2-bit A/D converters 44 and 45. This corresponds to the case where it is supplied. Binary baseband signals output from the first and second phase detectors 41 and 42, respectively, are input to 2-bit A/D converters 44 and 45, and sent via a variable phase shifter 53. They are digitized through sampling shaping by a common timing signal and output as digital signals X ₁ , X ₂ , Y ₁ , and Y ₂ . Data signals X ₁ and Y ₁ are sent to polarity discrimination circuits 47 and 48, respectively, for polarity discrimination, and data signals X ₂ and Y ₂ are sent to logic circuits 49 and 50, respectively, for position discrimination. The operations for detecting and outputting the phase control signal in the phase control signal detection system consisting of the polarity discrimination circuit 47 and logic circuit 49 and the phase control signal detection system consisting of the polarity discrimination circuit 48 and logic circuit 50 have been described above. This is similar to the case of the first embodiment. The phase control signals output from the logic circuits 49 and 50 are added in an adder circuit 51, and inputted to a variable phase shifter 53 via a low-pass filter 52, and then added to a timing signal sent from a fixed frequency oscillator 54. control and adjust the phase of As a result, the timing signal output from the variable phase shifter 53 is transmitted to the 2-bit A/D converters 44 and 4.
5, it is always supplied at the optimal timing. Next, the operation of the third embodiment of the present invention will be explained. FIG. 6 is a block diagram showing the main part of the third embodiment, which is an example of application of the present invention to a demodulator using a four-phase phase modulation method. In the figure, this embodiment uses a first phase detector 56, a second phase detector 57, and a π/2 phase shifter 58 as a 2-bit A/2 phase shifter 58.
A timing circuit consisting of D converters 59 and 60, carrier regeneration circuit 61, polarity discrimination circuits 62 and 63, logic circuits 64 and 65, low-pass filters 66 and 67, variable phase shifters 68 and 70, and fixed frequency oscillator 69. synchronous circuit 71. The third embodiment has two systems for phase control signal detection, including a phase control signal detection system consisting of a polarity discrimination circuit 62 and a logic circuit 64, and a phase control signal detection system consisting of a polarity discrimination circuit 63 and a logic circuit 65. system is provided in the timing synchronization circuit 71, and
The original timing signal output from the fixed frequency oscillator 69 is automatically phase-adjusted via two variable phase shifters 68 and 70, and is output as two timing signals to the 2-bit A/D converters 59 and 60. This corresponds to the case where each is supplied independently. The basic operation of the timing synchronization circuit 71 is the same as in the first embodiment described above. Next, the operation of the fourth embodiment of the present invention will be explained. FIG. 7 is a block diagram showing the main part of the fourth embodiment, which is an example of application of the present invention to a demodulator using the 16-value orthogonal amplitude modulation method. In the figure, this embodiment includes a first phase detector 72, a second phase detector 73, a π/2 phase shifter 74, 3-bit A/D converters 75 and 76, and a carrier regeneration circuit 77. and a polarity determination circuit 78, a logic circuit 79,
It includes a timing synchronization circuit 83 consisting of a low-pass filter 80, a variable phase shifter 81, and a fixed frequency oscillator 82. In the fourth embodiment, a pair of 3-bit A/D converters 75 and 76 are provided as A/D converters in response to the input of the 16-value orthogonal amplitude modulation signal S, and As a polarity determination signal, a 3-bit A/D converter 7
The data signals X ₁ and X ₂ output from the 3-bit A/D converter are referenced, and the data signals X 1 and X 2 output from the 3-bit A/D converter are used for determining the position of the baseband signal.
Of the series of data signals, data signal X ₃ is input to logic circuit 79 . first and second phase detectors 72 and 73;
π/2 phase shifter 74 and carrier recovery circuit 77
The operations, etc., are the same as in each of the above-described embodiments, and a description thereof will be omitted. One embodiment of the polarity determining circuit 78 in FIG. 7 is shown in FIG. As shown in FIG. 10, the polarity discrimination circuit 7
8 is a D type flip-flop 108-11
3 and an amplitude comparator 114. Data signal input to polarity determination circuit 78
Corresponding to X ₁ and X ₂ and the timing signal T,
D-type flip-flops 108 and 111
The data y ₁ at the sampling point T ₁ of the data signals X ₁ and _{X 2} is obtained at the output of the D-type flip-flops ₁₁₀ and 113.
Data y _-1 at time T _-1 is obtained. These data y ₁ and y _-1 are input to the amplitude comparison 114,
These levels are subjected to logical operation processing to determine the polarity of the differential series of the 4-value baseband signal input to the 3-bit A/D converter 75. Now T _-1
If the 4-value signal at time is E _-1 and the 4-value signal at time T ₁ is E ₁ , then in the amplitude comparator 114, E ₁ -E _-1 =
When M is calculated and M is positive, that is, the differential coefficient at time T ₀ is positive, the signal G is output as "1", and when M is negative, that is, the differential coefficient at time T ₀ is negative, the signal G is output as "1". 1” is output.
Note that E _-1 and E ₁ above are D type flip-flops 108, 110, 111 and 113.
As described above, it is obtained as part of the logical operation processing in the amplitude comparator 114. As mentioned above, the polarity determination circuit 78 outputs the signal G.
and are outputted and input to the logic circuit 79, but the operation of the logic circuit 79 is the same as in each of the above-described embodiments, and the phase control signal is passed through the low-pass filter 80 to the variable phase input to the device 81,
The phase of the original timing signal output from the fixed frequency oscillator 82 is adjusted and supplied to the 3-bit A/D converters 75 and 76 as a common timing signal. Next, a fifth example will be described. FIG. 8 is a block diagram showing the main part of the fifth embodiment, which is an example of application of the present invention to a demodulator using the 16-value orthogonal amplitude modulation method. In the figure, this embodiment includes a first phase detector 84, a second phase detector 85, a π/2 phase shifter 86, 3-bit A/D converters 87 and 88, and a carrier regeneration circuit 89. and a polarity determination circuit 90, a logic circuit 91,
The timing synchronization circuit 95 includes a low-pass filter 92, a variable phase shifter 93, and a fixed frequency oscillator 94. The difference between the fifth embodiment and the fourth embodiment described above is that only the data signal _X1 is input to the polarity discrimination circuit 90 for polarity discrimination, and the data signal _X2 is not required. There is no such thing. An example of the polarity determination circuit 90 in this case is as follows:
This circuit is similar to the polarity determining circuit 22 shown in _FIG . The phase control signal output from the logic circuit 91 is input to the variable phase shifter 93 via the low-pass filter 92, and the phase of the timing original signal output from the fixed frequency oscillator 94 is controlled and adjusted to a predetermined value. The operation of commonly supplying the timing signal to 3-bit A/D converters 87 and 88 is the same as in the fourth embodiment described above. Note that, as is clear from the comparison between the fourth and fifth embodiments described above, in the fourth embodiment, three series of data signals X ₁ and X ₂ output from the 3-bit A/D converter 75 , and _X3 , two series of data signals _X1 and _X2 are referred to the polarity discrimination circuit 78 for polarity discrimination, and in the fifth embodiment, the 3-bit A/
Of the three series of data signals X ₁ , X ₂ and X ₃ output from the D converter 87, only one series of data signal X ₁ is sent to the polarity discrimination circuit 9 for polarity discrimination.
0. Next, a sixth example will be described. FIG. 9 is a block diagram showing the main part of the sixth embodiment, which is an example of application of the present invention to a demodulator using the 64-value orthogonal amplitude modulation method. In the figure, this embodiment includes a first phase detector 96, a second phase detector 97, a π/2 phase shifter 98, 4-bit A/D converters 99 and 100, and a carrier recovery circuit 101. and a timing synchronization circuit 107 consisting of a polarity discrimination circuit 102, a logic circuit 103, a low-pass filter 104, a variable phase shifter 105, and a fixed frequency oscillator 106. The difference between the sixth embodiment and the fifth embodiment described above is that the A/D converter is a pair of 4-bit A/D converters 99 corresponding to the 64-value amplitude modulation method.
and 100,
As a reference signal for polarity discrimination to the polarity discrimination circuit 102, only the data signal _X1 outputted from the 4-bit A/D converter 99 is used, as in the case of the fifth embodiment. In the above description, examples of application of the present invention to demodulation devices using a 4-phase phase modulation method, a 16-value quadrature amplitude modulation method, a 64-value quadrature amplitude modulation method, etc. are described as embodiments of the present invention.
The scope of application of the present invention is not limited to the above-mentioned polyphase phase modulation method and multi-value quadrature amplitude modulation method, but N=2, 4, 8, 16, ..., and
As defined ^by L ² = 2, 3, 4,... Needless to say, it can be effectively applied. (Effects of the Invention) As explained in detail above, the present invention provides an A/D
By applying a timing synchronization circuit having a timing synchronization system formed by referring to a specific data signal among the data signals output from the converter, the phase with respect to the timing signal supplied to the A/D converter can be adjusted. There is an advantage that no adjustment is required at all, and the demodulated baseband signal can always be sampled and shaped at the optimum timing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of a conventional demodulator, and FIGS. 2, 5, 6, 7, 8, and 9 show the first, second, Third,
A block diagram showing the main parts of the fourth, fifth, and sixth embodiments. Fig. 3 is an explanatory diagram of the operation of the timing synchronization system. Fig. 4 shows the main parts of the embodiment of the polarity discrimination circuit and logic circuit. FIG. 10 is a block diagram showing the main parts of another embodiment of the polarity discrimination circuit. In the figure, 1, 16, 41, 56, 72, 8
4,96...first phase detector, 2,17,4
2, 57, 73, 85, 97... second phase detector, 3, 18, 43, 58, 74, 86, 98...
...π/2 phase shifter, 4, 5, 19, 20, 4
4, 45, 59, 60...2-bit A/D converter, 6, 21, 46, 61, 77, 89, 10
1... Carrier regeneration circuit, 7, 8... Full wave rectifier circuit, 9, 10... Phase adjustment circuit, 11... Phase comparator, 12, 24, 52, 66, 67, 80, 9
2,104...Low pass filter, 13...Voltage controlled oscillator, 14,15,27,55,71,83,9
5,107...timing synchronization circuit, 22,4
7, 48, 62, 63, 78, 90, 102...
Polarity discrimination circuit, 23, 49, 50, 64, 65,
79, 91, 103...logic circuit, 25, 53,
68, 70, 81, 93, 105... variable phase shifter, 26, 54, 69, 82, 94, 106...
Fixed frequency oscillator, 28-30, 32, 33, 4
0,108-113...D-type flip-flop, 31,114...Amplitude comparator, 34...
OR/NOR……Gate, 35, 36, 39…
AND gate, 37, 38...OR gate, 51...
...addition circuit.

Claims (1)

[Claims] Predetermined band limitation by 1 N (N=2, 4, 8, 16, ...) phase modulation method or L ² (L = 2, 3, 4, ...) value quadrature amplitude modulation method Input the digital carrier modulation signals that have been
a pair of first and second phase detectors that perform synchronous detection via carrier recovery signals having a phase difference of 2 radians to generate a predetermined pair of demodulated baseband signals; and a band of the pair of demodulated baseband signals. A pair of k-bit A/D converters that input a limited signal, convert it into digital data through a sampling shaping action using a predetermined timing signal, and output each as a predetermined k (integer greater than or equal to 1) series data signal. , inputting at least two or more specific data signals of the pair of k-sequence data signals output from the pair of A/D converters to generate a carrier wave corresponding to the carrier signal of the digital carrier modulation signal. a carrier regeneration circuit that generates a reproduced signal and outputs it for synchronous detection to the pair of phase detectors; A π/2 phase shifter that provides a phase difference of π/2 radians to each other to supply for synchronous detection, and a fixed frequency oscillator that forms an oscillation source of the timing signal as means for generating the timing signal. at least one variable phase shifter that automatically controls and adjusts the phase of the output signal of the A/D via at least one system of predetermined phase control signals;
A data signal for specific polarity determination among a pair of k-series data signals output from the converter is input, and the differential coefficient of the band-limited baseband signal at the sampling point of the A/D converter is calculated. A polarity discrimination circuit for discriminating polarity and a phase control signal detection system of a timing synchronization system are formed together with the polarity discrimination circuit, and the pair of A/ A logic circuit that generates and outputs the phase control signal by performing a predetermined logical operation on a predetermined baseband signal position determination data signal among the k-series data signals output from the D converter. A demodulation device comprising: and a predetermined timing synchronization circuit formed by. 2. The timing synchronization circuit is provided with one system of phase control signal detection system consisting of the polarity discrimination circuit and a logic circuit, and corresponding to this one system of phase control signal detection system, the band-limited base A specific (k-
1) Either one of the series or one specific series of data signals is referenced, and one system of timing signals generated corresponding to the one system of phase control signal detection system is transmitted to the pair of A/D converters. A demodulator according to claim 1, which is commonly supplied to the demodulator. 3. The timing synchronization circuit is provided with two phase control signal detection systems consisting of the polarity discrimination circuit and a logic circuit, and the band-limited base is output from each of the pair of A/D converters for determining the polarity of the differential coefficient of the band signal;
Either the specific (k-1) series or one specific series of data signals is referred to, and one system of timing signals generated corresponding to the two systems of phase control signal detection systems is The demodulator according to claim 1, which is commonly supplied to the pair of A/D converters. 4. The timing synchronization circuit is equipped with two phase control signal detection systems consisting of the polarity discrimination circuit and a logic circuit, and the band-limited base is For determining the polarity of the differential coefficient of the band signal, either a specific (k-1) series or a specific 1 series of data signals output from the pair of A/D converters is referred to, and , the demodulation device according to claim 1, wherein two systems of timing signals generated corresponding to the two systems of phase control signal detection systems are independently supplied to corresponding A/D converters. .