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JPH0230572B2 - - Google Patents
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JPH0230572B2 - - Google Patents

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Publication number
JPH0230572B2
JPH0230572B2 JP58052529A JP5252983A JPH0230572B2 JP H0230572 B2 JPH0230572 B2 JP H0230572B2 JP 58052529 A JP58052529 A JP 58052529A JP 5252983 A JP5252983 A JP 5252983A JP H0230572 B2 JPH0230572 B2 JP H0230572B2
Authority
JP
Japan
Prior art keywords
sio
resin
layer
film
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58052529A
Other languages
Japanese (ja)
Other versions
JPS59178749A (en
Inventor
Shiro Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5252983A priority Critical patent/JPS59178749A/en
Publication of JPS59178749A publication Critical patent/JPS59178749A/en
Publication of JPH0230572B2 publication Critical patent/JPH0230572B2/ja
Granted legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 (1) 発明の技術分野 本発明は多層構造体に係り、特に例えば半導体
装置、バブルメモリ装置などの微細パターンを有
する電子デバイスに関する。
DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a multilayer structure, and particularly to electronic devices having fine patterns, such as semiconductor devices and bubble memory devices.

(2) 技術の背景 電子回路の機能が増大しそれに用いられる電子
部品も次第に個別部品からIC及びLSIへと集積度
が増大するにつれて素子間の配線が複雑になり多
くの交差を必要とするようになつてきた。これに
より多層配線が必要になつた。我々は先に基板上
に一般式(H2-aRaSiO)o〔RはH3SiO,
H2CH3SiO,H(CH32SiOもしくは(CH33SiO
であり、aは0もしくは1で、分子中の平均値は
0と1の範囲にある。〕で表わされる樹脂を塗布
し、熱分解して酸化珪素膜を形成させる方法に関
する特許を出願しているが、本発明はこの樹脂を
配線構造体の絶縁層に適用したものである。
(2) Background of technology As the functions of electronic circuits increase and the degree of integration of the electronic components used in them increases, from individual components to ICs and LSIs, wiring between elements becomes complex and requires many intersections. I'm getting used to it. This necessitated multilayer wiring. We first applied the general formula (H 2-a RaSiO) o [R is H 3 SiO,
H 2 CH 3 SiO, H(CH 3 ) 2 SiO or (CH 3 ) 3 SiO
and a is 0 or 1, and the average value in the molecule is in the range of 0 and 1. A patent application has been filed for a method of coating a resin represented by the following formula and thermally decomposing it to form a silicon oxide film, and the present invention applies this resin to an insulating layer of a wiring structure.

(3) 従来技術と問題点 従来、LSI、ジヨセフソン素子J.J及びバブルメ
モリーなど微細パターンを有するデバイスの層間
絶縁はシリコン基板の熱酸化による酸化珪素
(SiO2)膜、シラン系ガスを用いた気相成長によ
るSiO2系絶縁材料、あるいはポリイミド、シリ
コーン樹脂などの有機系絶縁材料などを用いて行
なわれているが、微細化、信頼性などに一長一短
がある。即ち層間絶縁において平担化機能、空気
中400〜1000℃に耐える耐熱性、及び例えば密着
性、耐電食性、厚膜形成性などの信頼性のすべて
を満足する材料が存在しないのが現状である。
(3) Conventional technology and problems Conventionally, interlayer insulation for devices with fine patterns such as LSIs, Josephson devices JJ, and bubble memories has been achieved using silicon oxide (SiO 2 ) films created by thermal oxidation of silicon substrates, or vapor phase insulation using silane-based gases. This is done using grown SiO 2 -based insulating materials or organic insulating materials such as polyimide and silicone resin, but these have advantages and disadvantages in terms of miniaturization and reliability. In other words, the current situation is that there is no material that satisfies all of the requirements for interlayer insulation, such as flattening function, heat resistance that can withstand temperatures of 400 to 1000 degrees Celsius in air, and reliability such as adhesion, electrolytic corrosion resistance, and ability to form thick films. .

今、平担化機能及び耐熱性という点で優れてい
るシリコーン樹脂の塗布及び熱処理によるSiOx
膜形成に着目すると、ポリジアルコキシシラン
RO〔―(RO)2SiO〕―oR〔式中、Rは一価の炭化水
素、例えばCH3,C2H5又は水素であり、ORの少
なくとも1/3はアルコキシ基である。〕を熱分解し
てSiO2にする方法が知られている。分子中にア
ルコキシ基を残す理由はすべてをOHにすると保
存安定性が非常に悪くなるからである。このポリ
ジアルコキシシランを塗布後熱分解するとアルコ
キシ基が飛散する際に塗膜に歪とピンホールを残
すので、材料の種類によるけれども、0.2〜0.5μ
m以上の膜厚に塗布した場合は塗膜にクラツクが
入り、それ以下の膜厚に塗布した場合は電食不良
の原因になる。従つて熱分解時に飛散する原子又
は原子団が極めて小さく、少ないシリコーン樹脂
が存在すれば、平担化機能、耐熱性に加えて前記
信頼性も優れた絶縁膜を形成することができるは
ずである。
Currently, SiOx is produced by applying and heat-treating silicone resin, which has excellent flattening function and heat resistance.
Focusing on film formation, polydialkoxysilane
RO [-(RO) 2 SiO]- o R [wherein R is a monovalent hydrocarbon, such as CH 3 , C 2 H 5 or hydrogen, and at least 1/3 of OR is an alkoxy group. ] is known to be thermally decomposed into SiO 2 . The reason why alkoxy groups are left in the molecule is that if all of them are OH, the storage stability will be very poor. If this polydialkoxysilane is thermally decomposed after coating, the alkoxy groups will scatter and leave distortion and pinholes in the coating film, so depending on the type of material, the amount of 0.2 to 0.5μ
If it is applied to a thickness of more than m, cracks will appear in the coating, and if it is applied to a thickness less than that, it will cause electrolytic corrosion defects. Therefore, if a silicone resin exists with very few atoms or atomic groups scattered during thermal decomposition, it should be possible to form an insulating film with excellent flattening function, heat resistance, and reliability as described above. .

(4) 発明の目的 本発明の目的は多層配線構造体において、平担
化機能、耐熱性に加えて信頼性のある優れた絶縁
膜を提供することである。
(4) Object of the invention The object of the invention is to provide an excellent insulating film that has a flattening function, heat resistance, and reliability in a multilayer wiring structure.

(5) 発明の構成 本発明は一般式: R2O(―R1 2SiO)―oR 〔式中、R1は全部がHであるか又は少なくとも
半数がHであり、かつ残りが−OSiH3,−
OSiH2CH3,−OSiH(CH3)、もしくは−OSi
(CH33であり;R2は−SiH3,−SiH2CH3,−SiH
(CH32もしくは−Si(CH33であり;nは1〜
100の整数である。〕 で表わされるシリコーン樹脂を、必要に応じて溶
剤を用いて、塗布し次いで加熱することによつ
て、前記良好な平担化機能、耐熱性、信頼性を有
する酸化珪素膜が形成されることを利用して、前
記膜を配線構造体における絶縁層として適用する
ようにしたものである。
(5) Structure of the Invention The present invention is based on the general formula: R 2 O (-R 1 2 SiO) - o R [wherein R 1 is entirely H or at least half is H, and the remainder is - OSiH 3 ,−
OSiH 2 CH 3 , −OSiH(CH 3 ), or −OSi
( CH3 ) 3 ; R2 is -SiH3 , -SiH2CH3 , -SiH
(CH 3 ) 2 or -Si(CH 3 ) 3 ; n is 1 to
It is an integer of 100. ] A silicon oxide film having the above-mentioned good flattening function, heat resistance, and reliability can be formed by applying a silicone resin represented by the formula, using a solvent if necessary, and then heating it. By utilizing this, the film is applied as an insulating layer in a wiring structure.

即ち本発明は基板上に絶縁層及び導電性配線を
一層もしくはそれ以上に構成した配線構造体にお
いて、前記絶縁層の全部もしくは一部が一般式: (H2-aRaSiO)o 〔式中、RはH3SiO,H2CH3SiO,H(CH32SiO
もしくは(CH33SiOであり、aは0もしくは1
で、分子中の平均値は0と1の範囲にある。〕 で表わされるポリシロキサンの末端をH3SiO,
H2CH3SiO,H(CH32SiOもしくは(CH33SiO
で封鎖してあるシリコーン樹脂を塗布し、300〜
500℃で熱処理してSiOx化した層で形成されてい
ることを特徴とする配線構造体を提供する。
That is, the present invention provides a wiring structure in which an insulating layer and conductive wiring are formed in one or more layers on a substrate, in which all or part of the insulating layer has the general formula: (H 2-a RaSiO) o [wherein, R is H 3 SiO, H 2 CH 3 SiO, H(CH 3 ) 2 SiO
or (CH 3 ) 3 SiO, where a is 0 or 1
The average value in the molecule is in the range of 0 and 1. ] H 3 SiO,
H 2 CH 3 SiO, H(CH 3 ) 2 SiO or (CH 3 ) 3 SiO
Apply silicone resin sealed with 300~
Provided is a wiring structure characterized in that it is formed of a layer heat-treated at 500°C to form SiOx.

本発明の基本的な原理は式H3SiO(―H2SiO)―o
SiH3からなるシリコーン樹脂を用いてSiOxを形
成すれば、熱分解時にHは容易に分解されるので
SiOx膜中の不純物量は少なく、Hは体積が小さ
いのでH飛散後の体積収縮歪は小さく、ピンホー
ルも微細であり、かつSiOの酸化による体積増加
が歪を緩和し、ピンホールを埋めるので、最終的
に歪が小さくかつ緻密で純粋なSiOx(x=1〜
2)膜を有する配線構造体が得られるということ
にある。前記のようにHO(―H2SiO)―oHは不安定
であるが、末端をシリル化すると安定であり、こ
れによつて本発明によつて得られる装置は実際的
なものになつた。そしてこの基本原理の利点は分
子中にSi,O,Hの他に多少のCH3が含まれても
失なわれることはない。但し本発明に用いる前記
シリコーン樹脂の分子中のR1は実質的に全部が
Hであることが好ましく、H以外の置換基の割合
は通常10%程度まで、多くても50%未満であるべ
きである。
The basic principle of the invention is the formula H 3 SiO(-H 2 SiO)- o
If SiOx is formed using silicone resin consisting of SiH3 , H will be easily decomposed during thermal decomposition.
Since the amount of impurities in the SiOx film is small and the volume of H is small, the volume shrinkage strain after H scattering is small, and the pinholes are also minute, and the increase in volume due to SiO oxidation alleviates the strain and fills the pinhole. , the final result is small strain, dense, and pure SiOx (x=1~
2) A wiring structure having a film can be obtained. As mentioned above, HO(-H 2 SiO) -o H is unstable, but it becomes stable when the terminal is silylated, and this makes the device obtained by the present invention practical. . The advantage of this basic principle is not lost even if some CH 3 is included in the molecule in addition to Si, O, and H. However, it is preferable that substantially all of R 1 in the molecule of the silicone resin used in the present invention is H, and the proportion of substituents other than H should normally be about 10%, and at most less than 50%. It is.

本発明で用いるシリコーン樹脂R2O(―R1 2SiO)―
R2は比重1.6〜1.7であり、常温でn<3の場合
は液体であり、n≧3の場合は粉末であり、液体
の場合はそのまま塗布可能であるが、粉末の場合
又は例えば回転塗布(スピンコート)で基板に塗
布する場合などはトルエンなどの有機溶剤に溶解
してから塗布する。回転塗布の場合の膜厚調整は
分子量、溶剤の種類、樹脂濃度、回転数によつて
行なうことができる。適当な膜厚は0.5μ〜1.5μの
範囲にあり、それより大きい場合は耐クラツク性
を低下させ、それより小さい場合は絶縁効果を低
下させるが他の絶縁材料と組合せることで使用可
能である。
Silicone resin R 2 O (-R 1 2 SiO) used in the present invention
o R 2 has a specific gravity of 1.6 to 1.7, and at room temperature, if n<3, it is a liquid; if n≧3, it is a powder; if it is a liquid, it can be applied as it is, but if it is a powder, it can be applied by rotating, for example. When applying to a substrate by coating (spin coating), it is applied after being dissolved in an organic solvent such as toluene. In the case of spin coating, the film thickness can be adjusted by adjusting the molecular weight, type of solvent, resin concentration, and rotation speed. The appropriate film thickness is in the range of 0.5μ to 1.5μ; if it is larger than that, it will reduce the crack resistance, and if it is smaller than that, it will reduce the insulation effect, but it can be used in combination with other insulating materials. be.

シリコーン樹脂R2O(―R1 2SiO)―oR2は回転塗布、
スプレーなどの方法によるコーテイングが可能で
あるので、凹凸のある基板に塗布し、その表面を
平担化する機能を持つている。従つて微細配線を
設けた半導体装置あるいはバブルメモリなどの配
線層間絶縁材料として、60〜300℃で予熱、そし
て300〜500℃で熱処理してSiOx化して用いるの
に好適である。尚末端にCH3基をもつものは400
℃以下あるいは場合によつて470℃以下では完全
なSiOxには変化しないのであるが、層間絶縁に
用いる場合には完全を期さなくても使用できる。
Si―CH3結合の熱分解は300〜350℃以上で起きる
が、例えば赤外吸収測定でCH3基あるいはSi―C
結合の含有量を追跡することによつて反応を確認
できる。塗布と熱処理によるSiOx化を繰り返す
ことによつて厚膜を得たり、深い穴や溝を埋める
ようにすれば平担化機能が強調され、かつ緻密な
膜を得ることができる。
Silicone resin R 2 O (-R 1 2 SiO) - o R 2 is spin coating,
Since it can be coated by spraying or other methods, it has the ability to apply to uneven substrates and flatten the surface. Therefore, it is suitable for use as an interlayer insulating material for wiring in semiconductor devices with fine wiring or bubble memories, etc. by preheating at 60 to 300°C and heat treating at 300 to 500°C to form SiOx. Furthermore, those with CH 3 group at the end are 400
Although it does not change to complete SiOx at temperatures below ℃ or, in some cases, below 470 ℃, it can be used without requiring perfection when used for interlayer insulation.
Thermal decomposition of Si--CH 3 bonds occurs at temperatures above 300-350°C, but for example, infrared absorption measurements show that CH 3 groups or Si--C
Reactions can be confirmed by tracking the content of bonds. By repeating coating and heat treatment to form SiOx, a thick film can be obtained, and by filling deep holes and grooves, the flattening function is emphasized and a dense film can be obtained.

本発明において体積収縮による膜厚の減少は通
常の50%程度に対してわずか3〜10%の減少であ
り、ほとんど収縮は見られない。
In the present invention, the reduction in film thickness due to volumetric shrinkage is only 3 to 10% compared to the usual 50%, and almost no shrinkage is observed.

本発明の多層配線構造体における絶縁樹脂硬化
層は気相成長法によるSiO2などと組合せられた
層であつてもよい。
The insulating resin cured layer in the multilayer wiring structure of the present invention may be a layer combined with SiO 2 or the like by vapor phase growth.

(6) 発明の実施例 (1) 樹脂の調製 ジエトキシシランをメチルイソブチルケトン
(MIBK)に溶かし水を加えてシラノール化し、
35℃で20時間縮合重合させた後、ジメチルクロル
シランを加えて得た粉末状のポリシロキサン
(CH32HSiO(―H2SiO)―oSiH(CH32、〔nの平均
値は8であつた。〕を樹脂―とする。
(6) Examples of the invention (1) Preparation of resin Diethoxysilane was dissolved in methyl isobutyl ketone (MIBK) and water was added to convert it into silanol.
Powdered polysiloxane (CH 3 ) 2 HSiO (-H 2 SiO) - o SiH (CH 3 ) 2 obtained by adding dimethylchlorosilane after condensation polymerization at 35°C for 20 hours, [average value of n was 8. ] is a resin.

水を2%含むMIBK中にジクロルシランガスを
導入しさらにクロルシランでシリル化して得た粉
末状のポリシロキサンH3SiO(―H2SiO)―oSiH3〔n
の平均値は19であつた〕を樹脂とする。
Powdered polysiloxane H 3 SiO (-H 2 SiO) - o SiH 3 [n
The average value was 19] is used as a resin.

樹脂―、樹脂―をトルエンに溶解した液を
それぞれ樹脂液―、樹脂液―とする。
The liquids obtained by dissolving resin and resin in toluene are referred to as resin liquid and resin liquid, respectively.

(2) 実施例 1 前記のようにして25重量%の樹脂液を作成し
た。次にシリコン基板内にバイポーラ素子を形成
し、その上に1層目のアルミニウム配線を行なつ
た。前記アルミニウム配線の厚さは0.9μm、最小
線幅は3μm、最小線間隔は2μmである。前記樹
脂液を6000rpm、20秒の条件で回転塗布し、80
℃、30分の溶剤乾燥及び450℃,60分の熱処理を
行なつた。同一条件で平板上に塗布して得られる
膜厚は0.8μmであつたが、前記アルミニウム配線
上では0.4μm、スペース部では1.1μmであり、段
差は0.2μmであつた。次に1.0μmのPSGを公知の
方法で形成し、スルーホールの形成、2層目のア
ルミニウム配線の形成、さらに保護層として1.3μ
mのPSG層を形成し、電極取出し用窓あけを行
なつてバイポーラ素子装置を得た。この装置は空
気中500℃、1時間の加熱試験、−65℃←→150℃の
10回の熱衝撃試験、85℃,90%RH下での6V印
加、1000時間の試験及びこれらの試験を組合せた
試験後においても異常及び不良は見られなかつ
た。
(2) Example 1 A 25% by weight resin liquid was prepared as described above. Next, a bipolar element was formed in the silicon substrate, and a first layer of aluminum wiring was formed thereon. The aluminum wiring has a thickness of 0.9 μm, a minimum line width of 3 μm, and a minimum line spacing of 2 μm. The resin solution was spin-coated at 6000 rpm for 20 seconds, and
Solvent drying was carried out at 450°C for 30 minutes and heat treatment was carried out at 450°C for 60 minutes. The film thickness obtained by coating on a flat plate under the same conditions was 0.8 μm, but it was 0.4 μm on the aluminum wiring, 1.1 μm in the space, and the step difference was 0.2 μm. Next, 1.0 μm PSG is formed by a known method, through holes are formed, a second layer of aluminum wiring is formed, and a protective layer of 1.3 μm is formed.
A bipolar element device was obtained by forming a PSG layer of m and making a window for taking out the electrode. This device has a heating test of 500℃ in air for 1 hour, -65℃←→150℃
No abnormalities or defects were observed after 10 thermal shock tests, 6V application at 85°C and 90% RH, 1000 hours of testing, and a combination of these tests.

(3) 比較例 1 実施例1と同様に、但し前記樹脂液の代りに
ポリイミドを同一膜厚に塗布し、350℃、30分の
硬化を行なつて、バイポーラ素子装置を得ようと
したが、ポリイミド膜上にPSG膜を形成した段
階でPSG膜は剥離した。
(3) Comparative Example 1 An attempt was made to obtain a bipolar element device in the same manner as in Example 1, except that polyimide was applied to the same thickness instead of the resin liquid and cured at 350°C for 30 minutes. , the PSG film peeled off at the stage when it was formed on the polyimide film.

(4) 比較例 2 実施例1と同様に、但し層間絶縁層及び保護層
をポリイミドで形成してバイポーラ素子装置を得
た。これを窒素中500℃、1時間の耐熱試験をし
た所、ポリイミド層は茶褐色に変色した。さらに
85℃、90%RH下で6V印加試験を行なつた所、大
きなリーク電流が流れ、またポリイミド層が一部
剥離した。
(4) Comparative Example 2 A bipolar element device was obtained in the same manner as in Example 1, except that the interlayer insulating layer and the protective layer were formed of polyimide. When this was subjected to a heat resistance test in nitrogen at 500°C for 1 hour, the polyimide layer turned brown. moreover
When a 6V application test was conducted at 85°C and 90%RH, a large leakage current flowed and part of the polyimide layer peeled off.

(5) 比較例 3 実施例1と同様に、但し前記樹脂液の代りに
ラダー型のメチルポリシルセスキオキサンを塗布
し、窒素中450℃、1時間の硬化を行なつてバイ
ポーラ素子を得た。これを窒素中500℃、1時間
の耐熱試験及び、85℃、90%RH下での6V印加試
験をしたが、不良はなかつた。しかし空気中500
℃、1時間の耐熱試験をした所、電極窓あけ部の
一部にクラツクが発生した。
(5) Comparative Example 3 A bipolar element was obtained in the same manner as in Example 1, except that a ladder type methylpolysilsesquioxane was applied instead of the resin liquid and cured in nitrogen at 450°C for 1 hour. Ta. This was subjected to a heat resistance test in nitrogen at 500°C for 1 hour and a 6V application test at 85°C and 90% RH, but no defects were found. But 500 in the air
When a heat resistance test was conducted at ℃ for 1 hour, a crack occurred in a part of the electrode window opening.

(6) 実施例 2 実施例1と同様に、但し1層目のアルミニウム
配線上に18%の樹脂液を塗布し硬化した後、も
う一度樹脂液を塗布し硬化し、それからスルー
ホール形成後、2層目のアルミニウム配線を行な
つた。その上の保護層も樹脂液を用いて形成し、
電極取り出し窓を形成し、バイポーラ素子を得
た。この半導体装置を実施例1で述べた試験を行
なつたが異常及び不良は見られなかつた。
(6) Example 2 Same as Example 1, but after applying 18% resin liquid on the first layer of aluminum wiring and hardening, apply resin liquid again and harden, then after forming through holes, Layered aluminum wiring was performed. The protective layer on top is also formed using resin liquid,
An electrode extraction window was formed to obtain a bipolar device. This semiconductor device was subjected to the test described in Example 1, but no abnormalities or defects were found.

(7) 実施例 3 バブル発生のためのLPE(リキツドフエイズエ
ピタキシヤル)層の形成されたGGG(ガリウムガ
ドリニウムガーネツト)基板上に1000ÅのSiO2
層を形成した。その上に厚さ4000ÅのAl層から
なるコンダクタパターンを形成した。コンダクタ
パターンの線幅は1〜50μm、スペースは1〜
100μmであつた。
(7) Example 3 SiO 2 of 1000 Å was deposited on a GGG (gallium gadolinium garnet) substrate on which an LPE (liquid phase epitaxial) layer was formed for bubble generation.
formed a layer. A conductor pattern consisting of an Al layer with a thickness of 4000 Å was formed thereon. The line width of the conductor pattern is 1 to 50 μm, and the space is 1 to 50 μm.
It was 100 μm.

次に濃度15%の樹脂液―を用い、4000rpm、
30秒の条件で回転塗布し、60℃、30分間の溶剤乾
燥を行なつた。この段階では樹脂は溶剤に可溶で
ある。次いで空気中350℃、60分の硬化を行なつ
た。平坦基板に同一条件塗布したとき樹脂膜の厚
さは0.35μmであつた。さらに厚さ4000Åのパー
マロイパターンを形成し、その上に樹脂液―を
3000rpm、30秒の条件で回転塗布し、溶剤乾燥
後、窒素中300℃、180分の硬化を行なつた。平坦
基板上では厚さ0.4μmとなる。その上にスパツタ
によつて厚さ0.4μmのSiO2層を形成した。2層の
絶縁層の窓あけをCF4―O2(5%)の反応ガスを
用いたドライエツチングによつて行ないバブルメ
モリを得た。得られたバブルメモリを85℃、90%
RHの環境に置き、パーマロイパターンとコンダ
クタパターンの間に300Vの直流電圧を100時間印
加したが、絶縁不良は起きながつた。このバブル
メモリの正常の動作電圧は最大24Vであり、優れ
た信頼性があることがわかつた。
Next, using a resin liquid with a concentration of 15%, the speed was set at 4000 rpm.
Spin coating was performed for 30 seconds, and solvent drying was performed at 60°C for 30 minutes. At this stage the resin is soluble in the solvent. Then, curing was carried out in air at 350°C for 60 minutes. When applied to a flat substrate under the same conditions, the thickness of the resin film was 0.35 μm. Furthermore, a permalloy pattern with a thickness of 4000 Å is formed, and a resin liquid is applied on top of it.
Spin coating was performed at 3000 rpm for 30 seconds, and after drying the solvent, curing was performed at 300° C. for 180 minutes in nitrogen. The thickness is 0.4 μm on a flat substrate. A 0.4 μm thick SiO 2 layer was formed thereon by sputtering. A bubble memory was obtained by dry etching the two insulating layers using a reactive gas of CF 4 --O 2 (5%). Incubate the resulting bubble memory at 85℃, 90%
Although a DC voltage of 300V was applied between the permalloy pattern and the conductor pattern for 100 hours in a RH environment, insulation failures continued to occur. The normal operating voltage of this bubble memory is a maximum of 24V, and it was found to have excellent reliability.

(8) 比較例 4 実施例3と同様にして、但しコンダクタとパー
マロイの間の絶縁層としてポリジエトキシシロキ
サン溶液を塗布し、空気中350℃、60分処理して
厚さ3500Å(平坦基板上)のSiO2層を形成し、
パーマロイ層の上にはスパツタによる厚さ10000
ÅのSiO2層を形成した。このバブルメモリを実
施例3で行なつたのと同様の電食試験を行なつた
所、48時間で絶縁不良が発生した。
(8) Comparative Example 4 Same as Example 3, except that a polydiethoxysiloxane solution was applied as an insulating layer between the conductor and permalloy, and treated in air at 350°C for 60 minutes to a thickness of 3500 Å (on a flat substrate). form two layers of SiO,
The thickness of the permalloy layer is 10,000 mm due to spats.
Two layers of SiO were formed. When this bubble memory was subjected to the same electrolytic corrosion test as in Example 3, insulation failure occurred after 48 hours.

(7) 発明の効果 本発明によれば耐熱性、信頼性のあるコーテイ
ング樹脂を配線層間絶縁に用いることができるの
で高信頼性の多層構造体を得ることができる。
(7) Effects of the Invention According to the present invention, since a heat-resistant and reliable coating resin can be used for insulation between wiring layers, a highly reliable multilayer structure can be obtained.

Claims (1)

【特許請求の範囲】 1 基板上に絶縁層及び導電性配線を一層もしく
はそれ以上に構成した配線構造体において、前記
絶縁層の全部もしくは一部が一般式: (H2-aRaSiO)o 〔式中、RはH3SiO,H2CH3SiO,H(CH32SiO
もしくは(CH33SiOであり、aは0もしくは1
で、分子中のaの平均値は0と1の範囲にある。〕
で表わされるポリシロキサンの末端をH3SiO,
H2CH3SiO,H(CH32SiOもしくは(CH33SiO
で封鎖してあるシリコーン樹脂を塗布し、300〜
500℃で熱処理してSiOx化した層で形成されてい
ることを特徴とする配線構造体。
[Claims] 1. A wiring structure comprising one or more layers of an insulating layer and conductive wiring on a substrate, in which all or part of the insulating layer has the general formula: (H 2-a RaSiO) o [ In the formula, R is H 3 SiO, H 2 CH 3 SiO, H(CH 3 ) 2 SiO
or (CH 3 ) 3 SiO, where a is 0 or 1
So, the average value of a in the molecule is in the range of 0 and 1. ]
The ends of the polysiloxane represented by H 3 SiO,
H 2 CH 3 SiO, H(CH 3 ) 2 SiO or (CH 3 ) 3 SiO
Apply silicone resin sealed with 300~
A wiring structure characterized by being formed of a layer heat-treated at 500°C to form SiOx.
JP5252983A 1983-03-30 1983-03-30 Wiring structure Granted JPS59178749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5252983A JPS59178749A (en) 1983-03-30 1983-03-30 Wiring structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5252983A JPS59178749A (en) 1983-03-30 1983-03-30 Wiring structure

Publications (2)

Publication Number Publication Date
JPS59178749A JPS59178749A (en) 1984-10-11
JPH0230572B2 true JPH0230572B2 (en) 1990-07-06

Family

ID=12917275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5252983A Granted JPS59178749A (en) 1983-03-30 1983-03-30 Wiring structure

Country Status (1)

Country Link
JP (1) JPS59178749A (en)

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JP2565351B2 (en) * 1987-07-27 1996-12-18 京セラ株式会社 Electronic circuit parts
JP2565362B2 (en) * 1987-12-28 1996-12-18 京セラ株式会社 Method for manufacturing multilayer wiring board
US5387480A (en) 1993-03-08 1995-02-07 Dow Corning Corporation High dielectric constant coatings
US5693701A (en) 1995-10-26 1997-12-02 Dow Corning Corporation Tamper-proof electronic coatings
US5753374A (en) 1995-11-27 1998-05-19 Dow Corning Corporation Protective electronic coating
US5609925A (en) 1995-12-04 1997-03-11 Dow Corning Corporation Curing hydrogen silsesquioxane resin with an electron beam
US5693565A (en) * 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
US5807611A (en) * 1996-10-04 1998-09-15 Dow Corning Corporation Electronic coatings
US5711987A (en) * 1996-10-04 1998-01-27 Dow Corning Corporation Electronic coatings
US5707681A (en) * 1997-02-07 1998-01-13 Dow Corning Corporation Method of producing coatings on electronic substrates
TW392288B (en) 1997-06-06 2000-06-01 Dow Corning Thermally stable dielectric coatings
US5866197A (en) * 1997-06-06 1999-02-02 Dow Corning Corporation Method for producing thick crack-free coating from hydrogen silsequioxane resin
US5906859A (en) * 1998-07-10 1999-05-25 Dow Corning Corporation Method for producing low dielectric coatings from hydrogen silsequioxane resin
US6572974B1 (en) 1999-12-06 2003-06-03 The Regents Of The University Of Michigan Modification of infrared reflectivity using silicon dioxide thin films derived from silsesquioxane resins
US6576300B1 (en) 2000-03-20 2003-06-10 Dow Corning Corporation High modulus, low dielectric constant coatings
US6759098B2 (en) 2000-03-20 2004-07-06 Axcelis Technologies, Inc. Plasma curing of MSQ-based porous low-k film materials
US6913796B2 (en) 2000-03-20 2005-07-05 Axcelis Technologies, Inc. Plasma curing process for porous low-k materials
US6756085B2 (en) 2001-09-14 2004-06-29 Axcelis Technologies, Inc. Ultraviolet curing processes for advanced low-k materials
KR101247545B1 (en) 2004-11-02 2013-03-26 다우 코닝 코포레이션 Resist composition
JP5085649B2 (en) 2006-06-28 2012-11-28 ダウ コーニング コーポレーション Silsesquioxane resin system containing basic additives with electron withdrawing groups
KR101293937B1 (en) 2006-06-28 2013-08-09 다우 코닝 코포레이션 Silsesquioxane resin systems with base additives bearing electron-attracting functionalities
JP2014500897A (en) 2010-11-09 2014-01-16 ダウ コーニング コーポレーション Hydrosilylation-cured silicone resin plasticized with organophosphate compounds
CN106461811B (en) 2014-04-09 2019-03-12 美国陶氏有机硅公司 Optical element
CN106029556B (en) 2014-04-09 2019-06-18 美国陶氏有机硅公司 Hydrophobic products

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JPS5477557A (en) * 1978-11-15 1979-06-21 Toshiba Corp Monostable multivibrator circuit

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