JPH0230604B2 - RITOKUKAHENKAIRO - Google Patents
RITOKUKAHENKAIROInfo
- Publication number
- JPH0230604B2 JPH0230604B2 JP14665381A JP14665381A JPH0230604B2 JP H0230604 B2 JPH0230604 B2 JP H0230604B2 JP 14665381 A JP14665381 A JP 14665381A JP 14665381 A JP14665381 A JP 14665381A JP H0230604 B2 JPH0230604 B2 JP H0230604B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- transistors
- resistor
- differential pair
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements
- H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid-state elements in emitter-coupled or cascode amplifiers
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Processing Of Color Television Signals (AREA)
Description
【発明の詳細な説明】 本発明は利得可変回路に関するものである。[Detailed description of the invention] The present invention relates to a variable gain circuit.
従来の利得可変回路は第1図に示すように差動
対Q1,Q2を不平衡な状態にし、電流I1,I2の分流
比を変えて、I1を通して得られる信号〔Q3又は
Q4のベースに与えられる交流信号〕の利得を可
変するようなものであつたから温度に対する特性
は第2図に示すように頗る悪かつた。第2図にお
いて横軸は温度(℃)を、縦軸は利得をとつてお
り、分流比が1:1から離れるとイ,ロ,ハ,
ニ,ホ,ヘの如く温度ドリフトが大きくなるとい
う欠点があり、補償も困難であつた。 As shown in Figure 1, the conventional variable gain circuit puts the differential pair Q 1 and Q 2 in an unbalanced state, changes the shunt ratio of the currents I 1 and I 2 , and changes the signal obtained through I 1 [Q 3 or
Since the gain of the alternating current signal applied to the base of the Q4 was variable, the temperature characteristics were extremely poor, as shown in Figure 2. In Figure 2, the horizontal axis shows the temperature (°C) and the vertical axis shows the gain, and as the splitting ratio deviates from 1:1, it changes to A, B, C,
The disadvantage is that the temperature drift increases as shown in (D), (E), and (F), and it is difficult to compensate for this.
また、従来回路ではボリウム(VR)による制
御感度は抵抗R1とR2の比によつて決まるので、
制御感度を上げようとすると抵抗R1とR2の比を
大きく選んでおかなければならないが、ICにお
いては、抵抗比が大きければ、それだけ回路の特
性はバラツクことになり、好ましくない。 In addition, in the conventional circuit, the control sensitivity by the volume (VR) is determined by the ratio of resistors R 1 and R 2 , so
In order to increase the control sensitivity, the ratio between resistors R 1 and R 2 must be selected to be large, but in ICs, the larger the resistance ratio, the more the circuit characteristics will vary, which is not desirable.
本発明はこのような欠点を除去するように工夫
した新規且つ有効な利得可変回路を提案するもの
である。 The present invention proposes a novel and effective variable gain circuit devised to eliminate such drawbacks.
以下図面に示した実施例に従つて詳述する。 The embodiments will be described in detail below according to the embodiments shown in the drawings.
本発明では第3図に示すように第1、第2トラ
ンジスタT51,T54よりなる第1差動対と定電流
源トランジスタT55及び抵抗R67から構成される
差動増幅回路に第3、第4トランジスタT52,
T53よりなるトランジスタ対の各エミツタとT51,
T54のエミツタ間に比較的高い(例えば2.2KΩ程
度)抵抗R64,R65が介在される如く接続し、前
記第1、第2トランジスタT51,T54の少くとも
一方に入力された交流信号の利得をボリウム
(VR)を調整することによつて第1、第2抵抗
R68,R70の接続点の電位、即ち第3、第4トラ
ンジスタT52,T53のベース電位を変え、それに
よつて第3、第4トランジスタT52,T53のエミ
ツタ電流を変え、結果として第1、第2トランジ
スタT51,T54のコレクタ・エミツタ間を流れる
直流電流を変えることによつて可変し、その利得
可変された交流信号を例えば第2トランジスタ
T54のコレクタから取り出すようになつている。
E1,E2は一定のバイアス電源を示し、E2はアー
スとすることもできる。 In the present invention , as shown in FIG . , fourth transistor T 52 ,
Each emitter of a transistor pair consisting of T 53 and T 51 ,
A relatively high (for example, about 2.2KΩ) resistors R 64 and R 65 are connected between the emitters of T 54 , and an alternating current input to at least one of the first and second transistors T 51 and T 54 . The signal gain can be adjusted by adjusting the volume (VR) of the first and second resistors.
By changing the potential at the connection point of R 68 and R 70 , that is, the base potential of the third and fourth transistors T 52 and T 53 , and thereby changing the emitter currents of the third and fourth transistors T 52 and T 53 , the result is The gain is varied by changing the DC current flowing between the collectors and emitters of the first and second transistors T 51 and T 54 , and the AC signal with the variable gain is transmitted to the second transistor, for example.
It is designed to be taken out of the T 54 collector.
E 1 and E 2 represent constant bias power supplies, and E 2 can also be grounded.
上記実施例において、抵抗R64,R65は1つの
抵抗で共通化してもよい。また図示において第
3、第4トランジスタT52,T53のコレクタは、
それぞれ第1、第2トランジスタT51,T54のコ
レクタと結合されているが、そのような結合をせ
ずに電源ラインに直接接続してもよい。 In the above embodiment, the resistors R 64 and R 65 may be shared by one resistor. In addition, in the illustration, the collectors of the third and fourth transistors T 52 and T 53 are
Although they are coupled to the collectors of the first and second transistors T 51 and T 54 , respectively, they may be directly connected to the power supply line without such coupling.
第5図は本発明の利得可変回路をカラーテレビ
ジヨン受像機のカラー増幅回路における自動利得
可変回路2として使用した場合の例を示してお
り、21は合成カラー信号(搬送色信号+カラー
バースト)を通過せしめるバンドバス回路であ
る。 FIG. 5 shows an example in which the variable gain circuit of the present invention is used as the automatic variable gain circuit 2 in a color amplifier circuit of a color television receiver, and 21 shows a composite color signal (carrier color signal + color burst). This is a band bus circuit that allows the
手動利得可変回路2は前述のトランジスタ
T51,T52,T53,T54,T55、抵抗R63,R64,R65,
R66,R67,R68,R70、ボリウム(VR)による部
分で形成され、自動利得可変回路3はトランジス
タT46,T56,T57,T58,T59,T62、抵抗R69,
R72による部分で形成されており、トランジスタ
T48,T49,T50、ダイオードD8,D9、抵抗R54,
R55,R56,R57,R58,R59,R60,R61は定電圧回
路を形成している。T65は第2カラー増幅器4を
構成するトランジスタであつて、その出力はエミ
ツタフオロワトランジスタT66を介してK点に出
力される。 The manual gain variable circuit 2 is the transistor described above.
T 51 , T 52 , T 53 , T 54 , T 55 , resistance R 63 , R 64 , R 65 ,
R 66 , R 67 , R 68 , R 70 , and a volume (VR) part, and the automatic gain variable circuit 3 includes transistors T 46 , T 56 , T 57 , T 58 , T 59 , T 62 , and resistor R 69 ,
The transistor is formed by R72
T 48 , T 49 , T 50 , diode D 8 , D 9 , resistor R 54 ,
R55 , R56 , R57 , R58 , R59 , R60 , and R61 form a constant voltage circuit. T65 is a transistor constituting the second color amplifier 4, and its output is outputted to point K via an emitter follower transistor T66 .
バンドパス回路21を通して与えられた合成カ
ラー信号は抵抗R62を介して第1差動対を形成す
る一方のトランジスタT51のベースに供給され自
動利得可変回路2の出力点aから自動利得可変回
路3の出力点dに出力され、第2カラー増幅器4
に入力される。 The composite color signal applied through the bandpass circuit 21 is supplied to the base of one transistor T51 forming the first differential pair via a resistor R62 , and is supplied from the output point a of the automatic variable gain circuit 2 to the automatic variable gain circuit. 3 to the output point d of the second color amplifier 4.
is input.
自動利得可変回路3を構成する差動対のうち
T58,T59よりなる差動対23はd点に出力され
る直流出力レベルを一定にするように働くだけで
ある。一方信号の増幅にあずかる差動対22を構
成するトランジスタT56,T57のうちT57はオフと
なつているが、ACC信号が上がるとトランジス
タT46はオフとなり、トランジスタT57のベース
電位はACC電圧によつて決まる。 Of the differential pairs constituting the automatic variable gain circuit 3
The differential pair 23 consisting of T 58 and T 59 only works to keep the DC output level output to point d constant. On the other hand, among the transistors T 56 and T 57 that constitute the differential pair 22 that participate in signal amplification, T 57 is off, but when the ACC signal goes up, the transistor T 46 is turned off, and the base potential of the transistor T 57 is Depends on ACC voltage.
ACC電圧によるトランジスタT57のオン状態で
は、T57を流れる直流電流がACC電圧によつて制
御され、従つて、これと差動対を組むトランジス
タT56の直流電流も変化し、d点に出力される合
成カラー信号の利得はACC電圧によつて自動的
に制御されることになる。 When the transistor T 57 is turned on by the ACC voltage, the DC current flowing through T 57 is controlled by the ACC voltage, and therefore the DC current of the transistor T 56 forming a differential pair with it also changes, and is output at point d. The gain of the resulting composite color signal will be automatically controlled by the ACC voltage.
T60,T61はカラーキラー信号によつて作動す
るトランジスタであつて、これらのトランジスタ
T60,T61は図示の如く接続されていてj点に与
えられるカラーキラー回路の出力がローレベルの
ときにオフとなつて、手動利得可変回路2のトラ
ンジスタT51,T52,T53,T54の働きに何ら関与
しないが、j点に与えられるカラーキラー回路1
5の出力がハイレベルのときは導通して、それら
のエミツタ電位を上げるのでトランジスタT51,
T54はオフ状態となり、トランジスタT51のベー
スに与えられている信号はトランジスタT54のコ
レクタ、従つてa点に出力されない。このように
してカラーキラーが行なわれる。 T 60 and T 61 are transistors operated by color killer signals, and these transistors
T 60 and T 61 are connected as shown in the figure, and are turned off when the output of the color killer circuit given to point j is low level, and the transistors T 51 , T 52 , T 53 , Color killer circuit 1 that is not involved in the function of T 54 but is applied to point j
When the output of T51 is high level, it becomes conductive and raises the emitter potential of the transistors T51 and T51 .
T54 is turned off, and the signal applied to the base of transistor T51 is not output to the collector of transistor T54 , and therefore to point a. Color killer is performed in this way.
本発明の利得可変回路によれば差動対T51,
T54及びトランジスタ対T52,T53が常に平衡状態
を保つことになり温度特性は極めてよい。従つ
て、第4図に示すように、どのような状態ト,
チ,リ,ヌ,ル〔ボリウムVRによつて直流電流
を変た状態〕でも温度特性は略一定であり、わず
かな変化は例えば定電流源に手当を施こすことに
より簡単に補償できる。ただし、第4図の如き特
性であればそのような手当を施さなくても十分実
用に供しうる。また第3、第4トランジスタ
T52,T53のベース電位の変化は抵抗R64,R65に
よつて第1、第2トランジスタT51,T54のエミ
ツタでは小さくなるという如く制御端子側〔ボリ
ウムVR側〕からみた利得は抵抗R64,R65で制限
されるので低く、従つて抵抗R68とR70の比を大
きくとる必要がないという長所もあり、IC化に
好適である。 According to the variable gain circuit of the present invention, the differential pair T 51 ,
Since T 54 and the transistor pair T 52 and T 53 always maintain an equilibrium state, the temperature characteristics are extremely good. Therefore, as shown in FIG.
The temperature characteristics are approximately constant even when the DC current is varied by the volume VR, and slight changes can be easily compensated for by making adjustments to the constant current source, for example. However, if the characteristics are as shown in FIG. 4, it can be put to practical use without such measures. Also, the third and fourth transistors
Changes in the base potentials of T 52 and T 53 are reduced by the resistors R 64 and R 65 at the emitters of the first and second transistors T 51 and T 54 , so the gain seen from the control terminal side (volume VR side) is Since it is limited by the resistances R 64 and R 65 , it is low, and there is also the advantage that there is no need to take a large ratio between the resistances R 68 and R 70 , making it suitable for IC implementation.
尚、第3、第4トランジスタT52,T53のエミ
ツタを第1、第2トランジスタT51,T54のエミ
ツタに抵抗R64,R65を介することなく直接接続
することも考えられるが、この場合には第3、第
4トランジスタT52,T53のベース・エミツタ間
容量が第1、第2トランジスタT51,T54の負荷
として作用(検波作用を行なう)するので好まし
くないが、本発明では前記抵抗R64,R65によつ
て前記第3、第4トランジスタのベース・エミツ
タ間容量は第1、第2トランジスタT51,T54の
エミツタに対し隔離されるような形になるので前
記検波作用は生じない。 It is also conceivable to directly connect the emitters of the third and fourth transistors T 52 and T 53 to the emitters of the first and second transistors T 51 and T 54 without using the resistors R 64 and R 65 , but this In this case, the base-emitter capacitance of the third and fourth transistors T 52 and T 53 acts as a load (performs a detection function) for the first and second transistors T 51 and T 54 , which is not preferable, but the present invention Then, the base-emitter capacitance of the third and fourth transistors is isolated from the emitters of the first and second transistors T 51 and T 54 by the resistors R 64 and R 65 . No detection effect occurs.
第1図は従来の利得可変回路を示す回路図、第
2図はその説明図である。第3図は本発明を実施
した利得可変回路を示す回路図であり、第4図は
その説明図、第5図はその使用例を示す回路図で
ある。
T51,T54……第1差動対を形成するトランジ
スタ、T52,T53……第2差動対を形成するトラ
ンジスタ、R64,R65……抵抗、R68……第1抵
抗、R70……第2抵抗。
FIG. 1 is a circuit diagram showing a conventional variable gain circuit, and FIG. 2 is an explanatory diagram thereof. FIG. 3 is a circuit diagram showing a variable gain circuit embodying the present invention, FIG. 4 is an explanatory diagram thereof, and FIG. 5 is a circuit diagram showing an example of its use. T 51 , T 54 ... Transistors forming the first differential pair, T 52 , T 53 ... Transistors forming the second differential pair, R 64 , R 65 ... Resistors, R 68 ... First resistors , R 70 ...Second resistance.
Claims (1)
ベースに与えられ少くとも一方のトランジスタの
コレクタから出力を得るようにした差動対と、 前記差動対のエミツタ結合点に両エミツタが抵
抗を介して接続され、両コレクタが夫々前記差動
対の両コレクタ若しくは電源ラインに接続され、
更に両ベースが共通に接続されたトランジスタ対
と、 一端が、一定電位点に接続された第1抵抗とこ
の第1抵抗の他端に一端が接続された第2抵抗と
この第2抵抗の他端に可変端子が接続されたボリ
ウムとからなり、前記第1、第2抵抗の接続点が
前記トランジスタ対の両ベースに共通に接続さ
れ、前記差動対の利得を可変するべく前記トラン
ジスタ対に流れるエミツタ直流電流を共通に可変
する可変手段とからなる利得可変回路。[Claims] 1. A differential pair in which an input signal is applied to the base of at least one transistor and output is obtained from the collector of at least one transistor, and both emitters are connected to the emitter connection point of the differential pair. connected via a resistor, both collectors being connected to both collectors of the differential pair or the power supply line, respectively;
Furthermore, a pair of transistors having both bases connected in common, a first resistor having one end connected to a constant potential point, a second resistor having one end connected to the other end of the first resistor, and the other end of the second resistor. a volume having a variable terminal connected to its end; a connection point between the first and second resistors is commonly connected to both bases of the transistor pair; and a volume is connected to the transistor pair to vary the gain of the differential pair. A variable gain circuit consisting of variable means that commonly varies the flowing emitter direct current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14665381A JPH0230604B2 (en) | 1981-09-16 | 1981-09-16 | RITOKUKAHENKAIRO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14665381A JPH0230604B2 (en) | 1981-09-16 | 1981-09-16 | RITOKUKAHENKAIRO |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55127581A Division JPS5752288A (en) | 1980-09-11 | 1980-09-11 | Color gain variable circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5781712A JPS5781712A (en) | 1982-05-21 |
| JPH0230604B2 true JPH0230604B2 (en) | 1990-07-09 |
Family
ID=15412585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14665381A Expired - Lifetime JPH0230604B2 (en) | 1981-09-16 | 1981-09-16 | RITOKUKAHENKAIRO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0230604B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2305564A (en) * | 1995-09-19 | 1997-04-09 | Nec Corp | Bipolar operational transconductance amplifier |
-
1981
- 1981-09-16 JP JP14665381A patent/JPH0230604B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5781712A (en) | 1982-05-21 |
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