JPH0231895B2 - - Google Patents

Abstract

PURPOSE:To avoid the error and uncertainty in the result of detection, by providing a means which detects that the point of time of logical level change of a signal to be measured and the point of time of logical level detection arrive within a prescribed range. CONSTITUTION:Causes to errors in data test are that the test point is separated from driving and a voltage at the test point is floated (tri-state). In order to detect when this state takes place, a data line is connected to a non-inverting input of a pair of comparators 69 and 610. An inverting input of the comparators 69, 610 is respectively connected to a high reference voltage source 64 and a low level reference voltage source 65. A data H signal is produced at the output of the comparator 69 and a data L signal is at the output of the comparator 610. The data H goes to a high level only when a voltage of a data signal (d) on a line 61 is higher than a value VH of the voltage source 64, and the data L is goes to a high level only when the voltage of the signal (d) is higher than a value VL of the voltage source 65, and a tri-state signal T is produced at the output of a gate 611.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for detecting the logic level of a digital signal, and in particular to a device for detecting the logic level of a digital signal, and in particular, a method for detecting errors and uncertainties in detection results caused by the time point at which the logic level of the digital signal changes approaches the detection timing. Concerning devices that can be avoided.

A number of techniques have been developed for testing digital devices because of the qualitative differences between the types of signals present in digital devices and the types of signals present in analog devices. These testing techniques typically apply a set of test signals to various points in a circuit and observe a time series of digital data that occurs at one or more points. For example, FIG. 9 is a diagram explaining the principle of such a test, in which a two-input AND gate, a pair of input signals for testing the operation of the AND gate, and an output corresponding to the displayed test input signal are shown. The correct output signal at the port is shown. This AND gate is tested by observing the time series of digital data occurring at the output port and comparing the observed data time series with that of a good (i.e., properly functioning) AND gate.

In complex circuits, data time series must be observed at many test points, and each data time series usually contains many more bits than the 4-bit data time series in the example shown in Figure 9. . Due to the large amount of test data generated during typical digital equipment testing, many testing techniques process time series of data to generate output data that can be easily used by the tester. . In a method known as tracsition counting,
The test equipment processes each data series and counts the number of times the data transitions from a low level to a high level or from a high level to a low level.

Signature analysis b
(Apparatus and Method for Testing Digital by Gary B. Gordon and others)
Another digital testing method, known as U.S. Pat. to yield a length remainder (known as a signature). Each code is typically 16 or 20
The length is chosen to be in bits, so that the remainder is displayed as a 4- or 5-digit hexadecimal number.
The signature analysis method measures the signatures at each test point of the circuit under test and compares these signatures with those of a circuit known to be correct. These 2
The circuit under test is considered defective when the sets of characteristic indicators are not identical. In order to identify the actual defective element in a circuit, it is often possible to locate the element that outputs a signal that provides an incorrect characteristic indicator when a signal that provides a correct characteristic indicator is input.

These digital testing techniques rely on accurately detecting the time series of observed data. One cause of inaccurate detection of data time series is sampling data near transition points in data levels. When this happens, slight variations between circuits may cause some units under test to sample data slightly before the level transition.
The other unit under test transitions the corresponding data and samples it a little later. Therefore, due to the above-mentioned problems in testing technology, some of the units under test are labeled as ``defective'', which causes some ``good units'' to be determined as ``defective units.''

Another source of inaccuracy in detecting a time series of data is that there may be periods during which the test points of the circuit are not driven to either a high or low level by the unit under test. During such periods, these test points are at high impedance and may drift. That is, depending on the amount of net leakage current at the test point, the potential at the test point often becomes high level or low level. Therefore, during the above-mentioned period, if the units under test are different, a situation may occur in which the test point of one unit drifts toward a higher level, and the corresponding test point of the other unit drifts toward a lower level. Due to such variations, characteristic indicators vary from unit to unit. Similarly, such non-driven lines are susceptible to noise changes due to parasitic capacitances and the like, so the characteristic signature of such test points changes from test to test. Accurately testing digital devices therefore requires detecting when either of these two sources of potential error occurs and modifying the test technique to eliminate such errors or uncertainties. It is important to.

Generally, digital data does not transition along an ideal square wave from low level to high level or from high level to low level. Since these transitions occur along curves with finite slope, such transition times are non-zero. Moreover, such rapid transitions are accompanied by transient oscillations that must be damped to a certain level before digitally accurate signal detection is possible. Accurately measuring digital data as a result of such effects requires the setup time after a data transition.
The measurement must not be started for a short period of time known as Ts. Similarly, since the measurement process is not instantaneous, no data transitions are allowed within a short period of time, known as the hold time Th, after the start of the measurement.

In digital devices, the data time series within the device is typically generated synchronously with a clock signal. It is therefore natural to use such a clock signal to control the selection of data sample times from the unit under test. Under some test situations the clock signal is generated by the unit under test, while under other conditions the test equipment provides the clock signal. Clock signals are normally periodic but may be non-periodic in some cases. for example
The asynchronous interface HP-IB defined by IEEE Standard 488 allows data to be transmitted asynchronously,
One of the data lines carries the DAV signal, which determines when the data on the other data line is valid. Therefore, when testing the operation of such an interface, the DAV signal can be used as a clock signal to control the selection of measurement times. In each case, data sampling is initiated in response to a clock signal, so whether the clock signal transition occurs within the time interval before and after the data transition determined by the setup and hold times. It is important to detect

The timing of data transitions relative to clock transition times varies depending on which test point of the unit under test is being tested. For example,
Patsucard's HP3060Board Test System uses a contact mechanism called bed of nails, which has a sword-like appearance.
Contact the HP3060 circuit board under test. The mechanism contacts each test point on the circuit board with one of the HP3060's test probes. Therefore, the relative variation in delays between data collected at various test points is caused first by differences in the delay times for signals within the circuit board under test to arrive at the test points, and then by differences in the delay times for signals within the circuit board under test to arrive at the test points. This adds the relative delay due to the variation in delay between the various signal paths within the HP3060 that the received data travels.
Therefore, the delay time seen from the clock signal may be different for each data detected at each test point. As a result, even if the data detection at one test point is inaccurate, it may be accurate at some other test points. Therefore, it is important to check the timing of data transition from the point of clock transition for each test point.

According to the present invention, in order to detect an undesirable situation in which the clock and data transitions substantially coincide, an auxiliary signal having pulses synchronized with the transitions of the data signal is first generated from the data signal. Each of these pulses has a width T ₁ + T ₂ (T ₁ is the time after the data transition at which reproducible measurements cannot be started;
Moreover, T ₂ is the time before data transition, during which reproducible measurements cannot be started. )have. This width is equal to the width of the time period during which measurements before and after each transition should not be made. To see if the clock and data transitions approach each other as described above, the clock signal is delayed by a time T ₂ and one of the auxiliary signals pulses (becomes a "1" level). Check if there is a transition during the current period that triggers a data measurement. if,
If such a transition occurs during the auxiliary signal pulse, a flag is set to report the event to the user. If this approach occurs, the person testing the unit can choose a fixed delay Td.
The close state can be avoided by delaying the clock signal or the signal under test.

Another source of error or uncertainty in logic level measurements is that the test point may not be driven to a high or low logic level, but rather is left floating in a high impedance state. At such a floating test point, its voltage (logic level) will tend to drift toward a higher or lower level depending on the sign of the net leakage current. To prevent such drift that may vary from unit to unit under test, each test probe is connected through a high resistor to a voltage intermediate between the high logic level voltage and the low logic level voltage. The criteria for selecting this resistance value are, firstly, that the resistance value be high enough so that the leakage current through this resistor does not interfere with testing at test points that are not in a floating state; The first step is to make the resistance low enough that the leakage current through the resistor exceeds the current causing the drift and pulls the floating test point substantially to the aforementioned intermediate voltage. This intermediate voltage is chosen to be sufficiently far away from the high logic level voltage and the low logic level voltage so that it can be identified as a third voltage level. This allows the test device to detect that the test point is not activated.

Unfortunately, noise sources cause the voltage at the floating test point to change over time, and even with the above measures, the voltage at the floating test point changes over time. The logic level may become large enough to be detected as a high or low level. Therefore,
It is useful to ignore the data at a test point while it is in a floating state. Such data should be ignored by using the limited time signal (date
qualifier) and deactivate the clock signal. Data limited signals also have more general application. For example, it can be used to ignore selected period data even when the data is good.
For example, consider the case where a set of read-only memories (hereinafter referred to as ROM) are connected in parallel to a data bus and an address bus. these
To test the ROM, first connect the address bus
Given a sequence of addresses that manipulate the entire address space of the ROM, we measure characteristic indicators for the data bus. If this characteristic mark is defective
In order to test each ROM individually, the chip selection signal of a certain ROM is used as a data-limiting signal.
Selection of this limited signal allows the test equipment to connect to other ROMs.
data from the ROM can be ignored, thereby allowing the selected ROM to be tested separately.

Embodiments of the present invention will be described below based on the drawings.

1 is a diagram illustrating a circuit suitable for detecting the approximate coincidence of the trigger edge of clock C of FIG. 1 and a transition of a data line from a low level to a high level; FIG. Further, FIG. 2 is a diagram showing signals in the circuit in FIG. 1. Here, the data signal d is applied to the data line 11 and connected to one input of a two-input AND gate 12. The data signal d is also inverted by the inverter 13 and then the delay circuit 1
4 becomes a delayed data signal d', which is applied to the other input of AND gate 12. The output signal of AND gate 12 is high only when both data signal d and delayed data signal d' are high. FIG. 2 shows the relationship between these three signals.

The output signal d'' of AND gate 12 is applied to the D input of edge-triggered D flip-flop 15. Clock signal C is applied to clock line 16 and passes through delay circuit 17 to the clock input of edge-triggered D flip-flop 15. CK.This delayed clock signal C' and AND gate 1
The relationship between the two output signals d'' is also shown in Figure 2, assuming that the sampling of data occurs in response to a low to high transition of the clock signal. Therefore, the edge-triggered D flip-flop 15 is selected to respond to a low-to-high transition of the signal on its clock input CK, and conversely, to respond to a high-to-low transition of the clock signal. When starting (i.e., sampling data), flip-flop 15 is also a clock input.
Selected to respond to a high to low transition of the CK signal.

Delay circuits 14 and 17 are selected to provide delays of T ₁ +T ₂ and T ₂ respectively. By choosing the delay like this, the time after the data transition
AND gate 12 only if clock signal C rises within T ₁ or within time T ₂ before data transition.
A delayed clock signal is generated while the output signal d'' pulse is present.As mentioned above, the reproducibility of the measurement is not guaranteed in the time period T ₁ +T ₂ before and after this.

Elements 11, 12, 13, 14 shown in FIG.
It must be noted that the circuit configuration of 2 generates a pulse only for data transitions from low level to high level. On the other hand, FIG. 3 is a diagram showing a circuit for generating a pulse for a transition from a high level to a low level, and the elements 11 to 1 in FIG.
It can be used instead of the circuit consisting of 14. In the circuit of FIG. 3, the data signal d is applied to the data line 31, passes through the inverter 33 to become an inverted data signal, and is connected to one input of the AND gate 32, and the data signal d also passes through the delay circuit 34. Becomes delayed data signal e
is applied to the other input of AND gate 32 to generate AND gate 32's output signal e'. Figure 4 is the third
3 is a diagram illustrating a signal resulting from applying a data signal d to data line 33 in the illustrated circuit; FIG.

The circuit shown in FIG. 1 allows detection of the occurrence of clock transitions near low to high data transitions. Elements 11 to 14 in FIG.
If the circuit consisting of is replaced with the circuit of FIG. 3, it becomes possible to detect the occurrence of a clock transition near a data transition from a high level to a low level. or,
AND gate 12 (Figure 1) and AND gate 3
2 (FIG. 3) can also be applied to the inputs of a two-input OR gate to create an auxiliary signal that produces pulses at both types of data transition points. flip-flop
By applying this auxiliary signal to the D input of flop 15, the occurrence of a clock transition near the transition point for either type of data transition can be detected.

If an undesirable situation in which the clock and data transitions are nearly coincident is detected, the problem can be alleviated by delaying one signal relative to the other. Since this problem can occur on any of the data lines, it is easier to insert a variable delay circuit on the clock line than to insert a variable delay circuit on each data line. FIG. 5 is a diagram showing an example of a variable delay circuit. In this circuit,
The clock signal C is sent through four parallel lines, each line having a delay of 0, D ₁ , D ₂ and D ₃ inserted respectively. A pair of control signals A and B select which input line of multiplexer 51 is connected to output line 52 under user control. Initially inputs A and B are both zero, selecting zero delay. If the aforementioned data and clock transitions occur close to each other in this state, the delay D ₁
Select. If the above-mentioned proximity state still remains, select delay D ₂ this time. Finally, if delay D ₂ is inappropriate, select delay D ₃ .

Generally in any test, data lines from each of several test points supply data. Since each line has a different delay relative to the clock signal, the aforementioned close proximity of clock and data transitions on one line does not occur on others. If more than one clock delay can be selected, one of them increases the likelihood of avoiding the aforementioned proximity condition during all data times. If you get 4th in a given exam
If the four delays of the illustrated circuit are not sufficient to eliminate coincidence of all data and clock transitions, several alternatives can be used to accurately test all test points. The first alternative is to increase the number and/or range of delays. A second alternative is to insert variable delays on some or all of the data lines. A third alternative is to first process only the data on the lines where the aforementioned proximity condition does not occur when the delay is chosen to be zero. Then change the delay to D ₁ to test only lines that have not yet been tested and where no proximity condition has occurred. If some lines show proximity again, repeat this step with a delay _D2 . And repeat for delay D ₃ if necessary. clock rate up to 10MHz (i.e.
For test equipment configured to handle clock periods greater than 100 nanoseconds, the delays D ₁ , D ₂ ,
It is effective to select D ₃ to be 30, 60, and 90 nanoseconds, respectively. Since typical values of times T ₁ and T ₂ are 30 ns and 20 ns, respectively,
By selecting the amount of delay as described above, it is possible to eliminate coincidence of transitions on any given data line with clock signal transitions.

Another source of error in data testing, as previously discussed, is when the test point is disconnected from the drive, resulting in a floating voltage at the test point. Under such conditions, the voltage at the test point may drift toward one of the two logic voltages, depending on the leakage current. Therefore, floating test point voltages are not effective in testing whether the circuit is performing its intended function. Therefore, it is important to detect when this condition occurs. FIG. 6 shows a suitable circuit for detecting this condition.

In the circuit shown in FIG. 6, the data signal under test d is applied to the data input line 61. In the circuit shown in FIG. A pair of resistors 62 and 63 connect high level reference voltage source 6
4 and a low-level reference voltage source 65. These resistors act as a voltage divider to create an intermediate voltage between the high level reference voltage source voltage V _H and the low level reference voltage source voltage V _L at the connection point 66 between the resistors. Preferably, resistors 62 and 63 are substantially equal, so that the intermediate voltage is intermediate between both reference voltage sources V _H , V _L . However, the intermediate voltage need only be sufficiently far away from the high-level reference voltage _VH and the low-level reference voltage _VL to be distinguishable from those voltages. Node 66 is connected to data line 61 through a unity gain buffer 67 and resistor 68 to pull the line voltage down to an intermediate voltage when the data line is disconnected from its driver. resistance 68
The value of is generally chosen to be as small as possible without interfering with the test while the data line is being driven (an excessively small value will pull the line voltage close to the intermediate voltage even while the data line is being driven).

The state separated from the driver (floating state) is called a 3-state condition.
To detect when this condition occurs, the data line is connected to the non-inverting inputs of a pair of comparators 69 and 610. The inverting inputs of comparators 69 and 610 are connected to high level reference voltage source 64 and low level reference voltage source 65, respectively. Data H
A signal appears at the output of comparator 69 and a data L signal appears at the output of comparator 610. Data H goes high only when the voltage of data signal d on line 61 is higher than the value V _H of high level reference voltage source 64;
On the other hand, data L becomes high level only when the voltage of data signal d is higher than the value V _L of low level reference voltage source 65. Data H and data L are applied to the inputs of a 2-input exclusive OR gate 611, and the gate 6
A 3-state signal T is generated at the output of 11, indicating that the 3-state state has been entered.

FIG. 7 is a diagram showing signals in the circuit of FIG. 6. For the square wave data signal shown in FIG. 7, data H and data L both oscillate to a high or low level almost simultaneously, so that the three-state signal T remains at a low level. When the data signal d is in the 3-state state and the data signal is pulled to the intermediate voltage value, the data H remains at a low level, but the data L
changes to high level, resulting in the three-state signal T
changes to a high level. The three-state signal T is applied to the D input of edge-triggered D flip-flop 612, and the clock signal c is applied to the CK input of flip-flop 612. Result 3
The state signals are tested in synchronization with the testing of the data lines.

The Q output of flip-flop 612 is connected to a flag, and this flag is set to "1" if a tri-state condition is detected during testing of the data line. Separate flags can be assigned to each data line to allow determination of which data lines are in tristate during data line testing.

The information that a three-state state has been entered during testing of a line is available to the tester in a number of ways.
Examine the flow of data on the data line during the test using several devices, including an oscilloscope;
It is possible to determine during which period the data line enters the tri-state state. Once that period is known, another time window can then be selected to test the data line for periods that do not include tri-state conditions. Alternatively, only the data in the 3-state state may be ignored. FIG. 8 is a diagram showing a circuit for ignoring data only during the 3-state period.

In the circuit shown in Figure 8, the qualifier
A signal Q called Q is applied to one input of a two-input AND gate 81. The clock signal is applied to a variable delay circuit 82 similar to that shown in FIG. The output of variable delay circuit 82 is applied to the other input of gate 81, and the output of gate 81 is provided as a clock signal to the test equipment.
By using variable delay circuit 82, proximity conditions can be avoided in a manner similar to that previously described using FIG. Since AND gate 81 passes the delayed clock signal only when the qualifier signal Q is high, using the qualifier signal Q stops the clock from the test equipment during the period when data is to be ignored, thereby causing the qualifier signal Q to pass. You can stop testing data during low levels.

For low noise cases, the 3-state signal can be inverted and used as a limiting signal to ignore data during the 3-state state. Unfortunately, however, the noise level is often quite large, so that despite the pull-in by the intermediate voltage,
The floating data line voltage may sometimes vary above the voltage value V _H of the high level reference voltage source 64 and below the voltage value V _L of the low level reference voltage source 65 . As a result, "0" or "1" are randomly read here and there during the three-state period. Each time such a random read occurs, the tristate signal goes low. Under these circumstances, a three-state signal is no longer a suitable limiting signal. The HP5004ASignature Analyzer manufactured by Hewlett-Packard produces a three-state signal as described above. By using this 3-state signal, the data recorded during the 3-state period is made to have the same value as the data frame immediately before the 3-state.
If random "0"s and "1"s due to noise do not occur during the three-state period, the characteristic indicators produced by this method will be reproducible. Accurate characteristic marker analysis is thus completed.
However, this scheme does not work well in noisy environments, so it is more effective to use the tristate signal to inform the user of the tristate than to mask the data during the tristate.

However, the three-state signal can be used to create a limiting signal for a board to be subsequently tested. That is, first, the 3-state signal time series is recorded. Next, by inspection, it is possible to determine the correct 3-state state period by ignoring portions of the recording in which the 3-state signal is at a low level due to noise etc. within an interval where the 3-state signal should normally be continuously at a high level. Similarly, several records of the three-state signals described above can be made and applied to a multi-input OR gate to automatically create a limiting signal for subsequent device testing. Since the low level values of the 3-state signal during the 3-state state are randomly generated by noise, the possibility that random low-level values commonly appear at the same point in the recording of several 3-state signals is as described above. It decreases as the number of 3-state signal records to be associated increases. Therefore, the possibility of producing a poorly defined signal (i.e. containing at least one random low level value) with this technique can be reduced by selecting as many three-state signal records as necessary to achieve the desired level. can be suppressed to.

[Brief explanation of drawings]

1 to 8 are diagrams showing the circuit of the logic level detector according to the present invention and the signals of each part in this circuit, and FIG. 1 shows the trigger edge of the clock and the data line from low level to high level. 2 is a diagram showing the signals in the circuit of FIG. 1; FIG. 3 is a diagram showing the signals in the circuit of FIG. FIG. 4 is a diagram showing signals in the circuit in FIG. 3, FIG. 5 is a diagram showing an example of a variable delay circuit, and FIG. FIG. 7 is a diagram showing the signals in the circuit in FIG. 6, and FIG. 8 is a diagram showing a circuit for ignoring data only during the three-state period. FIG. 9 is a diagram showing the principle of testing a digital device. 11, 13, 61: data line, 14, 1
7, 34: Delay circuit, 16: Clock line, 5
1: Multiplexer, 64: High level reference voltage source, 65: Low level reference voltage source, 69,610:
Comparator, c: clock signal, c': delayed clock signal, d: data signal, d', e: delayed data signal,
T: 3-state signal, Q: limited signal.

Claims (1)

[Claims] 1. A logic level detector that detects the logic level of a signal under test in synchronization with a clock signal, comprising means for forming an auxiliary signal synchronized with transitions of the signal under test, and delaying the clock signal. means for forming a delayed clock signal with a delay clock signal; and means for determining that a time point at which the logic level of the signal under test changes and a time point at which the logic level is detected approach a predetermined range based on the auxiliary signal and the delayed clock signal. A logic level detector characterized in that it is provided with means for detecting.