JPH0231912B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical contour signal (hereinafter abbreviated as VDTL) generation device for a television video signal (hereinafter abbreviated as a video signal).

Figure 1 shows the configuration of a conventional VDTL generator.
As is well known, conventional VDTL generators use two delay circuits (hereinafter referred to as 1H delay circuits) that are equivalent to one horizontal line, and the first The output video signal of the second 1H delay circuit (hereinafter referred to as 1H video signal), and the output video signal of the second 1H delay circuit (i.e., a video signal with a delay time equal to the time of two horizontal lines; hereinafter referred to as 2H video signal). ) is used to generate VDTL.

The delay line of the 1H delay circuit used in this device has a large delay time of approximately 63.5 microseconds, so a lumped constant delay line using LC is practically unusable, and is currently not in practical use. What is included is an ultrasonic glass delay line.

This delay line generally performs AM modulation on a carrier wave of about 30 MHz with a video signal, and uses the propagation time of this AM modulated wave within the glass to obtain the delay time. This ultrasonic glass delay line, which is currently in practical use, has a bandwidth that is only about 1/3 of the carrier frequency (i.e., the width of both AM wave bands is 10M).
Hz), and the insertion loss is 25dB to 30dB.
Moreover, this loss is easily affected by the ambient temperature.
Moreover, there are large variations depending on the individual ultrasonic glass delay lines.

In addition, in order to obtain a large delay time with a small size, this delay line needs to be reflected within the glass about 2 to 5 times, which generates spurious signals.

Although consideration has been taken in the design to reduce this spurious to a level that does not pose a practical problem, it is not perfect and sometimes causes practical problems.

As mentioned above, the ultrasonic glass delay line has some performance constraints, and in addition, because the video signal main line output is obtained from the output of the 1H delay circuit (i.e.,
Since the video signal main line output passes through an ultrasonic glass delay line), the following problems occur.

(1) Since the video signal passing band width of the ultrasonic glass delay line is approximately 5 to 6 MHz, waveform distortion is likely to occur in the video signal. Even within the band, waveform distortion of the video signal occurs due to ripples in the frequency characteristics of the ultrasonic glass delay line.

(2) Spurious noise occurs in the main line output due to the ultrasonic glass delay line (even if it does not pose a practical problem, spurious noise will still occur, and we are just putting up with it because the spurious noise is small, and the characteristics will change during use. may become unacceptable).

(3) Loss in the ultrasonic glass delay line essentially causes S/N degradation in the video signal main line output. Especially built into color television cameras.
In the VDTL generation circuit, the S/N of the entire color television camera is degraded and cannot be ignored in many cases.

(4) Due to variations in the loss of the ultrasonic glass delay line,
Fluctuations in the level of the video signal main line output occur (AGC circuits are used to counter this, but the non-linearity of the gain control circuit for AGC affects the video signal transmission as DG and DP, degrading the main line characteristics. In addition, due to changes in AGC itself over time,
(maintenance and inspection required).

(5) Since AM modulation is performed using an ultrasonic glass delay line, nonlinearity caused by the modulator, demodulator, and transducer of the ultrasonic glass delay line causes deterioration of DG and DP. This becomes a particular problem when generating VDTL for the luminance signal of a video signal that has become an NTSC color signal.

(6) Since the main line output video signal is obtained from the 1H delay circuit, it is
When using a VDTL generation circuit, 1
This causes a phase shift in the horizontal line. For this reason, the phase of vertical synchronization also causes a difference of one horizontal line, and the use of a VDTL generation circuit for NTSC color signals is subject to restrictions due to this phase shift. in general
When generating VDTL with NTSC color signal,
VDTL is obtained from the luminance signal component.

The above are mainly the characteristics and usability problems caused by the ultrasonic glass delay line and the conventional device, but in addition to these, the conventional mounting has the following visual problems with the VDTL.

In standard television broadcasting, intermittent scanning is prescribed. An example of obtaining VDTL from a video signal obtained from a subject as shown in FIG. 2 will be explained. The perspective part of FIG. 2 is black, and the white part in the center is white. For example, if we pay attention to the scanning line from a black part to a white part in the center, we will get a video signal as shown in FIG. 3a. FIG. 3b shows the output of the first 1H delay circuit (that is, the main video signal output), and FIG. 3c shows the output of the second 1H delay circuit.

As is well known, the VDTL signal is obtained by adding together the signals in FIG. 3 a and c in equal amounts to obtain the signal in FIG. 3 d, and then adding the signals in FIG. 3 d and e, that is,
Perform d+e to obtain VDTL shown in FIG. 3f. (e is −b×2). The signal in FIG. 3f is added to the signal in FIG. 3b after inverting the polarity and performing level control (that is, controlling the amount of VDTL). Since this VDTL generation is performed in different fields through intermittent scanning, the VDTL signal becomes thick when viewed on a cathode ray tube.

That is, according to FIG. 4, (pay attention to the white part in the center of FIG. 2), for example, if the dashed-dotted line is the scanning line by the first field, the VDTL by the first field is as shown by the dashed-dotted line in FIG. Two lines occur, one above and one below the black and white boundaries.

Similarly, if the scanning line of the second field in the same area is the broken line in Figure 4, the VDTL generated by this scanning will be one line above and below the black and white boundary line, as shown by the broken line in Figure 5. Two occur.

As is clear from Figure 5, VDTL has two lines on the black side of the boundary between black and white in images on a cathode ray tube.
VDTL and two VDTLs occur on the white side.
VDTL emphasizes the vertical contrast change at the boundary in the contour area, creating a psychological effect of visually improving the resolution, but with conventional equipment, A thick VDTL occurs, giving an unnatural feel.

If you try to improve visual resolution by increasing VDTL, thick VDTL will stand out. Also,
This thicker VDTL has the effect of suppressing thinner image parts, reducing the subtlety of the image.

Now, returning to Figure 1 and briefly explaining the conventional device, 1 in Figure 1 is a video signal input, 2 is an AM modulator, and 3 is the first 1H delay line. The output of the 1H delay line 3 is sent to the second 1H delay line 4 and a demodulator 6, and this demodulator 6 amplifies and demodulates the output of the first 1H delay line 3. , its output is sent to a processing circuit 7 and an output terminal 8 (to which the video signal of the present application is output).

Further, the output of the second 1H delay line 4 is amplified and demodulated by a demodulator 5, and the output of this demodulator 5 is sent to a processing circuit 7. Video signal input 1 is also input to the processing circuit 7, and the processing circuit 7 receives 0H, 1H,
The VDTL is processed from each 2H video signal as shown in FIG. 3 and output to the output terminal 9.
After this, the amount of VDTL is controlled,
It is added to the video signal at the output terminal 8 with the polarity to be emphasized.

In addition, the digital method eliminates the characteristic deterioration caused by conventional ultrasonic glass delay lines.
A VDTL generation device has been proposed, and in this device, as shown in FIG. are shift registers and memory devices that each delay the digitized video signal by one horizontal line; demodulators 5 and 6 are digital-to-analog converters that return the digitized video signal to the original analog video signal; (D/A converter) (hereinafter referred to as a D/A converter) (A device that obtains VDTL from a digital video signal and then performs A/D conversion may also be used.) Even in this digital system, due to the performance of the A/D converter, the following Problems such as those listed below arise.

(a) Due to the problem of quantization noise of the A/D converter,
The A/D converter requires 8 to 10 bits (the above number of bits is required because the main line video signal passes through the A/D converter). To A/D convert a video signal with this number of bits, the current sampling frequency is about 14 MHz, which limits the bandwidth of the video signal to 7 MHz or less (usually about 6 MHz). This causes waveform distortion due to high frequency components. Furthermore, an A/D converter with such performance is expensive, leading to an increase in the cost of the equipment.

(b) The phase difference between the video input and output is the same as before, 1
There will be a difference in horizontal lines. Therefore, the problem (6) mentioned above with the conventional ultrasonic glass delay line device remains unsolved.

(c) The visual problem, namely the thickness of the VDTL caused by the interspersed scanning device, is also unresolved.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional technology, and it does not cause any characteristic deterioration of the main line video signal in VDTL generation, and the phase difference of one horizontal line can be reduced by the input signal in VDTL generation. This should not occur between outputs and is a visual problem.
The thinnest VDTL is determined from the number of scan lines
It is an object of the present invention to provide a vertical contour signal generation device that can be obtained as a VDTL.

Embodiments of the vertical contour signal generating device of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram showing the configuration of one embodiment. In FIG. 6, 10 is an input terminal to which a video signal is input, and 11 is an output terminal.

The input end 10 passes through a low pass filter 23,
It is connected to the A/D converter 12. The low-pass filter 23 cuts off the input of the A/D converter 12 when it has a component higher than the sampling frequency. It converts the signal into a digital video signal, and this digital video signal is sent to the address selection write circuit 13. This address selection write circuit 13 is a circuit for writing a digital video signal into a specific address of the memory, and its output is transferred to a field memory circuit 14.

The field memory circuit 14 stores one field's worth of digital video signals, and its contents are transferred to a memory readout circuit 15 that reads out the digital video signals. The output of the memory read circuit 15 is sent to the 1H delay circuit 16.
It is designed to be delayed by one horizontal line.
The output of the 1H delay circuit 16 and the respective digital video signals from the memory read circuit 15 are added together in an adder circuit 17. The output of this adder circuit 17 is converted into an analog video signal by a D/A converter 18.

The adder circuit 17 and the D/A converter 18 can also be synchronized with a synchronization pulse obtained from a control signal that determines the address within one horizontal line, in order to align the delay times of the digital circuits. The pulse path is shown as a dashed line.

On the other hand, 21 is an address control circuit, and an input terminal 22 of this address control circuit 21 receives horizontal and vertical synchronization information for the address control circuit 21 and a signal from a subcarrier or a phase-locked oscillator. The horizontal and vertical synchronization information is obtained from a composite synchronization signal, a blanking signal, a horizontal drive pulse signal, a vertical drive pulse signal, etc.

The above address control circuit 21 writes and reads a digital video signal to a predetermined scanning line (i.e., one horizontal line) address in the field memory circuit 14 based on scanning line position information obtained from horizontal and vertical synchronization information. Therefore, the address selection write circuit 13 and the memory read circuit 1
5. It is designed to control the 1H delay circuit 16.

In addition, in order to determine the order of digital video signals within one horizontal line, this address control circuit 21 uses horizontal synchronization and a sampling signal fixed to a constant phase to start A/D conversion of the A/D converter 12. It also controls the address selection write circuit 13, memory read circuit 15, and 1H delay circuit 16, and has the function of writing to a predetermined address in the field memory circuit 14 in one horizontal line in an orderly manner.

In this case, in order to order the address video signal within one horizontal line, the signal subcarrier, approximately
It is easy to use 3.58MHz. Alternatively, a phase lock type oscillation circuit may be used, which is controlled so that the phases at the beginning of each scanning line are the same.

The output of the D/A converter 18 is sent to a circuit 19 via a filter 24, and this circuit 19 receives an analog signal from the D/A converter 18 and a low-pass filter 25. This circuit obtains VDTL from the main video signal, and the low-pass filter 25 is almost the same as the low-pass filter 23.

Further, 20 is a VDTL output terminal, and the VDTL appearing at this output terminal 20 is then added to the main line video signal with a polarity that emphasizes the outline part through a VDTL amount control circuit.26 is a VDTL output terminal.
This is a delay line that requires phase alignment of the main video signal.

Next, the operation of the vertical contour signal generating device of the present invention configured as described above will be explained. The video signal input to the input terminal 10 becomes a direct video signal output, while passing through a low-pass filter 23.
The A/D converter 12 converts the signal into a digital video signal. Since this A/D converter 12 exists in the signal path only for obtaining VDTL, not in the path through which the main video signal passes, the sampling frequency is 4M.
Hz, that is, within the normal band of about 2 MHz.
It passes through a low-pass filter of ~2MHz.
In other words, this is sufficient as the sampling frequency of the A/D converter of the device of the present invention used for the purpose of obtaining only VDTL).

The resolution is determined by the ratio at which VDTL is mixed with the main video signal, but if this ratio is too large, the image will appear unnatural on the cathode ray tube, so it usually does not exceed about 10%, so it is ~
6 bits is sufficient (Currently, the majority of equipment that digitally processes main line video signals has a resolution of 8 bits. Therefore, VDTL contributes at a level of about 10% of the main line video signal.
The signal only requires a resolution of about 3 bits, so even if you allow a little margin, a resolution of 6 bits is sufficient.)

This A/D converter 12 (for example, 6 bits)
Digital data for one horizontal line that has become a digital video signal can be considered in a conceptual diagram as shown in FIG. That is, the video signal is sampled sequentially at a period determined by the sampling frequency, and all the sampled values are 6-bit digital video signals. The video signal within the horizontal retrace period (precisely, the signal during this period is only a synchronization signal, and there is no video component) is not A/D converted, which saves memory, so one horizontal line Of the period of approximately 63.5 microseconds, approximately 53 microseconds of the video signal in which the video signal exists may be converted to an A/D converter and stored in the field memory.

For example, if A/D conversion (6 bits) is performed after sequential sampling of a video signal for 53 microseconds at a sampling frequency of 4 MHz (sampling synchronization of 0.25 microseconds), n in FIG. 7 becomes 212. Therefore, the memory capacity of one horizontal line in this example is
212×6=1272 (bits).

Figure 7 shows the memory space for the digital video signal of the video signal obtained by one horizontal line, that is, one scanning line.The field memory concept shown in Figure 8 is when this is considered for the scanning line of one field. It is a diagram. m in this figure 8 is NTSC
In this method, the number of scanning lines is 525 in one frame (that is, 2 fields), so m = 262.5 lines, but in reality there is one vertical blanking period in one frame, so there are two vertical blanking periods. (equivalent to 40 scanning lines), if it is not necessary to store it in the memory after conversion by the A/D converter, m can be considered to be around 245 for one field, even considering the margin.

If you configure a memory with the above capacity, 1
The sampling frequency of the video signal for the field
It can be A/D converted and stored at 4MHz and 6-bit resolution. In other words, the address control circuit shown in FIG. 6 stores the vertical and horizontal synchronization information and the video signal from the sampling signal that determines sampling.For one horizontal line, the address control circuit in FIG. , and for one field, it is possible to provide a memory space such as that of FIG. 8, in which the memory spaces of FIG. 7 exactly overlap in the order determined by the order of the scan lines.

If you use this field memory circuit to write, store, and read digital video signals,
VDTL can be obtained between the main line video signal and the digital video signal of a different field. For example, consider a scanning line near the white center of a video signal obtained from an object as shown in FIG.

In Fig. 9, the first field of the scanning line that defines the video signal of the subject is indicated by a dashed line, and the second field is indicated by a dashed line.
Fields are shown with dashed lines. 1-1, 1-2, 1-
3 is the scanning line of the first field, 2-1, 2-2,
Reference numeral 2-3 indicates the scanning lines of the second field, and three scanning lines are shown for each central portion, six in total.

For example, the first field video signal is VDTL
When supplied to the generation circuit, the main line video signal becomes as shown in FIG. 10a'. In FIG. 10, the scanning lines 1-1, 1-2, and 1-3 correspond to those in FIG. 9, and the same applies hereafter.

Also, at this time, the digital video signal stored in the field memory in the previous field (ie, the second field) is read out with a phase as shown in FIG. 10b'. Although the waveform read out from the field memory is a digital signal and does not have the waveform shown in Figure 10b', the waveform in Figure 10b' is expressed digitally, so we used the waveform in Figure 10b' for consideration. It's easier to understand. Similarly, digital video signals will be shown below using analog video waveforms corresponding to the digital video signals. The waveform of FIG. 10b' is read out by the memory readout circuit 15 of FIG. 6, and after being delayed by 1H by the 1H delay circuit 16, the waveform of FIG.
Obtain a waveform like c′.

The adder circuit 17 inputs the digital video signals shown in FIGS. 10b' and 10c' to the memory readout circuits 15 and 1H.
A digital video signal is supplied from the delay circuit 16 and is a video signal as shown in FIG. 10d'. D/
The A converter 18 converts the video signal into an analog video signal (it goes without saying that after conversion to analog, the waveform becomes as shown in FIG. 10 d'). Further, the circuit 19 performs signal processing of d'+e'(e'=-2×a'),
The VDTL shown in FIG. 10f can be obtained.
This VDTL is superimposed on the main line video signal shown in FIG. 10a', resulting in a contour-corrected video as shown in FIG. 10g'. Fig. 10 f' is superimposed on the main video signal with a polarity that increases the level of video signals 1-2, and is controlled by the level control at this time.
It goes without saying that the amount of VDTL is controlled).

In this way, when obtaining VDTL, the digital video signal shown in FIG. 10b' is read out, and at the same time the digital video signal obtained by A/D converting the video signal shown in FIG. It is stored in the circuit 14. For example, 1 in Figure 9
If the digital video signals of scanning lines -2 and 2-1 use the same memory space in the field memory circuit 14, at the time when the digital video signals of 1-2 are written to the field memory circuit 14,
Since the digital video signal No. 1 has already been read out, there is no problem even if the memory contents are rewritten with the digital video signal No. 1-2 (as is clear in Fig. 10, the main video signal is 2-1 is being read out by 15).

Considering the second field in the same way, 2-
1, 2-2, 2-3, the main line video signal appears as a signal as shown in FIG. figure
A digital video signal of the video signal corresponding to "b" is read out by the memory readout circuit 15.The digital video signal read out by the memory readout circuit 15 is delayed by the 1H delay circuit 16, and as shown in FIG. A digital video signal such as video signal c'' is provided by the 1H delay circuit 16.

If this is processed in the same way as for the first field, a VDTL signal like f'' in Figure 11 will be obtained.F'' in Figure 11 has the opposite polarity to f' in Figure 10. If f' in Fig. 10 is superimposed on the video signal through the same path, a video signal as shown in g'' in Fig. 11 is obtained.

Reading and writing of the field memory circuit 14 in the second field is performed using scanning lines 1-2 and 2.
Since -1 uses the same memory room, it is necessary to write the data of 2-1 after 1-2 is read. This can be solved by providing the address selection write circuit 13 and the memory read circuit 15 with a simple 6-bit memory function that stores one sample of digital video signals.

That is, the memory readout circuit 15 reads digital data that is earlier in order by one sample, and
The memory reading circuit 15 may store the digital video signal in its own memory, and the address selection writing circuit 13 may write the digital video signal for one sample into the field memory circuit 14 immediately after the memory contents are read.

Figure 12 shows the VDTL obtained by this method. In this Figure 12, the dash-dotted line is obtained in the first field according to the above explanation.
In the part where VDTL changes from black to white, the level of the white side is increased to emphasize the outline. The dashed line is the second
The contours are emphasized by lowering the black video level using VDTL obtained from the field.

As can be understood from FIG. 12, the VDTL in the device of the present invention is half the thickness of the conventional device. This greatly reduces the visual problems caused by conventional equipment, and the thinnest
VDTL signals can be obtained (contour signals thinner than the scanning line cannot be obtained, so as in this invention,
The thinnest scanning line is one that emphasizes the white side and the other one that emphasizes the black side.) When VDTL is used as in the past, the inconsistency that degrades the delicateness of the screen is improved.

Also, according to FIG. 6, during A/D conversion of the video signal, two phases are locked with respect to the horizontal synchronization phase.
We considered a signal of about 4MHz, but subcarriers can also be used instead. For example, if we consider a subcarrier given by a sine wave whose phase is 0° or 180°,
It can be easily inferred from the standard broadcasting system that the first field and the second field are both in the same phase so that the video signal can be sampled. At this time, the sampling frequency is 3.58MHz, so the passband is approximately 1.7MHz, which is sufficient to obtain VDTL.

Furthermore, according to Figure 6, when obtaining VDTL,
Using Fig. 10 e' or Fig. 11 e'' as an analog, Fig. 10 d' or Fig. 11 of the D/A converter
For example, at this time, e' in Fig. 10 and e' in Fig. 11 are supplied as digital video signals immediately after A/D conversion, and
VDTL generation is performed at the digital video signal stage,
After this, D/A conversion may be performed.

In this case, there will be a phase lag in the main line video signal for A/D conversion of Figure 10 e' or Figure 11 e'', so the delay time of the main line video signal may be slightly longer. However, this degree of delay can be easily achieved using lumped constant circuits.

As described above, according to the vertical contour signal generating device of the present invention, since the 1H delay is not applied to the main line video signal, various characteristics such as frequency characteristics, linearity, stability, spurious, etc. of the main line video signal can be improved.
No deterioration occurs when VDTL occurs.

In addition, the main line video signal does not cause a vertical synchronization phase shift between the input and output of the VDTL generator due to a phase shift of one horizontal line caused by the main line video signal passing through the 1H delay circuit. .

Furthermore, by obtaining the thinnest VDTL determined by the number of scanning lines stipulated by the broadcasting system, it is possible to superimpose VDTL on the main video signal without impairing the delicacy of the video signal. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a conventional vertical contour signal generating device, FIG. 2 is a diagram showing an example of a subject,
3a to 3f are diagrams illustrating video processing when VDTL is generated by a conventional vertical contour signal generating device,
4 and 5 are diagrams showing the relationship between scanning lines and VDTL of a conventional vertical contour signal generating device, FIG. 6 is a block diagram showing the configuration of an embodiment of the vertical contour signal generating device of the present invention, and FIG. 7 and 8 are diagrams showing the concept of the memory space of the field memory circuit of the vertical contour signal generator of the present invention, respectively.
The figures are diagrams showing the scanning lines of each field in the vertical contour signal generating device of the present invention.
Figure 0g' and Figures 11a'' to 11g'' respectively show the vertical contour signal generator of the present invention.
Signal waveform diagram showing video processing when VDTL occurs,
FIG. 12 is a diagram showing how VDTL is generated by the vertical contour signal generating device of the present invention. 10...Input end, 11, 20...Output end, 12
...A/D converter, 13...Address selection write circuit, 14...Field memory circuit, 15...
...Memory read circuit, 16...1H delay circuit,
17...Addition circuit, 18...D/A converter, 19
...Circuit for obtaining VDTL, 21...Address control circuit, 23, 25...Low pass filter, 24...
...Filter, 26...Delay line for phase matching.

Claims (1)

[Claims] 1 A main line video signal is introduced, a means for converting it into a digital video signal after performing band limiting to make the pass band narrower than the frequency band of the main line video signal, and a means for converting this digital video signal to horizontal and vertical synchronization information and a constant phase. A field memory circuit that can be written and read using a maintained sampling signal and stores the digital video signal for one field or more, and means for delaying the digital video signal read from the memory circuit by one horizontal scanning period. , means for adding the delayed digital video signal and the digital video signal from the memory circuit, means for converting the added digital video signal into an analog signal, and the analog video signal and the main video signal are introduced. 1. A vertical contour signal generating device comprising a circuit for obtaining a vertical contour video signal from video signals of two scanning lines of different fields adjacent to a predetermined scanning line.