JPH023321B2 - - Google Patents
Info
- Publication number
- JPH023321B2 JPH023321B2 JP7536884A JP7536884A JPH023321B2 JP H023321 B2 JPH023321 B2 JP H023321B2 JP 7536884 A JP7536884 A JP 7536884A JP 7536884 A JP7536884 A JP 7536884A JP H023321 B2 JPH023321 B2 JP H023321B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- resistor
- terminal
- current
- current mirror
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/32—Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
Landscapes
- Amplifiers (AREA)
- Networks Using Active Elements (AREA)
Description
【発明の詳細な説明】
技術分野
本発明は、カレントミラー回路を用いた回路素
子数の少ない平衡不平衡変換回路に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a balanced/unbalanced conversion circuit using a current mirror circuit and having a small number of circuit elements.
従来の技術
カレントミラー回路を用いて、平衡電圧信号を
不平衡電流信号に変換する回路を構成する場合、
従来より第１図に示すものがよく用いられる。第
１図において、CMi（ｉ＝１〜３、以下同様）は、
カレントミラー回路であり、これらの回路はそれ
ぞれ入力ダイオードDi、出力トランジスタQi、
および抵抗Ri１とRi２とでもつて構成される。
またＩ１とＩ２は平衡電圧信号入力端子、Ｏは不
平衡電流信号出力端子、Ｒ１とＲ２は低抗、VC
は正電圧源である。Prior Art When configuring a circuit that converts a balanced voltage signal into an unbalanced current signal using a current mirror circuit,
Conventionally, the one shown in FIG. 1 has been often used. In Figure 1, CMi (i = 1 to 3, the same applies hereinafter) is
They are current mirror circuits, and each of these circuits has an input diode Di, an output transistor Qi,
It is also composed of resistors Ri1 and Ri2.
Also, I1 and I2 are balanced voltage signal input terminals, O is unbalanced current signal output terminal, R1 and R2 are low resistance, VC
is a positive voltage source.
第１図において、端子Ｉ１とＩ２における入力
信号電圧をそれぞれV1＋v1，V2＋v2とする。
（大文字が直流バイアス分，小文字が交流信号分
とする。以下同様）また、カレントミラーCMiの
電流増幅率をmiとする。このときCMiの出力電
流ICiは、それぞれ次式で与えられる。 In FIG. 1, input signal voltages at terminals I1 and I2 are assumed to be V1+v1 and V2+v2, respectively.
(The uppercase letters represent the DC bias component, and the lowercase letters represent the AC signal component. The same applies hereinafter.) Also, let mi be the current amplification factor of the current mirror CMi. At this time, the output current ICi of CMi is given by the following equations.
IC1＝m1・VC−（V1＋v1）−VD1／R1＋R11
IC2＝m2・（V2＋v2）−VD2／R2＋R21
IC3＝m3・IC2
ただし、VD１とVD２はそれぞれダイオード
Ｄ１，Ｄ２の導通電圧である。 IC1=m1・VC−(V1+v1)−VD1/R1+R11 IC2=m2・(V2+v2)−VD2/R2+R21 IC3=m3・IC2 However, VD1 and VD2 are conduction voltages of diodes D1 and D2, respectively.
従つて、ｍ３＝１，ｍ１＝ｍ２，Ｒ１＝Ｒ２，
Ｒ１１＝Ｒ２１，と設定することにより、信号出
力端子Ｏにおける電流出力信号IOは、
IO＝IC1＋IC3＝m1・（v2−v1）＋（VC＋V2
−V1−VD1−VD2）／R1＋R11
となり、（v2−v1）に比例する交流信号を得る。
すなわち、不平衡信号が得られる。（実際には、
図の外部でもつて交流分のみをとり出す回路を別
途設ける。）このように、従来例では平衡電圧信
号の電流信号に変換するのに２個、２つの電流信
号を合成して不平衡電流信号を作成するために１
個の計３個のカレントミラー回路が必要であつ
た。 Therefore, m3=1, m1=m2, R1=R2,
By setting R11=R21, the current output signal IO at the signal output terminal O is IO=IC1+IC3=m1・(v2−v1)+(VC+V2
−V1−VD1−VD2)/R1+R11, and obtain an AC signal proportional to (v2−v1).
That is, an unbalanced signal is obtained. (in fact,
A separate circuit is provided outside the diagram to take out only the AC component. ) In this way, in the conventional example, two signals are used to convert a balanced voltage signal into a current signal, and one signal is used to synthesize two current signals to create an unbalanced current signal.
A total of three current mirror circuits were required.
解決すべき問題点
前記のごとく、従来の平衡不平衡変換回路は、
計３個のカレントミラー回路が必要であつて、回
路が複雑で素子数が多くなるという欠点を有する
もので、本発明はその問題を解決しようとするも
のである。Problems to be solved As mentioned above, the conventional balanced/unbalanced conversion circuit has
A total of three current mirror circuits are required, making the circuit complicated and requiring a large number of elements. This invention is an attempt to solve this problem.
問題点を解決するための手段
本発明は２個の電流信号の合成を、平衡電圧信
号を電流信号に変換する回路の入力側で行なうよ
うにし、電流合成用カレントミラー回路を削除す
るようにしたものであつて、以下に実施例を示し
これにより本発明を詳しく説明する。Means for Solving the Problems The present invention combines two current signals on the input side of a circuit that converts a balanced voltage signal into a current signal, and eliminates the current mirror circuit for current synthesis. The present invention will be explained in detail with reference to Examples below.
実施例
第２図は本発明の実施例であつて、Ｑ４とＱ５
はトランジスタ、Ｒ３〜Ｒ５は抵抗である。（以
下の説明文中では第１図に用いた記号等は説明な
しに流用する。）
第２図においてトランジスタＱ４のベース電圧
VB４は次式となる。Embodiment FIG. 2 shows an embodiment of the present invention, in which Q4 and Q5
is a transistor, and R3 to R5 are resistors. (In the following explanatory text, the symbols used in Figure 1 will be used without explanation.) In Figure 2, the base voltage of transistor Q4
VB4 becomes the following formula.
VB4＝R3（V2＋v2）／R2＋R3
一方、CM１の出力電流によるＲ４の電圧降下
分VR４は次式となる。 VB4=R3(V2+v2)/R2+R3 On the other hand, the voltage drop VR4 of R4 due to the output current of CM1 is expressed by the following equation.
VR4＝｛m1・VC−（V1＋v1）−VD1／R1＋R11｝×R4
一方、出力端子Ｏにおける電流出力信号IO′は
次式となる。 VR4={m1·VC−(V1+v1)−VD1/R1+R11}×R4 On the other hand, the current output signal IO′ at the output terminal O is given by the following equation.
IO′＝VB4＋VR4＋VBE4−VBE5／R5
ここで、VBE４とVBE５はそれぞれトランジ
スタＱ４とＱ５のベース・エミツタ間導通電圧で
ある。 IO'=VB4+VR4+VBE4-VBE5/R5 Here, VBE4 and VBE5 are the base-emitter conduction voltages of transistors Q4 and Q5, respectively.
従つて、ｍ１＝１，Ｒ１＝Ｒ２，Ｒ１１＝Ｒ３
＝Ｒ４と設定することにより、
IO′＝｛R11｛（v2−v1）＋（VC＋V2−V1
−VD1）｝／R1＋R11＋VBE4−VBE5｝／R5
となり、ｖ２−ｖ１に比例する交流信号を得る。
すなわち不平衡信号が得られる。 Therefore, m1=1, R1=R2, R11=R3
By setting = R4, IO′ = {R11{(v2−v1)+(VC+V2−V1)
-VD1)}/R1+R11+VBE4-VBE5}/R5, and an AC signal proportional to v2-v1 is obtained.
That is, an unbalanced signal is obtained.
このように本発明によれば電流合成用のカレン
トミラー回路が不用となる。 As described above, according to the present invention, a current mirror circuit for current synthesis becomes unnecessary.
また、以上の説明ではVBEやVDが交流信号分
ｖ１，ｖ２で変化する分や、トランジスタのベー
ス電流による誤差分を無視したが通常の用途では
これらの誤差分を無視しても差し支えない。 Furthermore, in the above explanation, the changes in VBE and VD due to the alternating current signals v1 and v2, and the error caused by the base current of the transistor were ignored, but in normal applications, these errors can be ignored.
また、本発明がバイポーラ・トランジスタにと
どまらず、MOSトランジスタに対しても有効で
あることは自明である。 Furthermore, it is obvious that the present invention is effective not only for bipolar transistors but also for MOS transistors.
発明の効果
以上説明したように、本発明による平衡不平衡
信号変換回路は、電流合成用カレントミラー回路
が不用となり、従来よりも少ない素子数で構成で
きるという利点がある。Effects of the Invention As explained above, the balanced/unbalanced signal conversion circuit according to the present invention has the advantage that it does not require a current mirror circuit for current synthesis and can be configured with a smaller number of elements than the conventional circuit.
第１図は従来の平衡不平衡変換回路の一例の回
路図、第２図は本発明の平衡不平衡変換回路の一
実施例の回路図である。
CM１〜CM３…カレントミラー回路、Ｉ１，
Ｉ２，Ｏ…端子、VC…定電圧源、Ｒ１〜Ｒ５，
Ｒ１１，Ｒ１２，Ｒ２１，Ｒ２２，Ｒ３１，Ｒ３
２…抵抗、Ｑ１〜Ｑ５…トランジスタ、Ｄ１〜Ｄ
３…ダイオード。
FIG. 1 is a circuit diagram of an example of a conventional balanced/unbalanced conversion circuit, and FIG. 2 is a circuit diagram of an embodiment of the balanced/unbalanced conversion circuit of the present invention. CM1 to CM3...Current mirror circuit, I1,
I2, O...terminal, VC...constant voltage source, R1~R5,
R11, R12, R21, R22, R31, R3
2...Resistor, Q1-Q5...Transistor, D1-D
3...Diode.
Claims (1)
回路において、第１のトランジスタと、第１のト
ランジスタとは異なる導電タイプの第２のトラン
ジスタと、カレントミラー回路と、第１〜第５の
５個の抵抗とを具備し、前記第１と第２の抵抗の
第１端をそれぞれ平衡電圧信号入力端子とし、第
１の抵抗の第２端を前記カレントミラー回路の入
力端子に接続し、第２の抵抗の第２端を第１のト
ランジスタの第３端子であるベース又はゲートと
第３の抵抗の第１端との接続点に接続し、前記カ
レントミラー回路の出力端子を第２のトランジス
タの第３端子であるベース又はゲートと第４の抵
抗の第１端との接続点に接続し、第４の抵抗の第
２端は第１のトランジスタの第１の端子に接続
し、第５の抵抗の第１端を第２のトランジスタの
第１の端子に接続し、第３の抵抗の第２端と第５
の抵抗の第２端と第１のトランジスタの第２の端
子を定電位点に接続し、第２のトランジスタの第
２の端子を不平衡電流信号出力端子とすることを
特徴とする平衡不平衡変換回路。1. In a balanced unbalanced conversion circuit using a current mirror circuit, a first transistor, a second transistor of a conductivity type different from the first transistor, a current mirror circuit, and five transistors, first to fifth. a resistor, first ends of the first and second resistors are each used as a balanced voltage signal input terminal, a second end of the first resistor is connected to an input terminal of the current mirror circuit, and a second resistor is connected to the input terminal of the current mirror circuit. The second end of the resistor is connected to the connection point between the base or gate, which is the third terminal of the first transistor, and the first end of the third resistor, and the output terminal of the current mirror circuit is connected to the third terminal of the second transistor. The second end of the fourth resistor is connected to the first terminal of the first transistor, and the fifth resistor The first end of the resistor is connected to the first terminal of the second transistor, and the second end of the third resistor and the fifth resistor are connected to the first terminal of the second transistor.
The second end of the resistor and the second terminal of the first transistor are connected to a constant potential point, and the second terminal of the second transistor is used as an unbalanced current signal output terminal. conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7536884A JPS60218914A (en) | 1984-04-14 | 1984-04-14 | Balance and unbalance conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7536884A JPS60218914A (en) | 1984-04-14 | 1984-04-14 | Balance and unbalance conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60218914A JPS60218914A (en) | 1985-11-01 |
| JPH023321B2 true JPH023321B2 (en) | 1990-01-23 |
Family
ID=13574204
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7536884A Granted JPS60218914A (en) | 1984-04-14 | 1984-04-14 | Balance and unbalance conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60218914A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009284245A (en) * | 2008-05-22 | 2009-12-03 | Mitsubishi Electric Corp | Active balun circuit |
-
1984
- 1984-04-14 JP JP7536884A patent/JPS60218914A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60218914A (en) | 1985-11-01 |
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