JPH023339B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to variable delay equalizers;
More specifically, it relates to variable delay equalizers that utilize transversal filter theory.

FIG. 1 is a conceptual diagram showing an example of TDMA communication which is the background of this invention. TDMA communications are used, for example, in satellite communications, and such satellite communications systems include a plurality of earth stations ES, ES′, . . . and a common communications satellite CS. The earth station ES includes a transmitter TRA and a receiver REA. The signal modulated by the modulator MOD included in the transmitter TRA is sent to the equalizer EQL.
and is sent from the antenna AE to the antenna AS of the communication satellite CS via the transmitter TR. The signal is frequency converted within the satellite and transmitted to other earth stations.
Sent to ES′. Similarly, a signal from another earth station ES' is received by the antenna AE of the earth station ES via the communication satellite CS, and the received signal is given to the receiving device REA. The receiving device REA is demodulated by a demodulator DEM through a receiver RE and an equalizer EQL. The transmitter TR and receiver RE of the earth station ES and
It is known that the receiving and transmitting systems of communication satellites each produce amplitude distortion and/or group delay distortion. In particular, the high-output amplifier (not shown) included in the communication satellite CS is used in a highly saturated state due to size, cost, stability, and other reasons. Therefore, in this high-power amplifier, AM
-PM conversion occurs, resulting in a phase change as shown by line A in FIG. Note that in FIG. 2, line B indicates the output level. The above-mentioned phase change results in group delay distortion.

These amplitude distortions and group delay distortions are divided into the transmitting system and the receiving system, and the equalizer EQL included in the transmitting device TRA and the equalizer included in the receiving device REA are used.
EQL performs amplitude equalization or delay amount equalization. Conventionally, such an equalizer EQL is
Generally, a fixed amplitude equalizer, as shown in FIG.
FAE, fixed delay equalizer FDE and variable equalizer
It consists of ME. Depending on the amount of actual amplitude distortion or group delay distortion, the fixed amplitude equalizer FAE
Alternatively, one or both of the fixed delay equalizers FDE may be omitted.

In the TDMA communication system that forms the background of this invention, once operation begins, test signals are transmitted and received to measure the above-mentioned amplitude characteristics and group delay characteristics, thereby measuring the optimal equalization amount. is impossible. This is because such a communication system is performed on a time-division basis, and therefore the time that one earth station occupies the line is extremely short.
Therefore, when a new earth station joins such a communications satellite system, it is necessary to search for the optimal point where the amplitude distortion and group delay distortion are minimum and, therefore, the BER (bit error rate) is minimum. For this purpose, a variable equalizer ME as shown in FIG. 3 is used.

FIG. 4 is a circuit diagram showing an example of a conventional variable equalizer ME, which is the background of the present invention. In FIG. 4, an input signal applied from an input terminal 1 is distributed by a distributor 2. In FIG. The signal divider 2 divides the input signal into three signals of the same level using, for example, a known hybrid circuit. A delay line 3 having a delay amount T is inserted into one signal path of the three signals, a delay line 4 having a delay amount 2T is inserted into the other one signal path,
A polarity inverter 5 is inserted in the remaining one path. The polarity inverter 5 is composed of a known transformer or transistor, and converts the applied signal into
180° phase shift. The signal from the delay line 4 and the signal from the polarity inverter 5 are combined by a combiner 6 and then applied to a variable coefficient loading circuit 7. The variable coefficient loading circuit 7 is composed of a double-balanced mixer or the like having a polarity inversion function, and the output signal therefrom is combined with the output signal from the delay line 3 (main signal of the delay section) in a combiner 8. .

Here, it is assumed that there is no signal attenuation except for the variable coefficient loading circuit 7, and that there is no time delay except for the delay lines 3 and 4, and this main signal delay is the reference (set to 0).
Then, the output signal B(ω) obtained at the output terminal 9 is
is expressed by the following equation (1).

B(ω)=cosωt−lcosω(t+T) +lcosω(t−T) =√(1+2 ² )−2 ² 2 ×cos{ωt−π/2 +tan ^-1 (1/2lsinωT)} …(1) This output The characteristic G B (ω) of the amplitude of the signal _B (ω) with respect to the frequency and the characteristic τ _B (ω) of the amount of delay with respect to the frequency are given by the following equations (2) and (3), respectively.

G _B (ω)=20log{√(1+2 ² )−2 ² 2
}
…(2) τ _B (ω)=−2lT×cosωT/(1+2l ² )−2l ² cos2ω
T...(3) However, ω is the angular frequency, and ω=2π (is the frequency). This amplitude characteristic G _B (ω) and delay characteristic τ _B
(ω), when the coefficient l>0, the change characteristic is the fifth
As shown in the figure. Figure 5A shows the amplitude characteristics;
Figure B shows the delay characteristics, which change in the direction of the arrow when the coefficient l is increased. That is,
As can be seen from FIG. 5, in the example of FIG. 4, if the coefficient l is changed in the coefficient loading circuit 7, the amount of delay also changes. However, even in the example shown in FIG. 4, not only the amount of delay but also the amplitude changes as the coefficient l changes, making it extremely difficult to use it as a variable equalizer in a TDMA communication system. .

Therefore, the purpose of this invention is to e.g.
It is an object of the present invention to provide a variable delay equalizer that can be effectively used in a TDMA communication system and has a very small change in amplitude even when the amount of delay is changed.

To summarize, the present invention combines a signal that is advanced by a certain period of time and a signal that is delayed by a certain period of time when a signal that is delayed by a certain period of time with respect to an input signal is combined with different polarities, and a first coefficient is added as a weight. It includes a delay unit, and an amplitude correction unit that combines a second predetermined time advance signal and a delayed signal based on a signal delayed by a predetermined time with respect to the input signal, and adds a second coefficient as a weight. By connecting the delay section and the amplitude correction section in cascade, and interlocking them so that the weighting coefficient value in the amplitude correction section is the square of the weighting coefficient value of the delay section, the amplitude distortion generated in the delay line can be reduced to an amplitude This is a variable delay equalizer that performs correction in a correction section.

The above objects and other objects and features of the invention will become more apparent from the following detailed description with reference to the drawings.

Figure 6 shows TDMA as an embodiment of this invention.
1 is a block diagram showing a variable delay equalizer used in a communication system. FIG. In Figure 6, input terminal 1
The signal from the delay section 10 and the amplitude correction section 20
is applied to the output terminal 9 through. If this variable delay equalizer is used in a TDMA communication system as shown in FIG. 1, when included in a transmission system, input terminal 1 is connected to modulator MOD and output terminal 9 is connected to transmitter TR. , if included in a receiving system, the input terminal 1 would be connected to the receiver RE and the output terminal 9 would be connected to the demodulator DEM.

In this FIG. 6, the configuration of the delay section 10 is as follows.
Since it is the same as the variable equalizer ME in the figure, its explanation will be omitted. On the other hand, the amplitude correction section 20 connected in cascade to the delay section 10 includes a distributor 12 that distributes the input signal 3, a delay line 13 and a delay line 1 that delay two signals of the distributed output by 2T and 4T, respectively.
4. A combiner 16 that combines the signal that has passed through the delay line 14 and the undelayed signal, and two coefficient loads that are the same as the coefficient load circuits of the delay section connected in series and that add a coefficient l to each of the combined outputs. circuit 1
7a, 17b (these two coefficient loading circuits load a second coefficient set to the square of the first coefficient), a fixed attenuator 15 that fixedly attenuates the output of this coefficient loading circuit 17b, and this It is comprised of a combiner 18 that combines the output signal of the fixed attenuator 15 and the signal that has passed through the delay line 13 and outputs it to the output terminal 9.

Note that the coefficient loading circuit 17 of this amplitude correction section 20
The settings of coefficients l and l (i.e. l ² ) of a and 17b are as follows:
The amplitude correction section 20 is configured to be set in conjunction with the setting of the coefficient l of the coefficient loading circuit 7 of the delay section 10, that is, when l is set in the delay section 10, the amplitude correction section ²⁰ is automatically set to l2.

Here, the principle and operation of the amplitude correction section 20 shown in FIG. 6 will be explained using a known variable amplitude equalizer. FIG. 7 is a circuit diagram showing an example.
Compared to the delay section 10 shown in the figure, this delay section 10 is substantially the same as the delay section 10 except that the polarity inverter 5 is omitted. That is, the signal input from the input terminal 1 is distributed by the distributor 2. The signal passing through the delay line 4 is combined with the signal not passing through the delay line by a combiner 6, and is applied to a combiner 8 through a variable coefficient loading circuit 7 having a coefficient k. In this way, in the synthesizer 8, the signal passing through the delay line 3 (the main signal of the amplitude correction section) and the signal passing through the variable coefficient loading circuit 7 are combined and outputted to the output terminal 9'.

Here, assuming that there is no signal attenuation in areas other than the coefficient loading circuit 7, and that there is no time delay in areas other than the delay lines 3 and 4, and that this main signal delay is set to 0 as a reference, the output signal derived to the output terminal 9' A(ω) is given by the following equation (4).

A(ω)=cosωt+kcosω(t+T) +kcosω(t-T) =(1+2kcosωT)cosωt...(4) Also, the frequency characteristic G _A (ω) of the amplitude of this output signal A(ω) is expressed by the following equation (5) is given by

G _A (ω)=20log(1+2kcosωT) (5) However, the delay characteristic τ _A (ω) is flat.
The variation characteristic of this amplitude characteristic G _A (ω) with respect to the coefficient k is shown in FIG. If the coefficient k is increased, the amplitude changes in the direction of the arrow. That is, in FIG. 7, by changing the coefficient k of the variable coefficient loading circuit 7, a variable amplitude equalizer in which only the amplitude changes without changing the amount of delay can be obtained.

Further, as shown in FIG. 8, the amplitude repetition period of this variable amplitude equalizer is 1/T, while the amplitude repetition period of the delay unit 10, that is, the delay equalizer of FIG. 4 is as shown in FIG. As shown in A, it is 1/2T.

Therefore, if the repetition period of the amplitude characteristic of the amplitude correction section 20 is halved to be the same as the period of the delay section 10, and the amplitude polarity is reversed, the amplitude distortion generated in the delay section 10 can be reduced by the amplitude correction section 20. Understand that it can be corrected by

Next, the operation shown in FIG. 6 will be explained. In FIG. 6, the delay lines 3 and 4 of the delay section 10 have a delay amount of T and 2T, respectively, and the delay lines 13 and 14 of the amplitude correction section 20 have a delay amount of 2T and 4T, respectively, which is twice the delay amount of the delay section 10. It is assumed that the delay is set.

In this state, the coefficient loading circuits 7, 17a,
17b and the fixed attenuator 15, there is no signal attenuation, and there is no time delay except for the delay line, and the coefficient of the coefficient loading circuit 7 is l, the coefficient loading circuit 17a,
17b and the fixed attenuator 15 is k, the output signals G _B (ω) and G _A (ω) of the delay section 10 and the amplitude correction section 20 are expressed by the above-mentioned equations (2) and (5). It is expressed as In this case, since the delay section 10 and the amplitude correction section 20 are connected in cascade, the overall amplitude characteristic G _C (ω) is the sum of these amplitude characteristics and is expressed by the following formula.

G _C (ω)=G _B (ω)+G _A (ω) …(6) =20log(1+2kcosωT)√(1+2 ² )−2 ²
2=20log√ [(1+2 ² )+{4(1+2 ² )−2 ² }
2 + {4 ² (1+2 ² )−8 ² } ² 2−8 ^{2 2
3} 2]...(7) Here, assuming that the coefficient loading circuits 7, 17a, and 17b are interlocked with each other and have the same coefficient l, and the fixed attenuator 15 has an attenuation of 6 dB, that is, a coefficient of 0.5, k=0.5× l×l=l ² /2. Substituting this into equation (7), G _C (ω) = 20log√ [(1 + 2 ² ) + 4 ⁴ 2
+ + (2 ⁶ −3 ⁴ ) ² 2−2 ⁶ cos ³ 2ωT〕…
(8) becomes. Compared to the conventional equation (2), this equation (8) shows that l<
The term whose amplitude varies with frequency in the range of 1/√2 has become very small.

On the other hand, the delay characteristic τ _C (ω) in this case is
0 and the amplitude correction section 20, but since the amplitude correction section 20 has no delay characteristic, the overall delay characteristic τ _C
(ω) becomes τ _B (ω) shown in equation (3) above. That is, τ _C (ω) = τ _B (ω).

FIG. 9 shows the amplitude characteristics in this sixth embodiment.
It shows G _C (ω) and the delay characteristic τ _C (ω). Note that Fig. 9 shows the change when l>0, but when l<0, the sign of τ _B (ω), that is, τ _C (ω) in equation (3) is reversed, and the delay amount becomes The advance and lag are opposite to the reference value. Also, in equation (8)
G _C (ω) has the same value even if l<0 if the absolute values of l are equal. In other words, when l changes from the + side to the - side, the delay changes as shown in the arrow in Figure 10, but the amplitude characteristic G _C (ω)
simply repeats the characteristic of FIG. 9A.

From the above explanation, it will be understood that the embodiment of FIG. 6 can change only the delay amount without changing the amplitude. Therefore, if such a variable delay equalizer is used as a variable equalizer in a TDMA communication system, it will be possible to independently equalize only the degradation in BER due to group delay distortion, which will improve the performance of conventional Compared to a case where the amplitude and delay amount change together, as in the case of a digital camera, the operation to find the optimum point can be performed much more easily.

In addition, in the above embodiment, the coefficient loading circuit 7,
Although 17a and 17b are configured with a double-balanced mixer or the like that includes polarity inversion, if the variable range is limited depending on the application, they may also be configured with a variable attenuator or the like that does not include polarity inversion. Further, the polarity inverter 5 is not limited to a 180° phase shifter, but may also be a 180° combiner, a divider, or a 90° combiner/divider. For example, by arranging a 180° combiner in the combiner 6, the functions of the polarity inverter 5 and the combiner 6 may be provided, and similarly, the input side of the combiner 6 and the output side of the divider 2 are respectively provided.
A 90° combiner or distributor may also be used.

Further, the coefficient loading circuits 7, 17a, 17b and the fixed attenuator 15 may be inserted at any position as long as the amplitude of the signals input to the combiners 8, 18 is set at a constant ratio. often,
For example, the fixed attenuator 15 is connected to the distributor 12 and the combiner 1.
It is also possible to provide each between 6 and 6.

11 to 14 show other embodiments of the present invention.

In the embodiment shown in FIG. 6, the delay section 10 and the amplitude correction section 20
However, as shown in FIG. 11, it is also possible to connect two stages or two stages in cascade, and to interlock the coefficient loading circuits.

Further, as shown in FIG. 12, an n-stage delay section 1
By setting the fixed attenuator 15 in the amplitude correction section 20 to a value that minimizes the amplitude characteristic, it is possible to compensate for the motion of the coefficient loading circuit. Note that although FIG. 12 shows a one-stage amplitude correction section 20, an m-stage amplitude correction section 2 is shown.
0, the same is true by simply setting the value of the fixed attenuator 15. The embodiments shown in FIGS. 11 and 12 are also effective as means for widening the variable range of the variable delay equalizer.

In the embodiment of FIG. 6, the delay line is provided after the input signal is distributed, but it is also possible to provide the distributors 2, 12 and the delay lines 3, 13 alternately, as shown in FIG. Also, as shown in FIG. 14, the delay line 3,
4, 13, 14, the polarity inverter 5, and the combiner 6 may be configured in two stages or in n stages. here 3
1 and 32 are fixed attenuators, 32 is set to the square of 31, and 33 to 34 are delay lines.

As described above, according to the present invention, the delay section and the amplitude correction section are connected in cascade, and the amplitude distortion generated in the delay section is corrected by the amplitude correction section, so that the desired delay can be achieved without changing the amplitude characteristics. In addition, by linking the coefficient loading circuits of the delay section and amplitude correction section, it is possible to easily adjust the delay amount and obtain a highly accurate variable delay equalizer at a lower cost. .

[Brief explanation of drawings]

Figure 1 is a conceptual diagram showing the concept of a TDMA satellite communication system, Figure 2 is a characteristic diagram showing the characteristics of a high-power amplifier included in a communication satellite, and Figure 3 is an example of an equalizer used in a TDMA satellite communication system. 4 is a circuit diagram showing an example of a conventional variable delay equalizer, FIG. 5 is a characteristic diagram showing the amplitude and delay characteristics of FIG. 4, and FIG. 6 is an embodiment of the present invention. 7 is a circuit diagram showing an example of a variable amplitude equalizer, FIG. 8 is a characteristic diagram showing the amplitude characteristics of FIG. 7, and FIGS. 9 and 10 are FIG. 6 is a characteristic diagram showing the amplitude and delay characteristics of the embodiment, and FIGS. 11 to 14 are block diagrams (circuit diagrams) showing other embodiments of the present invention. In the figure, 2 and 12 are distributors, 3, 4, 13, 14
is a delay line, 5 is a polarity inverter, 6, 16, 8, 18
is a synthesizer, 7, 17a, 17b are coefficient loading circuits,
10 is a delay section, and 20 is an amplitude correction section. In addition,
In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A synthesizer that synthesizes signals obtained by shifting the phase of the input signal by T hours in the leading direction and in the delay direction, respectively, and inverting the polarity of one of the signals based on a signal obtained by delaying the input signal by T hours as a reference, and the output signal of this synthesizer a coefficient loading circuit for adding a first coefficient as a load; a synthesizer for synthesizing the output signal of the coefficient loading circuit and a signal obtained by delaying the input signal by a time T;
A delay unit that controls the amount of delay by changing the coefficient of , and a signal that is delayed by 2T time from the output signal of this delay unit as a reference, and synthesizes each signal whose phase is shifted by 2T time in the leading direction and the delay direction respectively. a combiner, a coefficient loading circuit that adds a second coefficient set to the square of the first coefficient to the output signal of the combiner, a signal obtained by fixedly attenuating the output signal of the coefficient loading circuit, and the delay section. , and an amplitude correction section that controls the amplitude by changing the second coefficient, and the delay section and the amplitude correction section are connected in cascade. A variable delay equalizer characterized in that the coefficient loading circuits of the delay section and the amplitude correction section are interlocked with each other, and the first and second coefficients are loaded.