JPH0234449B2 - - Google Patents
Info
- Publication number
- JPH0234449B2 JPH0234449B2 JP57225168A JP22516882A JPH0234449B2 JP H0234449 B2 JPH0234449 B2 JP H0234449B2 JP 57225168 A JP57225168 A JP 57225168A JP 22516882 A JP22516882 A JP 22516882A JP H0234449 B2 JPH0234449 B2 JP H0234449B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrophoresis
- insulation
- electrodes
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 35
- 239000000919 ceramic Substances 0.000 claims description 26
- 238000001962 electrophoresis Methods 0.000 claims description 11
- 239000000843 powder Substances 0.000 claims description 10
- 239000000725 suspension Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 description 10
- 239000002002 slurry Substances 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000009422 external insulation Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- 239000003985 ceramic capacitor Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 235000019441 ethanol Nutrition 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- BBKFSSMUWOMYPI-UHFFFAOYSA-N gold palladium Chemical compound [Pd].[Au] BBKFSSMUWOMYPI-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 230000003449 preventive effect Effects 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
- Thermistors And Varistors (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Ceramic Capacitors (AREA)
- Insulating Of Coils (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
【発明の詳細な説明】
本発明は積層セラミツク電子部品の絶縁方法に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for insulating laminated ceramic electronic components.
積層セラミツク電子部品は積層セラミツクコン
デンサ、積層セラミツクバリスタ、多層セラミツ
ク基板、積層セラミツクインダクタ、積層セラミ
ツク電歪素子、積層セラミツク圧電素子、積層型
セラミツクセンサーなど数多くのもので実用化さ
れている。 Multilayer ceramic electronic components have been put to practical use in many types, including multilayer ceramic capacitors, multilayer ceramic varistors, multilayer ceramic substrates, multilayer ceramic inductors, multilayer ceramic electrostrictive elements, multilayer ceramic piezoelectric elements, and multilayer ceramic sensors.
これらの積層セラミツク電子部品は、いずれも
小型であるため、外部に電極を取出すための端子
電極相互の間隔が小さくなり、端子電極間の絶縁
性、信頼性を確保することがむずかしかつた。積
層セラミツク部品では、技術上、コスト上の問題
から一般に端子電極として、銀又は金パラジウム
合金を焼付けていた。しかしながら、銀は水の存
在の下でマイグレーシヨンを起こすため特に耐湿
負荷試験などにおける信頼性を著しく低下させて
いた。 Since these laminated ceramic electronic components are all small, the distance between the terminal electrodes for taking out the electrodes to the outside is small, making it difficult to ensure insulation and reliability between the terminal electrodes. In laminated ceramic parts, silver or gold-palladium alloys have generally been baked as terminal electrodes due to technical and cost considerations. However, since silver undergoes migration in the presence of water, its reliability, especially in humidity load tests, has been significantly reduced.
この問題を解決するため、パラジウムの含有量
の多い銀パラジウム合金を使用したり、銀電極の
上をメツキなどの方法によつて、ハンダ、ニツケ
ル、銅などの卑金属でコーテイングしたり、端子
電極として無電解メツキなどの方法によつて銅や
ニツケルをつける等の研究、開発が行われてい
る。 To solve this problem, silver-palladium alloys with high palladium content are used, silver electrodes are coated with base metals such as solder, nickel, copper, etc. by plating, or terminal electrodes are used. Research and development is being carried out to attach copper or nickel using methods such as electroless plating.
しかしながら、これらのいずれの方法も、その
効果がなかつたり、製造プロセスが複雑になつた
り、使用できるセラミツク材料に制約があるなど
の問題があり、コストも高くなるなど実用化が進
まない状況にある。 However, all of these methods have problems such as ineffectiveness, complicated manufacturing processes, and restrictions on the ceramic materials that can be used, and high costs, which prevent them from being put into practical use. .
そこでリードの付いている積層セラミツク電子
部品では環境変化による信頼性を確保するための
外部絶縁の方法としては、ハーメチツクシールが
実用化されており、非常に優れた絶縁方法となつ
ているが、これは形状が大きくなり、しかもコス
トが著しく高くなることから、特に信頼性が要求
される部分に限定して使用せざるをえない状態で
ある。 Therefore, for multilayer ceramic electronic components with leads, hermetic seals have been put into practical use as an external insulation method to ensure reliability against environmental changes, and are an extremely excellent insulation method. However, since this increases the size and significantly increases the cost, it has to be used only in areas where reliability is particularly required.
従つて、リード付電子部品の外部絶縁、外装の
その他の方法として、エポキシ等の有機樹脂によ
る絶縁が行われているが、有機樹脂は水蒸気をほ
ぼ100%通過させてしまうため、マイグレーシヨ
ンに対しては全く防止効果が得られず、耐湿負荷
の信頼性を著しく低下させていた。 Therefore, insulation using organic resins such as epoxy is used as an alternative method for external insulation and packaging of electronic components with leads, but since organic resins allow almost 100% of water vapor to pass through, they are difficult to prevent migration. However, no preventive effect could be obtained at all, and the reliability of moisture resistance load was significantly lowered.
また、電子部品の導体部分を無機材料により絶
縁する方法としては、HIC等で使用されている無
機絶縁材料を含有する絶縁ペーストを用いたスク
リーン印刷法やデイツプ法、絶縁材料粉末を用い
たスプレー法などが実用化されているが、スクリ
ーン印刷法は均一に印刷できるものの位置合わせ
をすることがむつかしく、加えて個別の小型部品
の場合には、大量に処理することが出来ず、コス
ト高になつていた。また回路ごとにスクリーンを
用意する必要があり、工程管理の上でも問題が多
かつた。デイツプ法、スプレー法は大量に安く生
産できる利点はあるが、絶縁層を形成する位置が
不正確であつたり、厚みにバラツキが出たり、ピ
ンホールが発生し易いなどの絶縁層の品質上の欠
点があり限られた部分でしか使用されていなかつ
た。 In addition, methods for insulating the conductor parts of electronic components with inorganic materials include the screen printing method and dip method using insulating paste containing inorganic insulating materials used in HIC, etc., and the spray method using insulating material powder. Although screen printing methods can print uniformly, it is difficult to align them, and in addition, in the case of individual small parts, it is not possible to process large quantities, resulting in high costs. was. In addition, it was necessary to prepare a screen for each circuit, which caused many problems in terms of process control. The dip method and spray method have the advantage of being able to produce large quantities at low cost, but they have problems with the quality of the insulating layer, such as the positioning of the insulating layer being inaccurate, the thickness being uneven, and pinholes easily occurring. Due to its drawbacks, it was only used in limited areas.
以上述べたように端子電極の材料の検討、外装
方法の検討などにより、信頼性を確保する方法が
いろいろと試みられているが、著しい改善は見ら
れていない。このように部品レベルでの絶縁に対
する信頼性を確保することが困難なため、部品を
実装した回路全体を有機樹脂による外装などによ
つて絶縁の信頼性を確保しようという試みも行わ
れているが、コストが高くなつたり、形状が大き
くなつたりする問題があり、信頼性もあまり改善
がみられない状況にある。 As described above, various methods have been tried to ensure reliability by examining materials for terminal electrodes and packaging methods, but no significant improvements have been seen. Because it is difficult to ensure insulation reliability at the component level, attempts have been made to ensure insulation reliability by covering the entire circuit in which the components are mounted with organic resin, etc. However, there are problems such as increased cost and increased size, and there is little improvement in reliability.
一方、電気泳動法による導電体への粉末の塗布
は、金属の塗装、ホーロー等の分野では実用化さ
れている技術ではあるがいずれも形状の大きいも
のに塗布する技術である。また、電子部品にも電
気化学Vol.40、No.7ページ478や特公昭48−6299
に記載されているようにシリコンデバイスのパツ
シベイシヨンとして研究されている。しかしなが
らこれらの技術はいずれも表面全体を有機;無機
あるいはこれらの混合物で覆うものであり、本発
明にように非常に微細な導体部分の表面を選択的
に覆いかつ、隣接するセラミツク材料部分をも含
めて絶縁物を形成するようなものではなかつた。 On the other hand, applying powder to a conductor by electrophoresis is a technique that has been put into practical use in the fields of metal painting, enamel, etc., but in all cases it is a technique for applying to large objects. Also, for electronic parts, Electrochemistry Vol. 40, No. 7 page 478 and Special Publication No. 48-6299
As described in , it is being researched as a connectivity for silicon devices. However, all of these techniques cover the entire surface with organic, inorganic, or a mixture thereof, and as in the present invention, the surface of a very fine conductor part is selectively covered and the adjacent ceramic material part is also covered. It did not include anything that would form an insulator.
このように、これまで積層セラミツク電子部品
の外部に露出した電極部分を信頼性よく絶縁する
ことは非常に困難であり、実際には、全く絶縁さ
れないか、不充分な絶縁方法によつて絶縁された
状態で使用されており、その結果、これら電子部
品の信頼性を著しく低下させていた。 As described above, it has been extremely difficult to reliably insulate the externally exposed electrode portions of laminated ceramic electronic components, and in reality, they are either not insulated at all or are insulated using insufficient insulation methods. As a result, the reliability of these electronic components has been significantly reduced.
本発明はこれらの問題点を全て解決する新しい
外部絶縁方法を提案するものであり、形状が小さ
いものでも確実にかつ、低コストで絶縁できる特
徴をもつている。 The present invention proposes a new external insulation method that solves all of these problems, and has the feature that even small shapes can be insulated reliably and at low cost.
本発明は、積層セラミツク電子部品の金属導体
を一方の電極として用いる電気泳動法によつて、
無機粉末を金属導体上に塗布するものであり、こ
の方法により金属導体部分のみでなく隣接するセ
ラミツク素体の部分も含む形で無機粉末が塗布さ
れ、その後、これを焼き付けることによつて電子
部品の外部絶縁として利用できることを見出した
ものである。 The present invention utilizes an electrophoresis method using a metal conductor of a laminated ceramic electronic component as one electrode.
This method involves applying inorganic powder onto a metal conductor. By this method, the inorganic powder is applied not only to the metal conductor part but also to the adjacent ceramic body part, and then by baking it, it becomes an electronic component. It was discovered that it can be used as external insulation for
本発明の方法に従えば、積層セラミツク電子部
品の外部に露出した電極の部分に選択的に均一な
絶縁層を容易に形成することができ、しかも小型
の部品を大量に処理することが出来るためコスト
を下げることも可能である。 According to the method of the present invention, it is possible to selectively and easily form a uniform insulating layer on the electrode portions exposed to the outside of laminated ceramic electronic components, and it is also possible to process small components in large quantities. It is also possible to reduce costs.
以下本発明を、実施例によつて詳細に説明す
る。 The present invention will be explained in detail below using examples.
実施例 1
通常行なわれている方法によつて製造した
BaTiO3系積層セラミツクチツプコンデンサの寸
法が1mm×2mm×1mmで容量が0.1μFのものに通
常行われている、デイツプ法に従つて、銀ペース
トを塗布し、チツプ両端に外部電極を焼付けた。Example 1 Manufactured by a commonly used method
Silver paste was applied using the dip method, which is commonly used for BaTiO 3 multilayer ceramic chip capacitors with dimensions of 1 mm x 2 mm x 1 mm and a capacitance of 0.1 μF, and external electrodes were baked on both ends of the chip.
外部電極は、銀100%のものを用い、900℃で焼
付けを行つた。 The external electrodes were made of 100% silver and baked at 900°C.
このチツプコンデンサを第1図に示す様に装置
を用いて固定し、電気泳動法を行うためにスラリ
ー4の入つた槽5の中に入れて、直流電圧6を印
加し、絶縁層の塗布を行つた。電気泳動法用スラ
リーの組成は次に示すものを用い、これらの構成
成分をホモジナイザーで充分均一分散して、電気
泳動法用のスラリーとした。 This chip capacitor is fixed using a device as shown in Fig. 1, placed in a tank 5 containing slurry 4 for electrophoresis, and a DC voltage 6 is applied to apply an insulating layer. I went. The composition of the slurry for electrophoresis was as shown below, and these components were sufficiently uniformly dispersed using a homogenizer to prepare the slurry for electrophoresis.
エチルアルコール 400ml
ホウケイ酸鉛ガラス粉末 50g
ポリビニルブチラール 4g
水 8ml
スラリー4を入れた槽5は、スターラー7を用
いて、均一になる様に撹拌し、サンプル3と対向
電極2の間に50Vの直流を5分間印加した。Ethyl alcohol 400ml Lead borosilicate glass powder 50g Polyvinyl butyral 4g Water 8ml Tank 5 containing slurry 4 was stirred uniformly using stirrer 7, and 50V DC was applied between sample 3 and counter electrode 2. The voltage was applied for 5 minutes.
その結果電極の表面には約300μmの厚さの均
一なガラス粉末層が形成された。 As a result, a uniform glass powder layer with a thickness of about 300 μm was formed on the surface of the electrode.
この積層コンデンサを800℃で10分間熱処理し、
絶縁層を焼付けた。 This multilayer capacitor was heat treated at 800℃ for 10 minutes,
Baked the insulation layer.
電極部分にリード線をハンダ付けし、容量、誘
電損失、絶縁抵抗を測定した。 Lead wires were soldered to the electrodes, and capacitance, dielectric loss, and insulation resistance were measured.
その結果、絶縁層を形成する前の電気特性と全
く変化がが認められなかつた。 As a result, no change was observed in the electrical properties compared to those before forming the insulating layer.
次にこの試料を85℃相対湿度90〜95%の恒温槽
中で50Vの直流電圧を印加する試験を行つた。 Next, this sample was subjected to a test in which a DC voltage of 50 V was applied in a constant temperature bath at 85° C. and a relative humidity of 90 to 95%.
その結果絶縁層を形成しなかつた試料および有
機樹脂で外装を行つた試料は300時間以内にシユ
ート状態になつたが、本発明の製造方法に従つて
絶縁した試料は500時間を経過しても、電気特性
に変化は認められなかつた。 As a result, the samples without an insulating layer and the samples covered with organic resin reached the shute state within 300 hours, but the samples insulated according to the manufacturing method of the present invention remained in a shudder state even after 500 hours. No change was observed in the electrical properties.
実施例 2
通常行なわれている方法に従つて、アルミナ基
板上に銀−パラジウムペーストを用いて、導体回
路を厚膜法により形成した。Example 2 A conductive circuit was formed on an alumina substrate by a thick film method using silver-palladium paste according to a commonly used method.
この導体回路を電気泳動法用のスラリーの中に
浸漬し陰極、対向電極を陽極になるように直流電
圧を印加した。 This conductor circuit was immersed in a slurry for electrophoresis, and a DC voltage was applied so that the cathode and counter electrode became the anode.
スラリーの組成、電圧印加条件は実施例1と同
様であつた。 The composition of the slurry and the voltage application conditions were the same as in Example 1.
この結果、表面の導体層上とその付近のみに
300μmの無機粉末層が形成された。この基板を
830℃で10分間熱処理して、絶縁層を焼付けた。 As a result, only on and near the surface conductor layer
A 300 μm inorganic powder layer was formed. This board
The insulating layer was baked by heat treatment at 830°C for 10 minutes.
この方法によつて形成された絶縁層は均一でピ
ンホールが全くないものであつた。 The insulating layer formed by this method was uniform and free of pinholes.
実施例 3
グリーンシートを積層して、焼結する方法によ
つて得られたPZT系積層セラミツク圧電素子に
外部取出し電極を800℃で焼き付けた。Example 3 External electrodes were baked at 800° C. on a PZT-based laminated ceramic piezoelectric element obtained by laminating green sheets and sintering them.
実施例1で述べた方法と同様の方法で電気泳動
法によつて、絶縁層を形成するために、スラリー
の槽の中に入れ、直流電圧を印加した。 In order to form an insulating layer by electrophoresis in the same manner as described in Example 1, the sample was placed in a slurry bath and a DC voltage was applied.
電気泳動法のスラリー組成は次のものを用い
た。 The following slurry composition was used for electrophoresis.
イソプロピアアルコール 400ml
ホウケイ酸鉛系結晶化ガラス 50g
ヨウ素 3g
サンプルと対向電極の間に150Vの直流を3分
間印加した。Isopropia alcohol 400ml Lead borosilicate crystallized glass 50g Iodine 3g A direct current of 150V was applied for 3 minutes between the sample and the counter electrode.
その結果、外部電極上に200μmの厚さのガラ
ス粉末層が形成した。 As a result, a glass powder layer with a thickness of 200 μm was formed on the external electrode.
このサンプルを800℃で10分間加熱処理して、
絶縁層を焼付けた。 This sample was heat-treated at 800℃ for 10 minutes,
Baked the insulation layer.
このようにして絶縁層を形成した積層セラミツ
ク圧電素子の分極処理した後、300Vの交流電圧
を加えて、振動させたところ、良好な振動特性を
示した。 After the laminated ceramic piezoelectric element with the insulating layer formed in this manner was polarized, an AC voltage of 300V was applied to it and it was vibrated, and it showed good vibration characteristics.
またこのサンプルを湿度90〜95%、温度40℃の
条件で電圧と印加し、振動を行つたが、500時間
連続動作しても異常は生じなかつた。 Furthermore, this sample was vibrated by applying a voltage at a humidity of 90 to 95% and a temperature of 40°C, but no abnormality occurred even after continuous operation for 500 hours.
以上実施例で示したように、本発明によれば、
積層セラミツク電子部品の外部の電極露出部分付
近に選択的に絶縁層を均一に形成し、しかもセラ
ミツク部分と、電極部分の両方にまたがつて、絶
縁層を形成でき、しかも焼付けることによつて、
緻密なガラス又はセラミツク層となり、耐湿、耐
絶縁性の優れたチツプ状の積層セラミツク電子部
品を形成することができる。 As shown in the examples above, according to the present invention,
The insulating layer can be selectively and uniformly formed near the external electrode exposed part of a laminated ceramic electronic component, and the insulating layer can be formed across both the ceramic part and the electrode part, and moreover, by baking. ,
It becomes a dense glass or ceramic layer, making it possible to form chip-shaped laminated ceramic electronic components with excellent moisture resistance and insulation resistance.
また電気泳動法は、大量に処理することが可能
なため、量産化が可能となり、製造コストを下げ
ることができる。 Furthermore, since the electrophoresis method allows large quantities to be processed, mass production is possible and manufacturing costs can be reduced.
本発明の実施例では積層セラミツクコンデン
サ、多層セラミツク基板、圧電素子を示したが、
この他にも、積層バリスタ、積層インダクタ、積
層型センサなど、あらゆる積層セラミツク電子部
品に本発明の方法が適用できることは明らかであ
る。 In the embodiments of the present invention, a multilayer ceramic capacitor, a multilayer ceramic substrate, and a piezoelectric element are shown.
It is clear that the method of the present invention can be applied to all other laminated ceramic electronic components such as laminated varistors, laminated inductors, and laminated sensors.
第1図は本発明の電気泳動法を行うための装置
の一例を示す概略図である。図の中の番号はそれ
ぞれ1;陽極、2;陰極、3;チツプサンプル、
4;スラリー、5;恒温槽、6;直流電源、7;
撹拌機、を示す。
FIG. 1 is a schematic diagram showing an example of an apparatus for carrying out the electrophoresis method of the present invention. The numbers in the diagram are 1: anode, 2: cathode, 3: chip sample,
4; Slurry, 5; Constant temperature bath, 6; DC power supply, 7;
A stirrer is shown.
Claims (1)
2以上の端子電極あるいは配線のうち一部又は全
部を一方の電極とし、別に用意した電極板を対向
電極として、無機粉末を分散させた懸濁液中で両
電極間に直流電圧を印加して行う電気泳動法によ
り前記無機粉末を前記露出端子電極あるいは該露
出配線に塗布し、その後焼き付ける工程を有する
ことを特徴とするセラミツク電子部品の絶縁方
法。1. Part or all of one or more terminal electrodes or wiring exposed to the outside of a ceramic electronic component is used as one electrode, and a separately prepared electrode plate is used as a counter electrode in a suspension in which inorganic powder is dispersed. A method for insulating ceramic electronic parts, comprising the steps of applying the inorganic powder to the exposed terminal electrode or the exposed wiring by electrophoresis by applying a DC voltage between both electrodes, and then baking it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57225168A JPS59115512A (en) | 1982-12-22 | 1982-12-22 | Method of insulating ceramic electronic part |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57225168A JPS59115512A (en) | 1982-12-22 | 1982-12-22 | Method of insulating ceramic electronic part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59115512A JPS59115512A (en) | 1984-07-04 |
| JPH0234449B2 true JPH0234449B2 (en) | 1990-08-03 |
Family
ID=16825003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57225168A Granted JPS59115512A (en) | 1982-12-22 | 1982-12-22 | Method of insulating ceramic electronic part |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59115512A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008047676A (en) * | 2006-08-15 | 2008-02-28 | Fujifilm Corp | Multilayer piezoelectric element |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6164101A (en) * | 1984-09-05 | 1986-04-02 | 日本電気株式会社 | Circuit part and method of producing same |
| JP4802353B2 (en) * | 1999-12-08 | 2011-10-26 | Tdk株式会社 | Multilayer piezoelectric ceramic electronic component and manufacturing method thereof |
| JP6003446B2 (en) * | 2012-09-19 | 2016-10-05 | トヨタ自動車株式会社 | Method for manufacturing oriented magnet and rare earth magnet |
-
1982
- 1982-12-22 JP JP57225168A patent/JPS59115512A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008047676A (en) * | 2006-08-15 | 2008-02-28 | Fujifilm Corp | Multilayer piezoelectric element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59115512A (en) | 1984-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104252968B (en) | Monolithic ceramic electronic component and its mounting structure | |
| US8584348B2 (en) | Method of making a surface coated electronic ceramic component | |
| JPS5929414A (en) | Compliant terminal for ceramic chip condenser | |
| CN108054008A (en) | Multilayer ceramic capacitor | |
| CN1303621C (en) | Chip type electronic parts | |
| US3683245A (en) | Hermetic printed capacitor | |
| JPH08107039A (en) | Ceramic electronic component | |
| US6452780B2 (en) | Capacitor | |
| JPH0234449B2 (en) | ||
| JP2000182883A (en) | Manufacturing method of multilayer ceramic electronic component | |
| US20050229388A1 (en) | Multi-layer ceramic chip varistor device surface insulation method | |
| KR100807217B1 (en) | Ceramic parts and manufacturing method thereof | |
| CN102177562A (en) | Bulk capacitor and method | |
| JP3210042B2 (en) | Electronic components for surface mounting | |
| JPH04293214A (en) | Conductive paste for chip type electronic component | |
| JPH10163067A (en) | External electrodes for chip-type electronic components | |
| JP2850200B2 (en) | Multilayer ceramic electronic components | |
| JPH04329616A (en) | Laminated type electronic component | |
| JP4466567B2 (en) | Semiconductor ceramic electronic component and manufacturing method thereof | |
| JPH02224311A (en) | Manufacture of laminated ceramic electronic part | |
| JPH09266129A (en) | External electrodes for chip-type electronic components | |
| JPH0864029A (en) | Terminal electrode paste | |
| JPS5950596A (en) | Chip type electronic part and method of producing same | |
| US11984269B2 (en) | Ceramic electronic component | |
| JPS6164101A (en) | Circuit part and method of producing same |