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JPH0234537B2 - - Google Patents
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JPH0234537B2 - - Google Patents

Info

Publication number
JPH0234537B2
JPH0234537B2 JP59050428A JP5042884A JPH0234537B2 JP H0234537 B2 JPH0234537 B2 JP H0234537B2 JP 59050428 A JP59050428 A JP 59050428A JP 5042884 A JP5042884 A JP 5042884A JP H0234537 B2 JPH0234537 B2 JP H0234537B2
Authority
JP
Japan
Prior art keywords
circuit
signal
synchronization
spread
determination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59050428A
Other languages
Japanese (ja)
Other versions
JPS60194637A (en
Inventor
Kazuhiro Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP59050428A priority Critical patent/JPS60194637A/en
Publication of JPS60194637A publication Critical patent/JPS60194637A/en
Publication of JPH0234537B2 publication Critical patent/JPH0234537B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/713Spread spectrum techniques using frequency hopping
    • H04B1/7156Arrangements for sequence synchronisation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/713Spread spectrum techniques using frequency hopping
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69Spread spectrum techniques
    • H04B1/713Spread spectrum techniques using frequency hopping
    • H04B1/7156Arrangements for sequence synchronisation
    • H04B2001/71563Acquisition

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)

Description

【発明の詳細な説明】 〔技術分野〕 本発明は周波数ホツピングスペクトラム拡散通
信方式の受信機に用いられる同期回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a synchronization circuit used in a frequency hopping spread spectrum communication receiver.

〔従来技術〕[Prior art]

第1図は従来の周波数ホツピングスペクトラム
拡散通信方式における受信機の同期回路のブロツ
ク図である。この同期回路は、局部拡散信号を発
生するための周波数シンセサイザ8およびPN符
号発生器9と、搬送波の周波数がPN符号と予め
定められたデータとによつてホツピングする受信
信号(以下プリアンブル信号と呼ぶ)101と局
部拡散信号104との相関信号103を形成し、
平衡変調器3、帯域通過波器4、包絡線検波器
5から成る相関検出器1と;この相関信号103
を受け、プリアンブル信号101と局部拡散信号
104とのホツピングパターンの一例(以下同期
状態と呼ぶ)を検出し、積分器6、スレシホール
ド検出器7から成る第1の同期判定回路2と;
PN符号発生器9のクロツクを生ずるVCO10
と;同期状態の維持を行う同期追跡回路12と;
第1の判定回路2の出力を受けVCO10および
同期追跡回路12を制御する制御回路11とを備
えている。
FIG. 1 is a block diagram of a synchronization circuit of a receiver in a conventional frequency hopping spread spectrum communication system. This synchronization circuit includes a frequency synthesizer 8 and a PN code generator 9 for generating a locally spread signal, and a received signal (hereinafter referred to as a preamble signal) in which the frequency of a carrier wave is hopping according to a PN code and predetermined data. ) 101 and a locally spread signal 104 to form a correlation signal 103,
a correlation detector 1 consisting of a balanced modulator 3, a bandpass wave detector 4, and an envelope detector 5; this correlation signal 103;
A first synchronization determination circuit 2 comprising an integrator 6 and a threshold detector 7;
VCO 10 that generates the clock for the PN code generator 9
and; a synchronization tracking circuit 12 that maintains a synchronized state;
The control circuit 11 receives the output of the first determination circuit 2 and controls the VCO 10 and the synchronization tracking circuit 12.

この同期回路の動作を説明する。第2図はプリ
アンブル信号101と局部拡散信号104との間
の位相差に対する相関信号出力の特性図を示し、
点Aが同期状態である。この同期回路の動作は、
第2図の範囲Bに局部拡散信号の位相を調整する
捕捉と、点Aの同期状態まで調整する追跡とに分
けられる。まず捕捉においては、制御回路11は
局部拡散信号104の位相を変化させ判定回路2
の出力を監視する。判定回路2が局部拡散信号1
04の位相が範囲B内に入つたことを出力する
と、制御回路11は捕捉を終了し追跡を行うため
同期追跡回路12を動作させる。この後制御回路
11は、再び第1の判定回路2の出力により同期
状態が得られたかどうかを判定し、その結果によ
つて捕捉のやり直しか、または同期追跡の継続か
の何れかを行う。
The operation of this synchronous circuit will be explained. FIG. 2 shows a characteristic diagram of the correlation signal output with respect to the phase difference between the preamble signal 101 and the local spread signal 104,
Point A is in sync. The operation of this synchronous circuit is
This can be divided into acquisition, which adjusts the phase of the local spread signal to range B in FIG. 2, and tracking, which adjusts the phase to the synchronized state at point A. First, in acquisition, the control circuit 11 changes the phase of the locally spread signal 104 and the determination circuit 2
monitor the output of Judgment circuit 2 uses locally spread signal 1
When the control circuit 11 outputs that the phase of 04 falls within the range B, the control circuit 11 operates the synchronous tracking circuit 12 to complete the acquisition and perform tracking. Thereafter, the control circuit 11 again determines whether a synchronized state has been obtained based on the output of the first determination circuit 2, and depending on the result, either re-acquires or continues synchronized tracking.

しかし、この従来の同期回路では、受信信号レ
ベルが一定で自動利得調整回路(以下AGCと呼
ぶ)を必要としない場合には、第1の判定回路2
が正しい判定を行うが、受信信号レベルが変動し
それを補正するため捕捉終了後AGCを動作させ
ると、正しい判定ができないという問題がある。
例えば、雑音等により誤つて追跡に移行した場
合、第1の判定回路2はAGCの作用により雑音
を信号と誤認してしまい再び捕捉を行うことがで
きないという欠点があつた。
However, in this conventional synchronous circuit, when the received signal level is constant and an automatic gain adjustment circuit (hereinafter referred to as AGC) is not required, the first judgment circuit 2
However, if the received signal level fluctuates and AGC is operated after acquisition to compensate for it, there is a problem that correct determination cannot be made.
For example, when tracking is mistakenly performed due to noise or the like, the first determination circuit 2 misidentifies the noise as a signal due to the action of AGC, and is unable to perform acquisition again.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、このような欠点を除き、周波
数ホツピングスペクトラム拡散通信における受信
機の同期獲得を確実に行うことのできる同期回路
を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization circuit that can eliminate these drawbacks and reliably acquire synchronization of a receiver in frequency hopping spread spectrum communication.

〔発明の構成〕[Structure of the invention]

本発明の構成は、予め定めたデータによつて変
調されたスペクトル拡散信号を受けこのスペクト
ル拡散信号と局部拡散信号との間の相関値を示す
相関信号を形成する相関検出器と、この相関検出
器の相関信号を受け所定のタイミングにおける同
期のスレシホールド判定を行う第1の判定回路
と、前記局部拡散信号を形成する拡散信号発生器
と、この拡散信号発生器のクロツクを生ずる
VCOと、前記スペクトラム拡散信号を受け前記
局部拡散信号との同期関係を維持する同期追跡回
路と、前記第1の判定回路の判定出力を受け前記
VCOおよび前記同期追跡回路を制御する制御回
路とを含む同期回路において、前記相関検出器か
ら逆拡散された信号を受けデータ信号を復調する
FSK復調器と、この復調器のデータ信号と所定
データとの一致する割合を検出し所定割合以上の
一致を検出したとき同期と判定する判定出力を前
記制御回路に供給する第2の判定回路とを付加し
たことを特徴とする。
The present invention comprises a correlation detector that receives a spread spectrum signal modulated by predetermined data and forms a correlation signal indicating a correlation value between the spread spectrum signal and the local spread signal; a first determination circuit that receives the correlation signal of the detector and makes a synchronization threshold determination at a predetermined timing; a spread signal generator that forms the local spread signal; and a clock for the spread signal generator.
a synchronization tracking circuit that receives the spread spectrum signal and maintains a synchronous relationship with the local spread signal; and a synchronization tracking circuit that receives the determination output of the first determination circuit and receives the
A synchronization circuit including a VCO and a control circuit for controlling the synchronization tracking circuit receives the despread signal from the correlation detector and demodulates the data signal.
an FSK demodulator; a second determination circuit that detects a coincidence ratio between the data signal of the demodulator and predetermined data and supplies a determination output for determining synchronization when a coincidence of a predetermined ratio or more is detected to the control circuit; It is characterized by the addition of.

本発明による同期回路は、プリアンブル信号が
予め定められたデータパターンになることを利用
したものであり、従来の同期回路と、逆拡散され
た信号を受けデータ信号を生ずるFSK復調器と、
このデータ信号と予め定められたデータパターン
との一致を検出する第2の同期判定回路から構成
される。
The synchronization circuit according to the present invention utilizes the fact that a preamble signal has a predetermined data pattern, and includes a conventional synchronization circuit, an FSK demodulator that receives a despread signal and generates a data signal,
It is comprised of a second synchronization determination circuit that detects a match between this data signal and a predetermined data pattern.

〔実施例〕〔Example〕

以下図面を参照して本発明を詳細に説明する。 The present invention will be described in detail below with reference to the drawings.

第3図は本発明の一実施例のブロツク図であ
り、この実施例は、プリアンブル信号時のデータ
パターンが全て「1」の場合の例である。この実
施例は、第1図の従来回路に対して逆拡散信号1
02からデータ信号を生ずるFSK復調器と、あ
る一定時間内にデータ信号中に含まれる「1」の
数が予め定めた値に達したかどうかを判定するカ
ウンタ14とからなる第2の判定回路15を備え
ることを特徴とする。
FIG. 3 is a block diagram of one embodiment of the present invention, and this embodiment is an example in which the data pattern at the time of the preamble signal is all "1". In this embodiment, the despread signal 1 is different from the conventional circuit shown in FIG.
02, and a counter 14 that determines whether the number of "1"s included in the data signal reaches a predetermined value within a certain period of time. 15.

このような構成の回路の動作を説明する。 The operation of the circuit having such a configuration will be explained.

同期の捕捉は、従来の回路と同様に、第1の判
定回路2の出力を用いて行うが追跡後の同期の判
定では、制御回路11が第2の同期追跡回路15
にタイミング信号105を送出し、そのデータ信
号中の「1」の割合をカウントし、そのカウント
値が定めた値に達したかどうかで判定を行う。こ
のとき、このカウンタ14に与える値は第1の判
定回路2に与えるスレシホールドレベルに相当す
るが、この値はデータの誤り率に応じて設定され
る値であり細かい設定が可能である。
Acquisition of synchronization is performed using the output of the first determination circuit 2, as in the conventional circuit, but in determining synchronization after tracking, the control circuit 11 uses the output of the second synchronization tracking circuit 15.
A timing signal 105 is sent to the data signal, the ratio of "1" in the data signal is counted, and a determination is made based on whether the count value has reached a predetermined value. At this time, the value given to this counter 14 corresponds to the threshold level given to the first determination circuit 2, but this value is set according to the data error rate and can be set in detail.

また、判定回路1の結果がAGCにより、検波
器出力中の雑音レベルの変化によつて影響を受け
るのに対し、第1の判定回路2の結果はFSK復
調器13が信号レベル、雑音レベルの相対的比較
によりデータ信号を得るため、信号対雑音比によ
つて決まり、AGCの影響を受けにくい。このた
め従来の回路と比較すると、本実施例の同期回路
は捕捉、追跡後の同期状態かどうかの判定を正し
く行うことができる。
Furthermore, while the result of the first judgment circuit 1 is affected by the change in the noise level in the detector output due to AGC, the result of the first judgment circuit 2 is that the FSK demodulator 13 is affected by the change in the signal level and noise level. Since the data signal is obtained by relative comparison, it is determined by the signal-to-noise ratio and is not easily affected by AGC. Therefore, compared to conventional circuits, the synchronization circuit of this embodiment can correctly determine whether or not the synchronization state is established after acquisition and tracking.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、周波数
ホツピング拡散通信方式の受信機において、その
受信信号レベルが変動するような条件下でも同期
状態を確実に得ることが出来る同期回路が得られ
る。従つて、この同期回路を用いれば、その受信
信号レベルが大きく変動するような移動系のスペ
クトラム拡散通信も有効に行うことが出来る。
As described above, the present invention provides a synchronization circuit that can reliably obtain a synchronized state even under conditions where the received signal level fluctuates in a frequency hopping spread communication receiver. Therefore, by using this synchronization circuit, it is possible to effectively carry out mobile spread spectrum communication in which the received signal level fluctuates greatly.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の周波数ホツピング受信機の同期
回路の構成を示すブロツク図、第2図は第1図の
動作説明を行う相関値パターン図、第3図は本発
明の一実施例のブロツク図である。図において、 1……相関検出器、2……第1同期判定回路、
3……平衡変調器、4……帯域通過波器、5…
…包絡線検波器、6……積分器、7……スレシホ
ールド検出器、8……周波数シンセサイザ、9…
…PN符号発生器、10……VCO、11……制御
回路、12……同期追跡回路、13……FSK復
調器、14……カウンタ、15……第2同期判定
回路である。
Fig. 1 is a block diagram showing the configuration of a synchronization circuit of a conventional frequency hopping receiver, Fig. 2 is a correlation value pattern diagram explaining the operation of Fig. 1, and Fig. 3 is a block diagram of an embodiment of the present invention. It is. In the figure, 1... Correlation detector, 2... First synchronization determination circuit,
3...Balanced modulator, 4...Band pass wave generator, 5...
...Envelope detector, 6...Integrator, 7...Threshold detector, 8...Frequency synthesizer, 9...
... PN code generator, 10 ... VCO, 11 ... control circuit, 12 ... synchronization tracking circuit, 13 ... FSK demodulator, 14 ... counter, 15 ... second synchronization determination circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 予め定めたデータによつて変調されたスペク
トル拡散信号を受けこのスペクトル拡散信号と局
部拡散信号との間の相関値を示す相関信号を形成
する相関検出器と、この相関検出器の相関信号を
受け所定のタイミングにおける同期のスレシホー
ルド判定を行う第1の判定回路と、前記局部拡散
信号を形成する拡散信号発生器と、この拡散信号
発生器のクロツクを生ずるVCOと、前記スペク
トラム拡散信号を受け前記局部拡散信号との同期
関係を維持する同期追跡回路と、前記第1の判定
回路の判定出力を受け前記VCOおよび前記同期
追跡回路を制御する制御回路とを含む同期回路に
おいて、前記相関検出器から逆拡散された信号を
受けデータ信号を復調するFSK復調器と、この
復調器のデータ信号と所定データとの一致する割
合を検出し所定割合以上の一致を検出したとき同
期を判定する判定出力を前記制御回路に供給する
第2の判定回路とを付加したことを特徴とする同
期回路。
1 A correlation detector that receives a spread spectrum signal modulated by predetermined data and forms a correlation signal indicating a correlation value between the spread spectrum signal and the local spread signal; a first judgment circuit that performs a synchronization threshold judgment at a predetermined timing; a spread signal generator that forms the local spread signal; a VCO that generates a clock for the spread signal generator; In the synchronization circuit, the synchronization circuit includes a synchronization tracking circuit that maintains a synchronization relationship with the received local spread signal, and a control circuit that receives a determination output from the first determination circuit and controls the VCO and the synchronization tracking circuit, An FSK demodulator that receives the despread signal from the receiver and demodulates the data signal, and a judgment device that detects the proportion of coincidence between the data signal of this demodulator and predetermined data, and determines synchronization when a coincidence of a predetermined proportion or more is detected. A synchronous circuit further comprising a second determination circuit that supplies an output to the control circuit.
JP59050428A 1984-03-16 1984-03-16 Synchronizing circuit Granted JPS60194637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59050428A JPS60194637A (en) 1984-03-16 1984-03-16 Synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59050428A JPS60194637A (en) 1984-03-16 1984-03-16 Synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS60194637A JPS60194637A (en) 1985-10-03
JPH0234537B2 true JPH0234537B2 (en) 1990-08-03

Family

ID=12858593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59050428A Granted JPS60194637A (en) 1984-03-16 1984-03-16 Synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS60194637A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02181534A (en) * 1989-01-06 1990-07-16 Mitsubishi Electric Corp Adaptive control antenna
KR100702746B1 (en) 2002-08-20 2007-04-03 엘지전자 주식회사 Wireless LAN module power management method and computer device in computer system

Also Published As

Publication number Publication date
JPS60194637A (en) 1985-10-03

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