JPH0235265B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for measuring delay time of an integrated circuit.
For example, the present invention relates to a method of measuring delay time of an integrated circuit using an automatic test device having a memory device.

Generally, a function LSI with a large number of input/output pins (for example, 60 pins, 72 pins) is used as a high-speed measurement method for delay time between input and output of integrated circuits.
There is a method using a tester (automatic test equipment). According to this method, a test pattern generated by a pattern generator in a function LSI tester is applied to each of the input pins (for example, 40 pins, 60 pins, or 120 pins) of the device under test, and the output pins ( (also 40 pin, 60 pin, or 120 pin)
The output pattern for each is compared with the expected value to determine whether the quality of the device under test is good or bad. In this case, due to variations in output driver characteristics, differences in signal paths inside the LSI stator, etc., the rise/rise of the test pattern at the input pin of the device under test may occur.
A so-called skew occurs in which the falling edge deviates by approximately ±2 to ±5 nanoseconds for each pin. Furthermore, due to differences in impedance between the line connecting the function tester and the device under test and the terminals of the device under test, the rise of the test pattern at the input pins has a different rounding for each pin. Furthermore, because the detection system input capacitance differs for each output pin of the function LSI tester, the output waveform of the device under test becomes rounded. These skews in the input signal, blunting of the rise of the input signal, blunting of the output waveform, etc. can cause errors in delay time measurement, and may cause errors in the function.
When measuring delay time using an LSI tester,
These various error factors are superimposed and the measurement accuracy decreases. In order to correct measured values for these various error factors, function LSI
For each input/output pin of the tester, the measurement values have been individually determined in advance for the same type of device under test, and the correction values have been used to correct the measured values. However, the influence of various error factors on the device under test is
Investigating and correcting an extremely large number of combinations of input/output pins (up to 60 in the case of 60 pins)
Not only is it extremely complicated, but it also requires a lot of functionality.
The rise time of the waveform at the input pin of an LSI tester, which is determined by the circuit characteristics of the tester, is constant, for example 2 nanoseconds, so it cannot meet the measurement specifications of the device under test. It is not possible to deal with skew or blunted rise at the input pin, and complete correction is impossible due to the responsiveness of the detection system to the output of the device under test and the input impedance, so high accuracy is expected when measuring the delay time of integrated circuits. That is difficult.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to convert correction data of standard samples into accurate measurements using a sampling oscilloscope and a function LSI.
Based on the concept of calculating the difference between the values measured by the tester and correcting the measured values of each device under test using the correction data, we have improved the precision in measuring the delay time of integrated circuits and improved the accuracy of integrated circuit input. The purpose of this invention is to propose a method for measuring delay time of integrated circuits using a function LSI tester, which eliminates the complexity of examining the influence of error factors for all combinations of output pins.

In the present invention, an integrated circuit using a function tester applies a test pattern generated by a pattern generator to each of the input pins of the integrated circuit under test and compares the output value at each of the output pins with the expected value. A method for measuring delay time of a circuit involves accurately measuring the delay time of a completely non-defective standard sample of the integrated circuit under test using a sampling scope, and then measuring the delay time of the standard sample using the function tester. The difference between this and the measurement value of the sampling scope is stored in a storage device as a correction table, and the measurement value regarding the delay circuit obtained by the function tester for the integrated circuit under test is calculated using the correction table. A method for measuring the delay time of an integrated circuit is provided, which is characterized in that the quality of the integrated circuit under test is judged by correcting the delay time and comparing it with the expected value.

In the embodiment of the integrated circuit delay time measurement method according to the present invention, as shown in the attached drawing, the required test pattern generated from the pattern generator 1 is transmitted through the switching means 2 to determine whether the LSI under test is completely non-defective. It is connected to the input pin of the standard LSI sample 4 or the LSI under test 13.

First, input the test pattern into standard LSI sample 4. In this case, the input/output pins are selected by the switching means 3 and 5, respectively, and the selected input/output pins are connected to the sampling scope 7 or the function LSI tester 8 by the interlocking switching means 6. When the input/output pins of the standard LSI sample 4 are connected to the sampling scope 7, the delay time is measured by the sampling scope for each test pattern for each combination of input/output pins, and this measurement result is used for the interface circuit and
The data is stored on the disk 9 via the CPU (not shown). Since the rise time of the sampling scope and measurement system is on the order of sub-nanoseconds, the delay time can be measured almost accurately, but the time required for measurement is much longer than when using a function LSI tester. Next, the input/output pins of the standard LSI sample 4 are switched to a function by the interlocking switching means 6.
When connected to the LSI tester 8, the function LSI tester 8 measures the delay time for each test pattern for each input/output pin combination, and the measurement results are used for the interface circuit and
The data is stored on the disk 10 via a CPU (not shown). The difference for each test pattern for each combination of input and output pins of the delay time of the standard LSI stored in the disks 9 and 10 is calculated by the arithmetic unit 14, and this difference is calculated based on the measured value by the sampling oscilloscope 7. This means that the difference between the measured values by the function LSI tester 8 for the above is taken as a measuring machine difference, and this measuring machine difference is stored in the disk 15 as a correction table.

Next, measure the same type of standard LSI sample 4.
A test pattern similar to the above is applied to the input pin of the LSI 13 via the switching means 2 to the pattern generator 1.
Enter more information. The input/output pins of the LSI under test are selected by switching means 11 and 12, respectively, and the selected input/output pins are selected by the function LSI tester 8.
connected to. The delay time is measured for each test pattern for each combination of input and output pins of the LSI under test 13 by the function LSI tester 8, and this measurement result is used in the correction device 16 to adjust the input and output pins according to the correction table stored in the disk 15. is corrected for each test pattern for each combination. The LSI under test obtained in this way
The final measurements are approximately equal to those obtained using a sampling oscilloscope and are extremely accurate. This final measured value is compared with an allowable value in the determination device 17 to determine whether the quality is good or bad.

As explained above, according to the present invention, the correction data of the standard sample is obtained from the difference between the measurement value by the sampling oscilloscope and the measurement value by the function LSI tester, and the measurement value of each device under test is calculated using the correction data. Based on the concept of correcting the delay time of integrated circuits, we aim to improve the accuracy in measuring the delay time of integrated circuits and eliminate the tediousness of manually examining the effects of error factors on all input/output pin combinations of integrated circuits. A method for measuring delay time of integrated circuits using a function LSI tester, which eliminates the above problems, is obtained.

In the embodiments of the present invention, values measured by a sampling oscilloscope were used as a reference, but instead of this, values obtained using other precision measuring instruments may be used as a reference.

[Brief explanation of drawings]

The accompanying drawing is a block circuit diagram of an integrated circuit delay time measurement system for explaining a method of measuring delay time of an integrated circuit according to the present invention. 1: Pattern generator, 2, 3, 5, 6,
11, 12: switching means, 4: standard LSI sample,
7: Sampling scope, 8: Function
LSI tester, 9, 10, 15: disk, 13:
LSI to be measured, 14: Arithmetic device, 16: Correction device,
17: Determination device.

Claims (1)

[Scope of Claims] 1. A function tester that applies a test pattern generated by a pattern generator to each of the input pins of the integrated circuit under test and compares the output value at each of the output pins with an expected value. In the method used to measure the delay time of an integrated circuit, the delay time of a perfectly good standard sample of the integrated circuit under test is accurately measured using a sampling scope, and the delay time of the standard sample is measured using the function tester. The difference between this and the measured value of the sampling scope is stored in a storage device as a correction table, and the measured value regarding the delay circuit obtained by the function tester for the integrated circuit under test is stored in the correction table. 1. A method for measuring delay time of an integrated circuit, characterized in that the quality of the integrated circuit under test is judged by correcting the delay time using the expected value and comparing it with the expected value.