JPH023569B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed switch circuit which requires direct current insulation and which switches the voltage of a load at high speed.

Conventionally, there have been circuits of this type as shown in FIGS. 1 and 2. In Figure 1, 1 is a power supply, 2 is a protection resistor, 3 is a bipolar transistor, 4 is a load, 5 is a base current limiting resistor, 6 is a rectifier circuit, 7 is a transformer, 8 is a control circuit, and 9 is a signal input terminal. be.

In FIG. 2, the same reference numerals as in FIG. 1 indicate the same components, 10 is a MOS-FET, and 11 is a pulse transformer. In addition, in FIGS. 1 and 2, the control circuit 8, the bipolar transistor 3, and the switch circuit portion of the control circuit 8 and the MOS-FET 10 are the transformer 7 and the pulse transformer 1, respectively.
1 provides DC insulation.

Next, the operation of the conventional circuit shown in FIG. 2, which has many similarities with the present invention, will be explained.

When transistor 3 and MOS-FET 10 are off, the output voltage of power supply 1 is almost equal to load 4.
is applied to.

Next, the input signal 21 in FIG.
When the control circuit 8 is entered, a gate voltage 22 with a constant pulse width is applied to the pulse transformer 11, and the MOS-FET 10 is made conductive through this. At the same time, the drive base current 23 also flows through the transistor 3 via the transformer 7 and the rectifier circuit 6. Then,
Load 4 is first a MOS- with short switching time.
It is quickly shorted by FET10. Then, by the time this MOS-FET 10 becomes non-conductive, the transistor 3 is in a conductive state, so that the short-circuited state of the load 4 is maintained. After that, the control circuit 8 oscillates so that current alternately flows through the transformer 7 in the same manner as a DC/DC converter. At this time, a voltage 24 as shown in FIG. 4b appears on the secondary side of the transformer 7. This voltage 24 causes the transistor 3 to continue to conduct, and the voltage across the load 4 becomes zero. Note that FIGS. 4a and 4c show the same signals 21 and 23 as in FIGS. 3a and 3c.

Next, when the input signal 21 turns off, the control circuit 8
oscillation stops, the base current of transistor 3 stops flowing, and transistor 3 becomes non-conductive again.

Since the conventional high-speed switch circuit is configured as described above, the on-time of the switch is MOS−
Although high speed can be obtained by the switching speed of the FET 10, there is a drawback that the off time is limited by the switching speed of the transistor 3. For example, when the withstand voltage is 800V, the typical switching speed of conventional circuits is limited to 1μs.

This invention was made to eliminate the drawbacks of the conventional devices as described above, and is constructed using MOS-FETs to increase the switching speed when off, especially when the load is capacitive. By using a switch circuit and a control circuit that creates the gate voltage necessary to switch it quickly and stably, we provide a high-speed switch circuit that can switch not only on time but also off time at a high speed of 100 nsec or less. It is intended to.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows a high speed switch circuit according to one embodiment of the present invention. In the figure, 1 is the power supply, 2 is the power supply 1
a protective resistor connected in series with the load 4 across the
10 is a first circuit that short-circuits both ends of load 4 at high speed.
MOS-FET, 13 is a second MOS-FET connected in parallel to the protective resistor 2 to quickly apply the voltage of the power supply 1 to the load 4, 8 is a control for short-circuiting the load to the signal input terminal 9 When the signal is input, the first
A first on signal for turning on the MOS-FET 10 and a second off signal for keeping the second MOS-FET in the off state are generated, and when the above control signal is no longer input, the first MOS-FET 10 A control circuit 7 generates an off signal for turning off the second MOS-FET 13 and a second on signal for turning on the second MOS-FET 13;
Transformer for DC/DC converter as the first transformer added to the gate of MOS-FET10, 1
6 connects the off signal of the control circuit 8 to the first MOS-
This is a pulse transformer as an off transformer that is added to the gate of FET10, and this is used in this example.
An off signal is input to the gate of the switch element 15 consisting of a MOS-FET, and this switch element 15 switches the first
The off signal is transmitted by short-circuiting the gate and source of the MOS-FET 10. Further, 14 converts the second ON signal of the control circuit 8 into a second ON signal.
2nd for input to the gate of MOS-FET13
This is a pulse transformer as a transformer. Note that 6 is a rectifier circuit that full-wave rectifies the output of the transformer 7;
11 is a pulse transformer that transmits a pulse signal to compensate for the rise time of the signal in order to increase the switching speed of the first MOS-FET 10; 12 is a pulse transformer that transmits a pulse signal to compensate for the rise time of the signal in order to increase the switching speed of the first MOS-FET 10; This is a diode to prevent the current from flowing.

FIG. 6 shows the operating waveforms of each part of this circuit.

The figure a shows the input signal 21 as a control circuit input to the signal input terminal 9, the figure b shows the waveform of the gate voltage 22 sent from the pulse transformer 11 to the first MOS-FET 10, and the figure c shows the waveform of the gate voltage 22 of the transformer 7. The next output voltage 24, d in the same figure, is the first output voltage from the rectifier circuit 6.
The rectified voltage 25 sent to the MOS-FET 10, e in the same figure is the gate voltage 2 applied to the switch element 15.
6. The figure f shows the gate voltage 27 of the second MOS-FET 13, the figure g shows the gate voltage 28 of the first MOS-FET 10, and the figure h shows the output voltage 29 output from both ends of the load 4. Note that the time difference T ₁ between waveforms 26 and 27 is from the rise of waveform 26 to the first MOS-
This is the delay time until the FET 10 turns off.
Moreover, T ₂ of waveform 26 is the first MOS-FET 10 when turning on the second MOS-FET 13.
This is the time required to prevent the gate from charging up and to remove the falling portion of the waveform 25.
The A part of the waveform 27 is a negative voltage part for canceling the charge up of the gate of the second MOS-FET 13 due to the ON operation of the first MOS-FET 10.

Next, the operation will be explained.

In the initial state where there is no input signal 21, the first and second MOS-FETs 10 and 13 and the switch element 15 are all off, and the voltage of the power supply 1 is applied to the load 4 via the protective resistor 2. has been done.

Next, when the input signal 21 is input to the signal input terminal 9, the gate voltage 22 that compensates for the rise is applied to the first voltage via the pulse transformer 11 and the diode 12.
It is applied to the gate of MOS-FET10. Almost simultaneously, the rectified voltage 25 is applied to the gate of the first MOS-FET 10 via the transformer 7 and the rectifier circuit 6, and the first MOS-FET 10 is turned on to short-circuit both ends of the load 4. At the same time, the waveform 22 is applied to the pulse transformer 14 so as to have the opposite polarity, and a negative voltage is applied to the gate of the second MOS-FET 13 to maintain a stable off state. Then, while the input signal 21 is present, the first MOS-FET 10 remains on due to the rectified voltage 25, and the current from the power supply 1 flows through the first MOS-FET 10 and the protective resistor 2.

Next, when the input signal 21 is turned off, the rectified voltage 25 is turned off, but due to the back electromotive force of the transformer 7 and the capacitance between the gate and source of the first MOS-FET 10, the first MOS-FET 10 The gate voltage is difficult to turn off. Therefore, at the same time that the input signal 21 is turned off, the gate voltage 2 that drives the switch element 15 via the pulse transformer 16 is
6 and turns on the switch element 15, the gate voltage of the first MOS-FET 10 is forcibly turned off, and the off operation of the first MOS-FET 10 is accelerated.

In this way, after the first MOS-FET 10 is sufficiently turned off, the second MOS-FET 10 is turned off via the pulse transformer 14.
A gate voltage 27 is applied to the MOS-FET 13.
Then, the load 4 is connected from the power supply 1 to the load 4 and the second
Current flows through the MOS-FET 13, and even if there is stray capacitance across the load 4, it is quickly switched and returns to the initial voltage state. After that, the pulse 27 that had turned on the second MOS-FET returns to the off state, and at that time the pulse transformer 1
The second MOS-
Applying a reverse voltage to the gate of FET13, the second MOS
- Turn off FET 13 quickly and return to the initial state.

In this way, the rise and fall times of the output voltage across the load 4 can be reduced to 100 nsec or less.

In addition, in this embodiment, in order to prevent malfunctions due to gate charging of the non-operating side MOS-FET that occurs due to high-speed switching, the gate voltage 27 of the second MOS-FET 13 is increased during on-operation.
is set to a negative voltage (see part A of Fig. 6f) to cancel the charging voltage of the gate generated by switching, and during off-operation, the on-time _T2 of the switch element 15 is set to Make it long enough to cover the on time of FET13, and
This prevents the gate of the MOS-FET 10 from being charged by switching. Furthermore, since this device uses a transformer, it can provide DC insulation between input and output, and can be used without problems even when the output circuit is floating at high voltage.

FIG. 7 shows another embodiment of the invention. In the figure, 7a and 7b connect the first and second MOS-FETs 10 and 13 via rectifier circuits 6a and 6b, respectively.
A transformer that supplies gate voltage to 15a, 15
b are the first and second MOS-FET1, respectively
This is a switch element that forcibly turns off the gate voltages of 0 and 13, and here both MOS-FETs are used. Further, reference numerals 16a and 16b are pulse transformers that apply gate voltages to the switch elements 15a and 15b, respectively.

This circuit basically operates in the same way as the embodiment shown in FIG. 5, except that a switch element 15b is newly provided to quickly turn off the second MOS-FET 13, and the protective resistor 2 is omitted. The second point is that the current from the load 4 or the first MOS-FET 10 always flows through the second MOS-FET 13, and because the pulse transformer 11 is omitted, the rise speed of the gate voltage is slightly slower. This is different from the embodiment shown in FIG.

Although the above embodiment uses a pulse transformer 11 and a diode 12 for compensation of rise, it is possible to obtain sufficient voltage and rise with the transformer 7 and the rectifier circuit 6, and the pulse transformer 11 and diode 12 are used. The diode 12 may be omitted.

In addition, in the above other embodiments, the first MOS-
Switch elements 15a and 15b are used to speed up the off operation of FET 10, but instead
A negative voltage may be applied to the gate of the MOS-FET 10, and the same effect as in the above embodiment can be obtained.

As described above, according to this invention, MOS-FET
Since the switch is provided for ON and OFF of switching operation, switching can be performed with low impedance to the load, which is useful even when the load is a capacitive load such as stray capacitance that interferes with high-speed switching operation. It is effective enough to demonstrate its performance even when it is exposed to heat.

[Brief explanation of drawings]

1 and 2 are circuit diagrams showing a conventional high speed switch circuit, FIGS. 3 and 4 are operational waveform diagrams of the conventional circuit, and FIG. 5 is a circuit diagram showing a high speed switch circuit according to an embodiment of the present invention. 6 is an operational waveform diagram of the circuit of FIG. 5, and FIG. 7 is a circuit diagram showing another embodiment of the present invention. 1...Power supply, 4...Load, 2...Protection resistor, 10...First MOS-FET, 13...Second MOS-FET,
8... Control circuit, 7... Transformer (first transformer),
16...Pulse transformer (off transformer), 14
...Pulse transformer (second transformer). Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A power supply and a first MOS-FET connected in parallel to a load connected to the power supply for short-circuiting the load at high speed.
and a second MOS-FET connected in series to the load to apply the power supply voltage to the load at high speed.
and a first on signal for turning on the first MOS-FET when a control signal indicating that the load should be short-circuited and a second on signal for maintaining the off state of the second MOS-FET. a first off signal for generating an off signal and turning off the first MOS-FET when the input of the control signal is stopped; and the second MOS-FET.
- a control circuit that generates a second on signal for turning on the FET, and a control circuit that generates the first on signal of this control circuit;
A first transformer added to the MOS-FET of
an OFF transformer that applies a second OFF signal and a second ON signal of the control circuit to the second MOS-FET via the MOS-FET; A high-speed switch circuit characterized by being equipped with. 2 The second OFF signal of the control circuit is passed through the second driving MOS-FET and then sent to the second MOS-FET.
a second OFF transformer that applies the second ON signal to the second MOS-FET;
2. The high-speed switch circuit according to claim 1, further comprising a second transformer in addition to the first transformer.