JPH0239125B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase detection circuit suitable for detecting the phase of a microwave signal, and more specifically, the present invention relates to a phase detection circuit suitable for detecting the phase of a microwave signal. The present invention aims to provide a phase detection circuit suitable for phase detection of wave signals.

2. Description of the Related Art Conventionally, a phase detection circuit as shown in FIG. 1 of the drawings has been proposed as a phase detection circuit in a circuit device that handles signals in the microwave band. In Figure 1, 1
and 2 are microstrip lines, and the microwave signal S ₁ is inputted from their respective input ends 1a and 2a.
and S ₂ are supplied. Each of the lines 1 and 2 is connected to a 1/4 wavelength branch line directional coupler 3, and its output ends 4 and 5 are grounded via diodes 6 and 7, respectively, which are oriented in opposite directions. and,
The cathode of the diode 6 and the anode of the diode 7 are commonly connected and grounded through an inductance 8 and a load resistor 9 for high frequency blocking, and an output terminal 10 is led out from the connection point between the inductance 8 and the load resistor 9. ing. The microwave signal S ₁ from the input end 1a is transmitted from the line 1 to the directional coupler 3
to the output end 4 via a branch line 3a having a length of 1/4 wavelength, and to the output end 5 via branch lines 3c and 3b or 3a and 3d, each having a length of 1/4 wavelength, Each propagates with a mutual phase difference of π/2. Further, the microwave signal S2 from the input end 2a is also transmitted from the line 2 to the output end 5 via the branch line 3b of the directional coupler 3, and to the output end 4 via the branch lines 3c and 3a or 3b and 3d. , respectively, with a mutual phase difference of π/2. Each microwave signal propagated to these output terminals 4 and 5 is detected by diodes 6 and 7, respectively, and the detection outputs from both diodes 6 and 7 are combined to form a microwave signal S ₁ supplied to input terminals 1a and 2a. A phase detection output corresponding to the mutual phase difference of S2 and _S2 is obtained at the output terminal 10.

Such conventional phase detection circuits for microwave signals have the disadvantage of low detection sensitivity because the phase detection section is formed by a pair of diodes. The temperature characteristics of the microwave signal input vs. DC output characteristics change depending on the input power of the input microwave signal, but it is difficult to align these characteristics changes between two diodes used in a pair. Therefore, it also had the disadvantage of lacking stability in phase detection operation.

Therefore, the present invention provides a novel phase detection circuit suitable for detecting the phase of a microwave signal, configured using a multi-gate field effect transistor, which can eliminate the drawbacks seen in conventional phase detection circuits.
Furthermore, a novel frequency discrimination circuit to which such a phase detection circuit is applied is also disclosed. below,
Embodiments and application examples of the present invention will be described with reference to FIG. 2 and subsequent drawings.

FIG. 2 shows an example of a phase detection circuit according to the present invention. 11 is a multi-gate field effect transistor (hereinafter referred to as DG/FET), which has two gates, a first and second gate, a source and a drain;
a first gate electrode G ₁ , a second gate electrode G ₂ , and
A source electrode S and a drain electrode D are led out. The first gate electrode _G1 and the second gate electrode _G2 each have a microstrip line 1 for signal input.
2 and 13 are connected. These lines 12 and 1
3 is DC grounded via high frequency blocking inductances 14 and 15, and each input terminal 1
2a and 13a, respectively, microwave signals S ₁ and
_S2 is supplied. Here, the input end 12 of the line 12
The length from a to the first gate electrode _G1 is the line 1
The length from the input end 13a of No. 3 to the second gate electrode _G2 is an odd multiple of 1/4 of the propagation wavelength λg (λg/4・
It is lengthened by (2n+1), n=0, 1, 2, 3...). Therefore, while the microwave signals S ₁ and S ₂ supplied to the input terminals 12a and 13a propagate to the first gate electrode G ₁ and the second gate electrode G ₂ , respectively, the microwave signal S ₁ is microwave signal
For S ₂ , odd multiple of π/2 (π/2・(2n+1),
They have a mutual phase difference of n=0.1, 2, 3...). The source electrode S of the DG/FET 11 has an odd number multiple of 1/4 of the propagation wavelength λg (λg/4・(2n+1), n=
An open microstrip line 16 having a length of 0,1,2,3... has been done. One end of this bias resistor 18 and the power supply +
A variable resistor 19 for bias current supply is connected between the bias current supply voltage and the bias current supply voltage. Furthermore, a microstrip line 20 is connected to the drain electrode D of the DG/FET 11, and the end thereof is connected to a terminating resistor 22 via a DC blocking capacitor 21 for high frequency matching termination. reflection is prevented.
The line 20 is connected to a power supply +B via a high frequency blocking inductance 23 and a load resistor 24, and an output terminal 25 is led out from a connection point between the inductance 23 and the load resistor 24.

The phase detection circuit shown in FIG. 2 and constructed as described above is expressed as a DC equivalent circuit as shown in FIG. 3. Here, the DG FET 11 has an operational gate bias in which the gate becomes negative with respect to the source (the gate potential becomes lower than the source potential) due to a voltage drop due to the current flowing through the bias resistor 18 connected to the source electrode S. A voltage is applied and the bias is set near the pinch-off voltage to operate the first gate electrode _G1 and the second gate electrode.
A change in the drain current occurs in response to a change in the high frequency input supplied to G ₂ , and an output is obtained at the output terminal 25 based on the change in voltage across the load resistor 24 caused by the change in drain current. be. In this case, in order to increase the ratio of the output change to the above-mentioned high frequency input change, that is, to increase the sensitivity of the circuit, the bias resistor 18 connected to the source electrode S of the DG/FET 11 is The resistance value is made as small as possible. However, if the resistance value of this bias resistor 18 is small, the DG/FET 1 whose bias is set near the pinch-off voltage
Since the current If flowing out from the source of 1 is _small , the necessary gate bias voltage cannot be obtained just by allowing this current to flow through the bias resistor 18. Therefore, through the bias current supply variable resistor 19 connected between one end of the bias resistor 18 and the power supply +B, an additional bias current Ip is flowed from the power supply +B into the bias resistor 18, and the required bias current is determined by the sum If+Ip of both currents. This means that a gate bias voltage of 100% is obtained. This additional bias current Ip can be adjusted by adjusting the bias current supply variable resistor 19.
It is adjusted to a predetermined value, for example, 10 times or more of _If .
This makes it possible to increase the sensitivity of the circuit by reducing the resistance value of the bias resistor 18 connected to the source electrode S of the DG/FET 11, and to obtain the necessary gate bias voltage using this bias resistor 18. There is.

The above-mentioned DG/FET 11 has two gate electrodes, a first and a second gate electrode.
The FET can be thought of as being equivalent to two single-gate field effect transistors (hereinafter simply referred to as FETs) 26 and 27 connected in series with their drain-source paths, as shown in Figure 4A. It will be done. Then, as shown in Figure 4B, FET26 and 2
If the gate electrodes of FET 7 are G ₁ and G ₂ , the source electrode of FET 27 is S, and the drain electrode of FET 26 is D, this equivalently represents DG/FET 11, and the gate electrodes G ₁ and G ₂ input terminal 1 respectively
The circuit of FIG. 4B in which 2a and 13a are connected, the source electrode S is grounded, and the drain electrode D is connected to the load resistor 24 is a high-frequency equivalent circuit representation of the phase detection circuit shown in FIG. It is.

In the circuit shown in FIG. 4B, FET26
The gate-source voltage of FET27 is vg ₁ , the gate-source voltage of FET27 is vg ₂ , the gate-ground voltage of FET26 is v'g ₁ , the drain-source voltage of FET27 is v _d2 , the drain current of FET26 is i _d1 , FET
Let the drain current of 27 be i _d2 .

Since the gate bias voltage of the DG FET 11 is set to be near the pinch-off voltage as described above, the gate bias voltage of the FETs 26 and 27 is also set to be near the pinch-off voltage. In general, when the gate-source voltage of a FET is near the pinch-off voltage Vp, the relationship between the gate-source voltage v _G and the drain current i _D is i _D = α (Vp - k・v _G ) ² (however, α and k are constants) holds true. Therefore, in FIG. 4B, for FET 26, i _d1 = α (Vp ₁ − _{k 1} · vg ₁ ) ² , (α, k ₁ are constants, Vp ₁ is the pinch-off voltage of FET 26) = α {Vp ₁ −k ₁・(v′g ₁ −v _d2 )} ² ...(1) holds true. Here, it is a function F(vg ₂ ) of vg ₂ , and if higher-order terms regarding vg ₂ are omitted, it can be expressed as v _d2 = avg ₂ (where a is a constant)...(2). Substituting equation (2) into equation (1) and expanding, i _d1 = α{Vp ₁ −k ₁・(v ¹ g ₁ −avg ₂ )} ² = α{Vp ₁ ² −2Vp ₁・k ₁ (v ¹ g ₁ −avg ₂ ) +k ₁ ²・v ¹ g ₁ ² −2a・k ₁・v ¹ g ₁・vg ₂ +k ₁ ²・a ²・vg ₂ ² } ...(3).

Here, v ¹ g ₁ and vg ₂ are input terminals 12a and 13
The microwave signals S ₁ and S ₂ supplied to a are
respectively, a first gate electrode G ₁ and a second gate electrode G ₂
This is the voltage value when applied to Now the microwave signal
Assume that there is a phase difference θ between S ₁ and S ₂ , and S ₁ =
If we set cos(ωt+θ) and S=cosωt, then these S ₁
When S 2 and S ₂ are added to the first gate electrode and the second gate electrode, respectively, S ₁ is an odd number multiple of π/ ₂ (π/2・(2n+1), n=0,
1, 2, 3...), so v ¹ g ₁ = cos {ωt+θ+π/2・(2n+1)} =cos(ωt+φ), (however, φ=θ+π/2・(2n+1))... …(4) vg ₂ = cosωt …(5) Substituting equations (4) and (5) into equation (3) and taking the time average _d1 of i _d1 , the high frequency term in equation (3) becomes zero, so _d1 = α{Vp ₁ ² −2a・k ₁・cos(ωt+φ)・cosωt} = α[Vp ₁ ² +a・k ₁・{cos(2ωt+φ)+cosφ}], and cos(2ωt+φ) is also averaged by twice the high frequency term. is zero, so _d1 = α(Vp ₁ ² +a・k ₁・cosφ), and since φ=θ+π/2・(2n+1), _d1 = α(Vp ₁ ² +a・k ₁・sinθ). . That is, _d1 is the DC term and the microwave signal S ₁
It is an odd function with respect to θ, consisting of a term that changes depending on the phase difference θ between S 2 and S ₂ .

Output terminal 2 of the circuit shown in Figs. 2 and 3
The output V _O obtained in 5 is the time averaged value of the drain current of DG FET 11, i.e., the drain current i d1 of FET 26 in Figure 4 _{B, from the power supply voltage V B ,} assuming that the voltage of the power supply + _B is V B. Since it is obtained by subtracting the voltage _{drop caused by} Then, V _O =V _B − _d1・R=(V _B −R・α・V _P1 ² )+α・a・k ₁・sinθ. Therefore, the output obtained at the output terminal 25
V _O is the phase difference θ between the microwave signals S ₁ and S ₂
This output V _O is an odd function with respect to the phase difference θ
In other words, in this case, it is a phase detection output that detects the phase of the microwave signal S ₁ with respect to the phase of the microwave signal S ₂ .

As described above, the circuit shown in FIG. 2 is a circuit in which an output is obtained at the output terminal 25 according to the phase difference between the microwave signals S ₁ and S ₂ supplied to the input terminals 12a and 13a, respectively. It can be seen that it operates as a phase detection circuit.

In this case, as mentioned above, the low resistance value of the bias resistor 18 connected to the source electrode S of the DG/FET 11 is selected to be as small as possible, so that the change in the phase difference θ, that is, the input Output for change
The proportion of change in V _O is considered to be large, and therefore,
High phase detection sensitivity is obtained. There is also a phase detection section to which the microwave signal input is supplied.
Since the first and second gates of the DG FET 11 are formed extremely close to each other on the same semiconductor chip, there are almost no differences in various characteristics between the two gates, and the stability of the phase detection operation is extremely high. Well kept.

FIG. 5 shows a frequency discrimination circuit constructed by applying an example of the phase detection circuit according to the present invention shown in FIG. 2 above. In Figure 5, 28 is the second
The entire phase detection circuit shown in the figure is shown, and each part is given the same number as in FIG. 2, and detailed explanation is omitted. Input terminals 12a and 1 of this phase detection circuit 28
3a have microstrip lines 29 and 3, respectively.
0 are integrally connected. A dielectric resonator 31 having a resonant frequency f _p (for example, 11.66 GHz) is arranged to be coupled to each of these microstrip lines 29 and 30. One end of the microstrip line 29 is an input end 29a
From here, the frequency f _s is given as, for example, f _p =
An input microwave signal S ₃ centered at 11.66 GHz and varying by about ±10 MHz is supplied. In this case, the propagation wavelength λg of the phase detection circuit 28 is as follows:
For example, a wavelength is selected for frequency f _p .

In such a configuration, when the input microwave signal _S3 is supplied to the input end 29a of the line 29, the line 2
9 and the dielectric resonator 31.
The phase detection circuit 28 connected to the line 30 reaches one input end 12a of the phase detection circuit 28 connected to the line 9, and also gets on the line 30 via the coupling part between the line 30 and the dielectric resonator 31. reaches the other input end 13a. At this time, if the microwave signal reaching the input end 12a is S' ₃ and the microwave signal reaching the input end 13a is S'' ₃ , then S' ₃ and S'' ₃
are assumed to have their phases changed inversely to each other by a phase amount corresponding to the frequency f _s of S ₃ . That is,
S' ₃ passing through the coupling part between the line 29 and the dielectric resonator 31 has a frequency f ₃ of the dielectric resonator 31.
When the resonant frequency f _p is the same as that of the dielectric resonator 31
The phase remains unchanged compared to the phase when there is no dielectric resonator 31, but when f _s is lower than f _p , the phase is delayed compared to the phase when there is no dielectric resonator 31, and
When f _s is higher than f _p , the phase advances with respect to the phase without the dielectric resonator 31, and the phase change is in the range of ±π/2 and corresponds to the difference between f _s and f _p . becomes. If this situation is shown with the frequency f _s on the horizontal axis and the phase change relative to the case without the dielectric resonator 31 on the vertical axis, it will become like the broken line in FIG. 6. On the other hand, the line 30 and the dielectric resonator 31
When the frequency f _s is the same as f _p , the phase of S″ ₃ passing through the coupling point with the line 29 and the dielectric resonator 31 does not change with respect to the phase at the coupling point between the line 29 and the dielectric resonator 31.
When f _s is lower than f _p , the phase at the coupling point between the line 29 and the dielectric resonator 31 is advanced, and when f _s is higher than f _p , the phase between the line 29 and the dielectric resonator 31 is advanced. The phase lags behind the phase at the coupling point, and the phase change is in the range of ±π/2 and corresponds to the difference between f _s and f _p . this,
If the frequency f _s is plotted on the horizontal axis and the phase change with respect to the phase at the coupling point between the line 29 and the dielectric resonator 31 is plotted on the vertical axis, the result will be as shown by the solid line in FIG. From this, S′ ₃ and S″ ₃ have a mutual phase difference θ′ corresponding to f _s with f _s =f _p as the center frequency.

This means that the input terminal 12a of the phase detection circuit 28
and 13a are supplied with microwave signals S' ₃ and S'' 3 whose mutual phase difference is the phase difference θ' that changes according to the change in the frequency f _s of the input microwave signal S ₃ , and _the phase detection At the output terminal 25 of the circuit 28, an output V' _O corresponding to the phase difference θ' is obtained by the operation as explained in the circuit shown in FIG. 2. This output V' _O corresponds to the phase difference θ' , i.e., depending on the frequency f _s of the input microwave signal S ₃ ,
The entire circuit shown in FIG. 5 constitutes a frequency discrimination circuit. In this case, the microwave signals S' ₃ and S'' ₃ supplied to the input terminals 12a and 13a of the phase detection circuit 28 change in frequency, and the frequency change is, for example, as follows.
Since f _p is approximately ±10 MHz centered around 11.66 GHz, the influence of the change in the length of the quarter wavelength due to this frequency change on the circuit configuration of the phase detection circuit 28 is as follows.
Virtually negligible.

FIG. 7 shows a portion of another example of the phase detection circuit according to the present invention. In this example, the parts corresponding to the example shown in FIG. 2 are given the same numbers as in FIG. 2, and the explanation thereof is omitted. In place of the variable resistor 19, a transistor 32 is used with its emitter connected to one end of the bias resistor 18 and its collector connected to the power supply +B. Since this transistor 32 is in the form of an emitter follower and supplies current to the bias resistor 18, the potential V _S at one end of the bias resistor 18 connected to its emitter is approximately the base potential V _b of the transistor 32. The change in V _S due to the change in the source current of the DG FET 11 is small. This equivalently means that the resistance value of the bias resistor 18 becomes smaller, and the sensitivity of the circuit improves. Furthermore, by temperature-controlling the base potential V _b of the transistor 32, for example, it is possible to compensate for the temperature of the output obtained at the output terminal 25.

In each of the above examples, the DC blocking capacitor 21 and the terminating resistor 2 used at the end of the line 20 connected to the drain electrode D of the DG/FET 11
It is convenient for the circuit configuration that 2 is a capacitor/resistance integrated component 33 configured as shown in FIGS. 8A and 8B, for example. In the example shown in FIG. 8A, a silicon low resistance layer 35 is formed on one surface of a silicon substrate 34, an insulating layer 36 made of silicon oxide is formed on the silicon substrate 34, and a pair of electrode metal layers 37a and 37b are further formed on the insulating layer 36 made of silicon oxide. is formed and configured. In this case, the electrode metal layers 37a and 3
A capacitor is formed between 7b and the silicon low resistance layer 35, and a resistance is formed between the silicon low resistance layer 35 and the metal layers for both electrodes. Then, for example, the electrode metal layer 37a is connected to the line 20,
The electrode metal layer 37b is grounded and used, and the electrode metal layers 37a and 37b and the silicon low resistance layer 3
5 becomes the DC blocking capacitor 21, and the resistance between the metal layers for both electrodes of the silicon low resistance layer 35 becomes the terminating resistor 22.

In the example shown in FIG. 8B, instead of the silicon low resistance layer 35 in the example shown in FIG. 8A, a thin metal resistance film 38 in an H-shaped pattern is formed on one surface of the silicon substrate 34. The other parts are the same as the example shown in FIG. 8A.

In order to obtain the desired capacitance value in these integrated capacitor and resistor parts, the electrode metal layer 37 is
Areas of a and 37b and silicon oxide insulating layer 3
In addition, in order to obtain the desired amount of resistance, the dimensions of the portion between the metal layers for both electrodes of the silicon low resistance layer 35 or the metal resistance film 38 may be selected.

As explained above, in the phase detection circuit according to the present invention, the phase detection section is composed of a DG/FET which is an active element, and the resistance value of the bias resistor connected to the source thereof is as small as possible. Therefore, the phase detection sensitivity is extremely high. The two gates, to which input microwave signals to be phase-detected are supplied, are formed very close to each other on the same semiconductor chip, so they have the same characteristics and extremely stable operation. It will be done. In addition, in the case of phase detection of a microwave signal, when the phase detection section is configured with a diode as in the past, the reflection characteristics of the diode for microwave signal input change depending on the input power of the input microwave signal. Since the present invention uses a DG-FET, there is almost no dependence of the reflection characteristic on the input power of the microwave signal input, and there is an advantage that the input matching circuit can be easily designed. Furthermore, 1/
Since a 4-wavelength branch line directional coupler etc. is not required,
Another feature is that the overall configuration can be made smaller.

It should be noted that the present invention is not limited to the above-described embodiments, and it goes without saying that various configurations may be adopted without departing from the scope of the invention.

[Brief explanation of drawings]

FIG. 1 is a circuit connection diagram showing a conventional phase detection circuit for microwave signals, FIG. 2 is a circuit connection diagram showing an example of a phase detection circuit according to the present invention, and FIGS.
5 is an equivalent circuit diagram used to explain the phase detection circuit shown in FIG. 2, FIG. 6 is a diagram for explaining the frequency discrimination circuit shown in FIG. 5, FIG. 7 is a circuit connection diagram partially showing another example of the phase detection circuit according to the present invention, and FIG. 8 is a diagram for explaining the frequency discrimination circuit shown in FIG. FIG. 3 is a perspective view showing an example of components that may be used to configure a portion of such a phase detection circuit. In the figure, 1, 2, 12, 13, 16, 20, 29
and 30 is a microstrip line, 3 is a 1/4 wavelength branch line directional coupler, 11 is a multiple gate field effect transistor (DG/FET), 18 is a bias resistor, 19 is a variable resistor for bias current supply,
24 is a load resistor, 26 and 27 are single gate field effect transistors, 31 is a dielectric resonator, 32 is a transistor, and 33 is a capacitor/resistance integrated component.

Claims (1)

[Claims] 1. First and second microstrip lines are connected to the first and second gates of the multi-gate field effect transistor, respectively, and the first and second microstrip lines are connected to their inputs. First and second high-frequency input signals having equal propagation wavelengths are respectively supplied from the ends, and the length from the input end of the first microstrip line to the first gate and the second microstrip line are The length from the input end of the strip line to the second gate is an odd number multiple of 1/4 of the propagation wavelength, and the source of the field effect transistor is connected to the propagation wavelength. An open microstrip line having a length that is an odd multiple of 1/4 of the line is connected to one end of a bias resistor whose other end is grounded, and a predetermined bias current is supplied from the power supply to the bias resistor. Further, the drain of the field effect transistor is connected to a power source via a load, and an output according to a phase difference between the first and second high frequency input signals is generated by a change in voltage at the load. A phase detection circuit obtained based on